Example Configuration
807
SPRUH91D – March 2013 – Revised September 2016
Copyright © 2013–2016, Texas Instruments Incorporated
External Memory Interface B (EMIFB)
Configuring SDRAM Configuration Register (SDCFG)
The SDRAM configuration register (SDCFG) contains register fields that configure the EMIFB memory
controller to match the data bus width, CAS latency, number of banks, and page size of the attached
SDRAM memory. In this example, we assume the following configuration:
•
Data bus width = 32 bits
•
CAS latency = 2
•
Number of banks = 4
•
Page size = 512 words
shows the resulting SDCFG configuration. Note that the value of the TIMUNLOCK field is
dependent on whether or not it is desirable to unlock SDTIM1 and SDTIM2. The TIMUNLOCK bit should
only be set to 1 when the SDTIM1 and SDTIM2 need to be updated.
Table 19-19. SDCFG Configuration
Field
Value
Function Selection
TIMUNLOCK
x
Set to 1 to unlock the SDRAM timing register 1 (SDTIM1) and the SDRAM timing register 2
(SDTIM2). Cleared to 0 to lock SDTIM1 and SDTIM2.
NM
0
To configure the EMIFB memory controller for a 32-bit data bus width.
CL
2h
To select a CAS latency of 2.
IBANK
2h
To select 4 internal SDR SDRAM banks.
PAGESIZE
1h
To select 512-word page size.
Configuring SDRAM Refresh Control Register (SDRFC)
The SDRAM refresh control register (SDRFC) configures the EMIFB memory controller to meet the
refresh requirements of the attached SDRAM device. SDRFC also allows the EMIFB memory controller to
enter and exit self-refresh and power-down and enable and disable the MCLK stopping. In this example,
we assume that the EMIFB memory controller is not is in self-refresh/power-down mode and that MCLK
stopping is disabled. The REFRESH_RATE field in SDRFC is defined as the rate at which the attached
SDRAM device is refreshed in SDRAM cycles.
The value of this field may be calculated using the following equation:
REFRESH_RATE = SDRAM clock frequency × SDRAM refresh rate
Assuming 64 ms (tREF), 8192 rows (2
13
; 13 address lines), SDRAM refresh rate = 64/8192 = 7.8
μ
s.
Therefore, the following results assuming 133-MHz SDRAM clock frequency.
REFRESH_RATE = 133 MHz × 7.8
μ
s = 1037.4 Therefore, REFRESH_RATE = 1038 = 40Eh.
shows the resulting SDRFC configuration.
Table 19-20. SDRFC Configuration
Field
Value
Function Selection
LP_MODE
0
EMIFB memory controller not put in low power mode.
MCLKSTOP_EN
0
MCLK stopping is disabled.
SR_PD
0
This bit is ignored when LP_MODE=0.
REFRESH_RATE
40Eh
Set to 40Eh SDRAM clock cycles to meet the SDRAM memory refresh rate requirement.