X
1
0
X
1
0
Interrupt
enable
register
(IER)
Interrupt pending
register (IPR)
X
1
0
DMA region
access enable 0
(DRAE0)
Eval
pulse
EDMA3CC_INT0
IEVAL0.EVAL
pulse
Eval
X
1
0
(DRAE1)
access enable 1
DMA region
EDMA3CC_INT1
EDMA3CC_INT
n
Eval
pulse
access enable
n
X
1
DMA region
(DRAE )
n
0
IEVAL1.EVAL
IEVAL .EV
n
AL
...
...
Architecture
469
SPRUH91D – March 2013 – Revised September 2016
Copyright © 2013–2016, Texas Instruments Incorporated
Enhanced Direct Memory Access (EDMA3) Controller
Figure 16-12. Interrupt Diagram
Note:
n
is the number of shadow regions supported in the EDMA3CC for a specific device.
NOTE:
The DRAE for all regions is expected to be set up at system initialization and to remain static
for an extended period of time. The interrupt enable registers should be used for dynamic
enable/disable of individual interrupts.
Because there is no relation between the TCC value and the DMA/QDMA channel, it is
possible, for example, for DMA channel 0 to have the OPT.TCC = 31 in its associated
PaRAM set. This would mean that if a transfer completion interrupt is enabled
(OPT.TCINTEN or OPT.ITCINTEN is set), then based on the TCC value, IPR.E31 is set up
on completion. For proper channel operations and interrupt generation using the shadow
region map, you must program the DRAE that is associated with the shadow region to have
read/write access to both bit 0 (corresponding to channel 0) and bit 31 (corresponding to
IPR.E31 bit that is set upon completion).
16.2.9.1.2 Clearing Transfer Completion Interrupts
Transfer completion interrupts that are latched to the interrupt pending register (IPR) is cleared by writing
a 1 to the corresponding bit in the interrupt pending clear register (ICR). For example, a write of 1 to
ICR.E0 clears a pending interrupt in IPR.E0.
If an incoming transfer completion code (TCC) gets latched to a bit in IPR, then additional bits that get set
due to a subsequent transfer completion will not result in asserting the EDMA3CC completion interrupt. In
order for the completion interrupt to be pulsed, the required transition is from a state where no enabled
interrupts are set to a state where at least one enabled interrupt is set.