Architecture
784
SPRUH91D – March 2013 – Revised September 2016
Copyright © 2013–2016, Texas Instruments Incorporated
External Memory Interface B (EMIFB)
Table 19-1. EMIF Pins Used to Access SDRAM (continued)
Pins(s)
I/O
Description
EMB_CAS
O
Active-low column address strobe pin.
This pin is connected to the CAS pin of the attached SDRAM device and is used for sending
commands to the device.
EMB_SDCKE
O
Clock enable pin.
This pin is connected to the CKE pin of the attached SDRAM device and is used for issuing the
SELF REFRESH command which places the device in self-refresh mode. See
for details.
EMB_CLK
O
SDRAM clock pin.
This pin is connected to the CLK pin of the attached SDRAM device. See
for
details on the clock signal.
19.2.4 Pin Multiplexing
Refer to device-specific data manual for pin multiplexing details.
19.2.5 Memory Map
See your device-specific data manual for information describing the device memory-map.
19.2.6 SDRAM Controller and Interface
The EMIFB can gluelessly interface to most standard SDR SDRAM devices and support such features as
self-refresh mode and prioritized refresh. In addition, it provides flexibility through programmable
parameters such as the refresh rate, CAS latency, and many SDRAM timing parameters. The following
sections include details on how to interface and properly configure the EMIFB to perform read and write
operations to externally connected SDR SDRAM devices.
19.2.6.1 SDRAM Commands
The EMIFB supports the SDRAM commands described in
.
shows the truth table for
the SDRAM commands, and an example timing waveform of the PRE command is shown in
.
EMB_A[10] is pulled low in this example to deactivate only the bank specified by the EMB_BA pins.
Table 19-2. EMIF SDRAM Commands
Command
Function
PRE
Precharge.
Depending on the value of EMB_A[10], the PRE command either deactivates the open row in all banks
(EMB_A[10] = 1) or only the bank specified by the EMB_BA[1:0] pins (EMB_A[10] = 0).
ACTV
Activate
. The ACTV command activates the selected row in a particular bank for the current access.
READ
Read.
The READ command outputs the starting column address and signals the SDRAM to begin the burst read
operation. Address EMB_A[10] is always pulled low to avoid auto precharge. This allows for better bank
interleaving performance.
WRT
Write.
The WRT command outputs the starting column address and signals the SDRAM to begin the burst write
operation. Address EMB_A[10] is always pulled low to avoid auto precharge. This allows for better bank
interleaving performance.
BT
Burst terminate
. The BT command is used to truncate the current read or write burst request.
LMR
Load mode register
. The LMR command sets the mode register of the attached SDRAM devices and is only
issued during the SDRAM initialization sequence described in
REFR
Auto refresh
. The REFR command signals the SDRAM to perform an auto refresh according to its internal
address.
SLFR
Self refresh
. The self refresh command places the SDRAM into self-refresh mode, during which it provides its own
clock signal and auto refresh cycles.
NOP
No operation
. The NOP command is issued during all cycles in which one of the above commands is not issued.