PLLC Registers
121
SPRUH91D – March 2013 – Revised September 2016
Copyright © 2013–2016, Texas Instruments Incorporated
Phase-Locked Loop Controller (PLLC)
7.4
PLLC Registers
lists the memory-mapped registers for the PLLC.
(1)
This register is not supported on the C6745 DSP.
Table 7-2. PLL Controller (PLLC) Registers
Address
Acronym
Register Description
Section
01C1 1000h
REVID
Revision Identification Register
01C1 10E4h
RSTYPE
Reset Type Status Register
01C1 1100h
PLLCTL
PLL Control Register
01C1 1104h
OCSEL
(1)
OBSCLK Select Register
01C1 1110h
PLLM
PLL Multiplier Control Register
01C1 1114h
PREDIV
PLL Pre-Divider Control Register
01C1 1118h
PLLDIV1
PLL Controller Divider 1 Register
01C1 111Ch
PLLDIV2
PLL Controller Divider 2 Register
01C1 1120h
PLLDIV3
PLL Controller Divider 3 Register
01C1 1124h
OSCDIV
(1)
Oscillator Divider 1 Register (OBSCLK)
01C1 1128h
POSTDIV
PLL Post-Divider Control Register
01C1 1138h
PLLCMD
PLL Controller Command Register
01C1 113Ch
PLLSTAT
PLL Controller Status Register
01C1 1140h
ALNCTL
PLL Controller Clock Align Control Register
01C1 1144h
DCHANGE
PLLDIV Ratio Change Status Register
01C1 1148h
CKEN
Clock Enable Control Register
01C1 114Ch
CKSTAT
Clock Status Register
01C1 1150h
SYSTAT
SYSCLK Status Register
01C1 1160h
PLLDIV4
PLL Controller Divider 4 Register
01C1 1164h
PLLDIV5
PLL Controller Divider 5 Register
01C1 1168h
PLLDIV6
PLL Controller Divider 6 Register
01C1 116Ch
PLLDIV7
PLL Controller Divider 7 Register
01C1 11F0h
EMUCNT0
Emulation Performance Counter 0 Register
01C1 11F4h
EMUCNT1
Emulation Performance Counter 1 Register