PLLC Registers
123
SPRUH91D – March 2013 – Revised September 2016
Copyright © 2013–2016, Texas Instruments Incorporated
Phase-Locked Loop Controller (PLLC)
7.4.3 PLL Control Register (PLLCTL)
The PLL control register (PLLCTL) is shown in
and described in
.
Figure 7-4. PLL Control Register (PLLCTL)
31
16
Reserved
R-0
15
9
8
7
6
5
4
3
2
1
0
Reserved
CLKMODE
Reserved
PLLENSRC
Reserved
PLLRST
Rsvd
PLLPWRDN
PLLEN
R-0
R/W-0
R-1
R/W-1
R/W-1
R/W-0
R-0
R/W-1
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 7-5. PLL Control Register (PLLCTL) Field Descriptions
Bit
Field
Value
Description
31-9
Reserved
0
Reserved
8
CLKMODE
Reference Clock Selection
0
Internal oscillator (crystal)
1
Square wave
7-6
Reserved
1
Reserved
5
PLLENSRC
0
This bit must be cleared before PLLEN will have any effect.
4
Reserved
1
Reserved. Write the default value when modifying this register.
3
PLLRST
Asserts RESET to PLL if supported.
0
PLL reset is asserted
1
PLL reset is not asserted
2
Reserved
0
Reserved
1
PLLPWRDN
PLL power-down.
0
PLL operation
1
PLL power-down
0
PLLEN
PLL mode enables.
0
Bypass mode
1
PLL mode, not bypassed