PLLC Registers
133
SPRUH91D – March 2013 – Revised September 2016
Copyright © 2013–2016, Texas Instruments Incorporated
Phase-Locked Loop Controller (PLLC)
7.4.18 PLL Controller Clock Align Control Register (ALNCTL)
The PLL controller clock align control register (ALNCTL) is shown in
and described in
. Indicates which SYSCLKs need to be aligned for proper device operation.
Figure 7-19. PLL Controller Clock Align Control Register (ALNCTL)
31
16
Reserved
R-0
15
7
6
5
4
3
2
1
0
Reserved
ALN7
ALN6
ALN5
ALN4
ALN3
ALN2
ALN1
R-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 7-20. PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions
Bit
Field
Value
Description
31-7
Reserved
0
Reserved
6
ALN7
SYSCLK7 needs to be aligned to others selected in this register.
0
No
1
Yes
5
ALN6
SYSCLK6 needs to be aligned to others selected in this register.
0
No
1
Yes
4
ALN5
SYSCLK5 needs to be aligned to others selected in this register.
0
No
1
Yes
3
ALN4
SYSCLK4 needs to be aligned to others selected in this register.
0
No
1
Yes
2
ALN3
SYSCLK3 needs to be aligned to others selected in this register.
0
No
1
Yes
1
ALN2
SYSCLK2 needs to be aligned to others selected in this register.
0
No
1
Yes
0
ALN1
SYSCLK1 needs to be aligned to others selected in this register.
0
No
1
Yes