Project Planning Manual
SIPART DR20
•
CPU data
Controller cycle time
Smallest integration rate
dy/dt = Kp
∗
xd / Tn
97.8 ms
±
1 %
0.1
∗
0.1. % / 10
4
s
•
A/D conversion
Procedure
Resolution
Zero error
Full-scale error
Linearity error
Temperature influence
Successive approximation,
> 120 conversions per input and averaging
over 20 or 16.67 ms
11 bit
≅
0.06 %
≤
0.2 %
≤
0.2 %
≤
0.2 %
≤
0.2 % / 10 K
•
Displays
-
w/x display
Color/digit height
Display range
Decimal point
Repetition rate
Resolution
Display error
-
xd- display
Length of display
Display range
Resolution
Resolution around xd = 0
Repetition rate
-
y display
Color/digit height
Display range
Repetition rate
Resolution
Display error
four-digit, 7-segment display
red / 7 mm
- 1999 to 9999, adjustable
can be fixed
0,1 to 5 s, adjustable together with y display
1 digit, but not better than A/D converter
corresponding to A/D converter and analog
inputs
20 red LEDs, 1 green LED in the center
50.8 mm
±
10 %, can be reprogrammed to
±
2.5 to
±
40%
0.1 of display range
0.05 of display range
0.1 s
two-digit, 7-segment display
red / 7 mm
- 9 to 109 % (100 % = h0
109 % = h9)
0.1 to 5 s, adjustable together with w/x display
1 digit = 1 %
corresponding to A/D converter and analog
inputs
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