Rev. 6.0, 07/02, page x of I
Section
Page
Item
Description
13.1.4 Register Configuration 318
Table 13.2 BSC Registers
Bus control register 3
and 4 added to table,
and Note added
13.1.5 Overview of Areas
320
Table 13.3 External Memory
Space Map
64
*
7
added to Area 0, 5,
6 Settable Bus Widths,
and Note 7 added
319
Space Divisions
Description amended
320
Table 13.3 External Memory
Space Map
Table amended, and
Notes amended and
added
321, 322
Memory Bus Width
Description added
13.2.1 Bus Control Register
1 (BCR1)
326
Bit table
Bit 18 amended and
note added
327
Bit 31, Bit 30, Bit 29
Description added
328
Bit 26
330
Bit 16
Description and notes
added
330
Bit 15, Bit 14
Description amended
331
Bits 13 to 11
332
Bits 10 to 8
333
Bits 7 to 5
Table amended and
note added
334
Bit 0
Description amended
13.2.2 Bus Control Register
2 (BCR2)
335
Bits 15, 14
Description added
337
Newly added
13.2.3 Bus Control Register
3 (BCR3) (SH7750R Only)
338
Bits 12 to 1—Reserved
Description added
13.2.4 Bus Control Register
4 (BCR4)
338,
339
Newly added
13.2.5 Wait Control Register
1 (WCR1)
342
Note amended
13.2.6 Wait Control Register
2 (WCR2)
344 to
349
Bits 31 to 29, Bits 25 to 23,
Bits 19 to 17, Bits 15 to 13,
Bits 11 to 9, Bits 8 to 6,
Bits 5 to 3, and Bits 2 to 0
Description added and
amended
13.2.7 Wait Control Register
3 (WCR3)
351
Bit table
Bits 19 and 7 changed,
and Note added
351
Description added
Summary of Contents for SH7750 series
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