Rev. 6.0, 07/02, page 951 of 986
Appendix E Pin Functions
E.1
Pin States
Table E.1
Pin States in Reset, Power-Down State, and Bus-Released State
Reset
(Power-On)
Reset
(Manual)
Signal Name
I/O
Master Slave
Master Slave
Standby
Bus
Released
Hard-
ware
Standby Notes
D0–D7
I/O
Z
*
15
Z
*
15
Z
*
15
Z
*
15
Z
*
15
Z
*
15
Z
D8–D15
I/O
Z
*
15
Z
*
15
Z
*
15
Z
*
15
Z
*
15
Z
*
15
Z
D16–D23
I/O
Z
*
15
Z
*
15
Z
*
15
Z
*
15
Z
*
15
Z
*
15
Z
D24–D31
I/O
Z
*
15
Z
*
15
Z
*
15
Z
*
15
Z
*
15
Z
*
15
Z
D32–D51
I/O
Z
*
15
Z
*
15
ZK
*
15
ZK
*
15
Z
*
15
K
Z
*
15
K
Z
Output
state held
when used
as port
D52–D55
I/O
Z
*
15
Z
*
15
Z
*
15
Z
*
15
Z
*
15
Z
*
15
Z
D56–D63
I/O
Z
*
15
Z
*
15
Z
*
15
Z
*
15
Z
*
15
Z
*
15
Z
A0, A1, A18–A25
O
Z
*
16
Z
*
16
Z
*
14
O
*
17
Z
*
14
Z
*
14
O
*
7
Z
*
14
Z
A2–A17
O
Z
*
16
Z
*
16
Z
*
14
O
*
9
Z
*
14
Z
*
14
O
*
7
Z
*
14
Z
RESET
I
I
I
I
I
I
I
I
BACK
/
BSREQ
O
H
H
H
H
H
O
Z
BREQ
/
BSACK
I
I
*
16
I
*
16
I
*
13
I
*
13
I
*
13
I
*
13
I
BS
O
H
Z
*
16
H
Z
*
14
Z
*
14
H
*
7
Z
*
14
Z
CKE
O
H
H
O
*
6
O
*
6
L
O
*
6
Z
CS6
–
CS0
O
H
Z
*
16
H
Z
*
14
Z
*
14
H
*
7
Z
*
14
Z
RAS
O
H
Z
*
16
O
*
6
Z
*
14
Z
*
14
O
*
5
Z
*
14
O
*
5
Z
RD
/
CASS
O
H
Z
*
16
O
*
6
Z
*
14
Z
*
14
O
*
5
Z
*
14
O
*
5
Z
RD/
WR
O
H
Z
*
16
H
Z
*
14
Z
*
14
H
*
7
Z
*
14
Z
RDY
I
PI
*
16
PI
*
16
I
*
13
I
*
13
I
*
13
I
*
13
I
WE7
/
CAS7
/DQM7
O
H
Z
*
16
O
*
6
Z
*
14
Z
*
14
O
*
5
Z
*
14
O
*
5
Z
WE6
/
CAS6
/DQM6
O
H
Z
*
16
O
*
6
Z
*
14
Z
*
14
O
*
5
Z
*
14
O
*
5
Z
WE5
/
CAS5
/DQM5
O
H
Z
*
16
O
*
6
Z
*
14
Z
*
14
O
*
5
Z
*
14
O
*
5
Z
WE4
/
CAS4
/DQM4
O
H
Z
*
16
O
*
6
Z
*
14
Z
*
14
O
*
5
Z
*
14
O
*
5
Z
WE3
/
CAS3
/DQM3
O
H
Z
*
16
O
*
6
Z
*
14
Z
*
14
O
*
5
Z
*
14
O
*
5
Z
Summary of Contents for SH7750 series
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