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Serial
data
MPBT bit cleared to 0, data
written to SCTDR1, and
TDRE flag cleared to 0 by
TEI interrupt handler
Data written to SCTDR1
and TDRE flag cleared
to 0 by TXI interrupt
handler
TXI interrupt
request
TEI interrupt
request
1
1
0
D0 D1
D7
0
0
0
D0 D1
D7
0
D0 D1
D7
1
1
1
Multi-
proces-
sor bit
Multi-
proces-
sor bit
Multi-
proces-
sor bit
Stop
bit
Start
bit
Stop
bit
Stop
bit
Start
bit
Data
Data
Data
Start
bit
TDRE
TEND
One frame
Idle state
(mark state)
Figure 15.14 Example of SCI Transmit Operation (Example with 8-Bit Data,
Multiprocessor Bit, One Stop Bit)
Multiprocessor Serial Data Reception: Figure 15.15 shows a sample flowchart for
multiprocessor serial reception.
Use the following procedure for multiprocessor serial data reception after enabling the SCI for
reception.
Summary of Contents for SH7750 series
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