Rev. 6.0, 07/02, page 15 of 986
Table 1.2
Pin Functions (cont)
Memory Interface
No.
Pin
No.
Pin Name
I/O
Function
Reset
SRAM
DRAM
SDRAM PCMCIA MPX
61
U3
BACK
/
BSREQ
O
Bus
acknowledge/
bus request
62
V3
BREQ
/
BSACK
I
Bus
request/bus
acknowledge
63
W2
D8
I/O
Data
A8
64
Y2
D7
I/O
Data
A7
65
W3
CKE
O
Clock output
enable
CKE
66
V5
VDDQ
Power IO VDD (3.3 V)
67
U5
VSSQ
Power IO GND (0 V)
68
Y3
WE5
/
CAS5
/
DQM5
O
D47–D40
select signal
WE5
CAS5
DQM5
69
W4
WE4
/
CAS4
/
DQM4
O
D39–D32
select signal
WE4
CAS4
DQM4
70
Y4
WE1
/
CAS1
/
DQM1
O
D15–D8 select
signal
WE1
CAS1
DQM1
WE1
71
W5
WE0
/
CAS0
/
DQM0
O
D7–D0 select
signal
WE0
CAS0
DQM0
72
Y5
A17
O
Address
73
V6
VDDQ
Power IO VDD (3.3 V)
74
U6
VSSQ
Power IO GND (0 V)
75
W6
A16
O
Address
76
Y6
A15
O
Address
77
V7
VDD
Power Internal VDD
78
U7
VSS
Power Internal GND
(0 V)
79
W7
A14
O
Address
80
Y7
A13
O
Address
81
V8
VDDQ
Power IO VDD (3.3 V)
82
U8
VSSQ
Power IO GND (0 V)
83
V4
NC
84
W8
A12
O
Address
85
Y8
A11
O
Address
86
W9
A10
O
Address
Summary of Contents for SH7750 series
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