Hitachi SH7750 series, Hardware Manual

Page: 978 / 1037

Rev. 6.0, 07/02, page 928 of 986
Table 22.36 Peripheral Module Signal Timing (3)
HD6417750
VF128
HD6417750
F167
HD6417750
F167I HD6417750
BP200M
* 2 * 3 * 4
Module Item Symbol Min Max Min Max Min Max Unit Figure
TMU,
RTC Timer clock
pulse width
(high) t
TCLKWH
4 — 4 — 4 — Pcyc
*
1
22.61
Timer clock
pulse width
(low) t
TCLKWL
4 — 4 — 4 — Pcyc
*
1
22.61
Timer clock
rise time t
TCLKr
— 0.8 — 0.8 — 0.8 Pcyc
* 1
22.61
Timer clock
fall time t
TCLKf
— 0.8 — 0.8 — 0.8 Pcyc
* 1
22.61
Oscillation
settling time t
ROSC
— 3 — 3 — 3 s 22.62
SCI Input clock
cycle (asyn-
chronous) t
Scyc
4 — 4 — 4 — Pcyc
*
1
22.63
Input clock
cycle (syn-
chronous) t
Scyc
6 — 6 — 6 — Pcyc
* 1
22.63
Input clock
pulse width t
SCKW
0.4 0.6 0.4 0.6 0.4 0.6 t
Scyc
22.63
Input clock
rise time t
SCKr
— 0.8 — 0.8 — 0.8 Pcyc
* 1
22.63
Input clock
fall time t
SCKf
— 0.8 — 0.8 — 0.8 Pcyc
*
1
22.63
Transfer data
delay time t
TXD
1.3 10 1.3 8 1.2 6 ns 22.64
Receive data
setup time
(synchronous) t
RXS
16 — 16 — 16 — ns 22.64
Receive data
hold time
(synchronous) t
RXH
16 — 16 — 16 — ns 22.64
I/O
ports Output data
delay time t
PORTD
0.5 10 0.5 8 0.5 6 ns 22.65
Input data
setup time t
PORTS
3.5 — 3.5 — 3 — ns 22.65
Input data
hold time t
PORTH
1.5 — 1.5 — 1.5 — ns 22.65