Rev. 6.0, 07/02, page 971 of 986
(17)
BUS 64
(128M: 4M × 8b × 4) × 8 (SH7750R only)
AMX 6
128M, column-addr-10bit
128MB
AMXEXT0
SH7750 Series Address Pins
RAS Cycle
CAS Cycle
Synchronous DRAM
Address Pins
Function
A16
A26
A26
A13
A15
A25
A25
A12
BANK selects bank address
A14
A24
0
A11
A13
A23
H/L
A10
Address precharge setting
A12
A22
A12
A9
A11
A21
A11
A8
A10
A20
A10
A7
A9
A19
A9
A6
A8
A18
A8
A5
A7
A17
A7
A4
A6
A16
A6
A3
A5
A15
A5
A2
A4
A14
A4
A1
A3
A13
A3
A0
Address
A2
Not used
A1
Not used
A0
Not used
Summary of Contents for SH7750 series
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