Hitachi SH7750 series, Hardware Manual

Page: 66 / 1037

Rev. 6.0, 07/02, page 16 of 986
Table 1.2 Pin Functions (cont)
Memory Interface
No.
Pin
No.
Pin Name I/O Function Reset
SRAM DRAM SDRAM PCMCIA MPX
87 V9 VDDQ Power IO VDD (3.3 V)
88 U9 VSSQ Power IO GND (0 V)
89 Y9 A9 O Address
90 W10 A8 O Address
91 Y10 A7 O Address
92 Y11 CKIO O Clock output CKIO
93 V10 VDDQ Power IO VDD (3.3 V)
94 U10 VSSQ Power IO GND (0 V)
95 W11 CKIO2 O CKIO
*
1
CKIO
96 Y12 A6 O Address
97 W12 A5 O Address
98 Y13 A4 O Address
99 V11 VDDQ Power IO VDD (3.3 V)
100 U11 VSSQ Power IO GND (0 V)
101 W13 A3 O Address
102 Y14 A2 O Address
103 V12 DRAK1 O DMAC1
request
acknowledge
104 U13 DRAK0 O DMAC0
request
acknowledge
105 V13 VDDQ Power IO VDD (3.3 V)
106 U12 VSSQ Power IO GND (0 V)
107 W14
CS3
O Chip select 3
CS3
(
CS3
)
CS3 CS3
108 Y15
CS2
O Chip select 2
CS2
(
CS2
)
CS2 CS2
109 V14 VDD Power Internal VDD
110 U14 VSS Power Internal GND
(0 V)
111 W15
RAS
O
RAS RAS RAS
112 Y16
RD
/
CASS
/
FRAME
O Read/
CAS
/
FRAME
OE CAS OE FRAME
113 V15 VDDQ Power IO VDD (3.3 V)
114 U15 VSSQ Power IO GND (0 V)