Rev. 6.0, 07/02, page 932 of 986
t
DBQH
t
DBQS
CKIO
D63 to D0
(READ)
DBREQ
BAVL
TR
t
BAVD
t
BAVD
t
TRH
(2)
t
TRS
t
DTRH
t
DTRS
(1)
(1): [2CKIO cycle – t
DTRS
] (= 18 ns: 100 MHz)
(2): DTR = 1CKIO cycle (= 10 ns: 100 MHz)
(t
DTRS
+ t
DTRH
) < DTR < 10 ns
Figure 22.66(b)
DBREQ
DBREQ
DBREQ
DBREQ
/
TR
TR
TR
TR
Input Timing and
BAVL
BAVL
BAVL
BAVL
Output Timing
t
TCKcyc
t
TCKH
t
TCKL
t
TCKr
t
TCKf
1/2V
DDQ
V
IH
V
IH
V
IL
V
IL
V
IH
1/2V
DDQ
Note: When clock is input from TCK pin
Figure 22.67 TCK Input Timing
/
BRKACK
SCK2/
t
ASEBRKH
t
ASEBRKS
t
ASEBRKS
t
ASEBRKH
(Low)
(High)
Figure 22.68
RESET
RESET
RESET
RESET
Hold Timing
Summary of Contents for SH7750 series
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