Hitachi SH7750 series, Hardware Manual

Page: 902 / 1037

Rev. 6.0, 07/02, page 852 of 986
Table 22.29 Clock and Control Signal Timing (HD6417750BP200M, HD6417750SBP200)
V
DDQ
= 3.0 to 3.6 V, V
DD
= 1.5 V, T
a
= –20 to +75
°
C, C
L
= 30 pF
Item Symbol Min Max Unit Figure
1/2 divider
operating f
EX
16 67 MHz PLL2
operating
1/2 divider not
operating f
EX
8 34
1/2 divider
operating f
EX
2 67
EXTAL
clock input
frequency
PLL2 not
operating
1/2 divider not
operating f
EX
1 34
EXTAL clock input cycle time t
EXcyc
15 1000 ns 22.1
EXTAL clock input low-level pulse width t
EXL
3.5 — ns 22.1
EXTAL clock input high-level pulse width t
EXH
3.5 — ns 22.1
EXTAL clock input rise time t
EXr
— 4 ns 22.1
EXTAL clock input fall time t
EXf
— 4 ns 22.1
PLL2 operating f
OP
25 100 MHz CKIO clock
output
PLL2 not operating f
OP
1 100 MHz
CKIO clock output cycle time t
cyc
10 1000 ns 22.2(1)
CKIO clock output low-level pulse width t
CKOL1
1 — ns 22.2(1)
CKIO clock output high-level pulse width t
CKOH1
1 — ns 22.2(1)
CKIO clock output rise time t
CKOr
— 3 ns 22.2(1)
CKIO clock output fall time t
CKOf
— 3 ns 22.2(1)
CKIO clock output low-level pulse width t
CKOL2
3 — ns 22.2(2)
CKIO clock output high-level pulse width t
CKOH2
3 — ns 22.2(2)
Power-on oscillation settling time t
OSC1
10 — ms 22.3, 22.5
Power-on oscillation settling time/mode
settling t
OSCMD
10 — ms 22.3, 22.5
SCK2 reset setup time t
SCK2RS
20 — ns 22.11
SCK2 reset hold time t
SCK2RH
20 — ns 22.3, 22.5, 22.11
MD reset setup time t
MDRS
3 — t
cyc
22.12
MD reset hold time t
MDRH
20 — ns 22.3, 22.5, 22.12
RESET
assert time t
RESW
20 — t
cyc
22.3, 22.4, 22.5,
22.6, 22.11
PLL synchronization settling time t
PLL
200 —
µ
s 22.9, 22.10