Rev. 6.0, 07/02, page 238 of 986
9.8.2
In Exit from Standby Mode
Standby
→
→
→
→
Interrupt
CKIO
STATUS
Normal
Standby
Normal
WDT count
Oscillation stops
Interrupt request
WDT overflow
Figure 9.3 STATUS Output in Standby
→
→
→
→
Interrupt Sequence
Standby
→
→
→
→
Power-On Reset
Reset
CKIO
*
1
STATUS
Normal
Reset
Normal
0–10 Bcyc
Standby
Oscillation stops
SCK2
*
2
0–30 Bcyc
Notes:
*
1 When standby mode is exited by means of a power-on reset, a WDT count is not
performed. Hold
low for the PLL oscillation stabilization time.
*
2 Undefined
Figure 9.4 STATUS Output in Standby
→
→
→
→
Power-On Reset Sequence
Summary of Contents for SH7750 series
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