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Hitachi SH7750 series Hardware Manual Download Page 673

Rev. 6.0, 07/02, page 623 of 986

15.3.2

Operation in Asynchronous Mode

In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the
start of communication and followed by one or two stop bits indicating the end of communication.
Serial communication is thus carried out with synchronization established on a character-by-
character basis.

Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex
communication. Both the transmitter and the receiver also have a double-buffered structure, so
that data can be read or written during transmission or reception, enabling continuous data
transfer.

Figure 15.5 shows the general format for asynchronous serial communication.

In asynchronous serial communication, the transmission line is usually held in the mark state (high
level). The SCI monitors the transmission line, and when it goes to the space state (low level),
recognizes a start bit and starts serial communication.

One serial communication character consists of a start bit (low level), followed by data (in LSB-
first order), a parity bit (high or low level), and finally one or two stop bits (high level).

In asynchronous mode, the SCI performs synchronization at the falling edge of the start bit in
reception. The SCI samples the data on the eighth pulse of a clock with a frequency of 16 times
the length of one bit, so that the transfer data is latched at the center of each bit.

Serial 
data

(LSB)

7 or 8 bits

One unit of transfer data (character or frame)

Parity
bit

1 bit, 
or none

1 or 
2 bits

Stop 
bit(s)

1

1

0

D0

D1

D2

D3

D4

D5

D6

D7

0/1

1

1

Idle state (mark state)

Start 
bit

1 bit

(MSB)

Transmit/receive data

Figure 15.5   Data Format in Asynchronous Communication (Example with 8-Bit Data,

Parity, Two Stop Bits)

Data Transfer Format

Table 15.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12
transfer formats can be selected according to the SCSMR1 setting.

Summary of Contents for SH7750 series

Page 1: ...Hitachi SuperH RISC engine SH7750 Series SH7750 SH7750S SH7750R Hardware Manual ADE 602 124E Rev 6 0 7 10 2002 Hitachi Ltd ...

Page 2: ...of bodily injury such as aerospace aeronautics nuclear power combustion control transportation traffic safety equipment or medical equipment for life support 4 Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating operating supply voltage range heat radiation characteristics installation conditions and other characteristics Hita...

Page 3: ...se this manual basic knowledge of electric circuits logic circuits and microcomputers is required Purpose This manual provides the information of the hardware functions and electrical characteristics of the SH7750 SH7750S and SH7750R The SH 4 Programming Manual contains detailed information of executable instructions Please read the Programming Manual together with this manual How to Use the Book ...

Page 4: ...r manuals for development tools Name of Document Document No C C Compiler Assembler Optimizing Linkage Editor User s Manual ADE 702 246 Simulator Debugger User s Manual ADE 702 186 Hitachi Embedded Workshop User s Manual ADE 702 201 ...

Page 5: ...TMU SH7750R table added to Product lineup Notes 1 2 3 added 1 2 Block Diagram 9 Figure 1 1 Block Diagram of SH7750 Series Functions I cache 8 KB and 0 cache 16 KB deleted from table 1 3 Pin Arrangement 10 to 12 Figure 1 2 to 1 4 SH7750R added and description amended 1 4 Pin Functions 13 to 40 Table 1 2 to 1 4 Table and note amended 2 7 Processor Modes 55 Description deleted 3 2 Register Descriptio...

Page 6: ...uration Description added 101 Figure 4 3 Configuration of Operand Cache SH7750R Newly added 4 3 6 RAM Mode 106 to 107 Description amended and added 4 3 7 OC Index Mode 107 Description added 4 4 1 Configuration 109 Figure 4 5 amended to figure 4 6 description added and amended 110 Figure 4 7 Configuration of Instruction Cache SH7750R Newly added 4 6 Memory Mapped Cache Configuration SH7750R 116 New...

Page 7: ...nction in table and amended 9 2 2 Peripheral Module Pin High Impedance Control 226 Other information Description amended 9 2 3 Peripheral Module Pin Pull Up Control 226 Other Information Added 9 2 4 Standby Control Register 2 STBCR2 227 Bit table Bit 6 amended to STHZ and bit 1 to MSTP6 note added 227 Bit 6 Bits 1 and 0 Description added 9 2 5 Clock Stop Register 00 CLKSTP00 SH7750R Only 228 229 N...

Page 8: ...50 SH7750S Table amended and Note amended and added 253 Table 10 3 2 Clock Operating Modes SH7750R Newly added 254 Table 10 4 FRQCR Settings and Internal Clock Frequencies Table and Note amended 10 8 2 Watchdog Timer Control Status Register WTCSR 261 Description amended 10 10 Notes on Board Design 265 When Using a PLL Oscillator Circuit Description amended 266 Figure 10 5 Points for Attention when...

Page 9: ... Diagram of TMU amended 12 1 4 Register Configuration 293 294 Table 12 2 TMU Registers Description and Note added 12 2 3 Timer Start Register 2 TSTR2 297 Added 12 2 4 Timer Constant Registers TCOR 298 Description amended and added 12 2 5 Timer Counters TCNT 298 299 Description amended and added 12 2 6 Timer Control Registers TCR 299 Description amended and added 12 3 1 Counter Operation 304 Descri...

Page 10: ...n added 328 Bit 26 330 Bit 16 Description and notes added 330 Bit 15 Bit 14 Description amended 331 Bits 13 to 11 332 Bits 10 to 8 333 Bits 7 to 5 Table amended and note added 334 Bit 0 Description amended 13 2 2 Bus Control Register 2 BCR2 335 Bits 15 14 Description added 337 Newly added 13 2 3 Bus Control Register 3 BCR3 SH7750R Only 338 Bits 12 to 1 Reserved Description added 13 2 4 Bus Control...

Page 11: ...SRAM interface 387 Basic Timing Description amended 388 393 to 395 Figures 13 6 13 11 to 13 13 Notes added 395 Read Strobe Negate Timing Setting Only Possible in the SH7750R Description added and amended 13 3 4 DRAM Interface 400 to 408 Figures 13 17 to 13 22 Notes added 13 3 5 Synchronous DRAM Interface 413 Connection of Synchronous DRAM Description added 415 Address Multiplexing Description amen...

Page 12: ...d 457 to 472 Figures 13 57 to 13 72 Notes added 473 Description amended 13 3 9 Byte Control SRAM Interface 475 to 477 Figures 13 74 to 13 76 Notes added 13 3 10 Waits between Access Cycles 479 Figure 13 77 Waits between Access Cycles Replaced 13 3 11 Bus Arbitration 480 481 Description added and amended 13 3 16 Notes on Usage 487 Refresh Bus Arbitration Description amended 487 Synchronous DRAM Mod...

Page 13: ...ransfer 526 Table 14 9 External Request Transfer Sources and Destinations in DDT Mode Usable DMAC channels changed 525 a Normal DMA Mode Description amendment 14 3 5 Number of Bus Cycle States and DREQ Pin Sampling Timing 533 to 535 Figure 14 15 to 14 17 Figure description added 14 5 On Demand Data Transfer Mode DDT Mode 545 Description amendments 14 5 2 Pins in DDT Mode 547 BAVL Data bus D63 D0 r...

Page 14: ...ription changed 672 Bit 3 Framing Error FER Description changed 672 Bit 2 Parity Error PER Description changed 16 2 9 FIFO Control Register SCFCR2 676 Bits 10 to 8 SH7750R added 16 2 11 Serial Port Register SCSPTR2 Figure 16 6 MRESET SCK2 Pin Deleted 16 3 2 Serial Operation 689 Figure 16 6 Sample SCIF Initialization Flowchart Amended 696 Serial Data Reception Description added to 5 17 1 Overview 7...

Page 15: ...766 Newly added 19 3 6 Interrupt Mask Clear Register 00 INTMSKCLR00 SH7750R Only 767 Newly added 19 3 7 Bit Assignments of INTREQ00 INTMSK00 and INTMSKCLR00 SH7750R Only 767 19 3 4 moved to 19 3 7 19 4 1 Interrupt Operation Sequence 768 Note 3 added 19 5 Interrupt Response Time 771 Note amended 20 2 4 Break Address Mask Register BAMRA 778 779 Bit 2 and Bits 3 1 and 0 Description added 20 2 10 Brea...

Page 16: ...y added 21 3 3 H UDI Interrupt 811 Description changed 21 3 4 BYPASS Deleted 21 3 4 Boundary Scan EXTEST SAMPLE PRELOAD BYPASS 812 Newly added 21 4 Usage Notes 812 5 Description added 22 1 Absolute Maximum Ratings 813 Table 22 1 Absolute Maximum Ratings Table amended and notes amended 22 2 DC Characteristics 814 815 Table 22 2 DC Characteristics HD6417750RBP240 Newly added 816 817 Table 22 3 DC Ch...

Page 17: ...0SBP200 HD6417750RBP200 HD6417750RBP200 clock timing added 842 Table 22 20 Clock Timing HD6417750RF200 Newly added 842 Table 22 21 Clock Timing HD6417750SF200 Amended 843 Table 22 22 Clock Timing HD6417750F167 HD6417750F167I HD6417750SF167 HD6417750SF167I Amended 843 Table 22 23 Clock Timing HD6417750SVF133 HD6417750SVBT133 Amended 843 Table 22 24 Clock Timing HD6417750VF128 Amended 22 3 1 Clock a...

Page 18: ... Timing HD6417750SVF133 HD6417750SVBT133 Amended 860 861 Table 22 33 Clock and Control Signal Timing HD6417750VF128 Amended 864 Figure 22 6 Standby Return Oscillation Settling Time Return by RESET Amended 865 Figure 22 8 Standby Return Oscillation Settling Time Return by IRL3 IRL0 Amended 866 Figure 22 10 PLL Synchronization Settling Time in Case of IRL Interrupt Amended 22 3 2 Control Signal Timi...

Page 19: ...TC CPG TMU table added Appendix B Package Dimensions 943 944 Figure B 1 Package Dimensions 256 Pin BGA Figure B 2 Package Dimensions 208 Pin QFP Amended Appendix C Mode Pin Settings 946 Clock Modes Table 10 3 1 2 inserted 947 Area 0 Bus Width Area 0 memory type deleted and data integrated into area 0 bus width table Appendix D CKIO2ENB Pin Configuration 948 Figure D 1 CKIO2ENB Pin Configuration Am...

Page 20: ...iplexing Tables 972 973 19 BUS 32 128M 4M 8b 4 4 SH7750S and SH7750R only 20 BUS 32 256M 4M 16b 4 2 SH7750S and SH7750R only SH7750R added Appendix H Power On and Power Off Procedures 977 to 979 Newly added Appendix I Product Code Lineup 980 Table I 1 SH7750 Series Product Code Lineup SH7750R added ...

Page 21: ...Control Registers 49 2 2 5 System Registers 50 2 3 Memory Mapped Registers 52 2 4 Data Format in Registers 53 2 5 Data Formats in Memory 53 2 6 Processor States 54 2 7 Processor Modes 55 Section 3 Memory Management Unit MMU 57 3 1 Overview 57 3 1 1 Features 57 3 1 2 Role of the MMU 57 3 1 3 Register Configuration 60 3 1 4 Caution 60 3 2 Register Descriptions 61 3 3 Address Space 64 3 3 1 Physical ...

Page 22: ...tion 84 3 6 6 Data TLB Protection Violation Exception 85 3 6 7 Initial Page Write Exception 86 3 7 Memory Mapped TLB Configuration 87 3 7 1 ITLB Address Array 88 3 7 2 ITLB Data Array 1 89 3 7 3 ITLB Data Array 2 90 3 7 4 UTLB Address Array 90 3 7 5 UTLB Data Array 1 92 3 7 6 UTLB Data Array 2 93 Section 4 Caches 95 4 1 Overview 95 4 1 1 Features 95 4 1 2 Register Configuration 96 4 2 Register Des...

Page 23: ...7 4 SQ Protection 124 4 7 5 Reading the SQs SH7750R Only 124 4 7 6 SQ Usage Notes 125 Section 5 Exceptions 127 5 1 Overview 127 5 1 1 Features 127 5 1 2 Register Configuration 127 5 2 Register Descriptions 128 5 3 Exception Handling Functions 129 5 3 1 Exception Handling Flow 129 5 3 2 Exception Handling Vector Addresses 129 5 4 Exception Types and Priorities 130 5 5 Exception Flow 132 5 5 1 Excep...

Page 24: ...dressing Modes 175 7 3 Instruction Set 179 Section 8 Pipelining 193 8 1 Pipelines 193 8 2 Parallel Executability 200 8 3 Execution Cycles and Pipeline Stalling 204 Section 9 Power Down Modes 221 9 1 Overview 221 9 1 1 Types of Power Down Modes 221 9 1 2 Register Configuration 223 9 1 3 Pin Configuration 223 9 2 Register Descriptions 224 9 2 1 Standby Control Register STBCR 224 9 2 2 Peripheral Mod...

Page 25: ...w 247 10 1 1 Features 247 10 2 Overview of CPG 249 10 2 1 Block Diagram of CPG 249 10 2 2 CPG Pin Configuration 252 10 2 3 CPG Register Configuration 252 10 3 Clock Operating Modes 253 10 4 CPG Register Description 254 10 4 1 Frequency Control Register FRQCR 254 10 5 Changing the Frequency 257 10 5 1 Changing PLL Circuit 1 Starting Stopping When PLL Circuit 2 is Off 257 10 5 2 Changing PLL Circuit...

Page 26: ...T 273 11 2 6 Day Counter RDAYCNT 274 11 2 7 Month Counter RMONCNT 274 11 2 8 Year Counter RYRCNT 275 11 2 9 Second Alarm Register RSECAR 276 11 2 10 Minute Alarm Register RMINAR 276 11 2 11 Hour Alarm Register RHRAR 277 11 2 12 Day of Week Alarm Register RWKAR 277 11 2 13 Day Alarm Register RDAYAR 278 11 2 14 Month Alarm Register RMONAR 279 11 2 15 RTC Control Register 1 RCR1 279 11 2 16 RTC Contr...

Page 27: ...309 12 5 1 Register Writes 309 12 5 2 TCNT Register Reads 309 12 5 3 Resetting the RTC Frequency Divider 309 12 5 4 External Clock Frequency 309 Section 13 Bus State Controller BSC 311 13 1 Overview 311 13 1 1 Features 311 13 1 2 Block Diagram 313 13 1 3 Pin Configuration 314 13 1 4 Register Configuration 318 13 1 5 Overview of Areas 319 13 1 6 PCMCIA Support 322 13 2 Register Descriptions 326 13 ...

Page 28: ...ring Master Mode 485 13 3 15 Cooperation between Master and Slave 486 13 3 16 Notes on Usage 487 Section 14 Direct Memory Access Controller DMAC 489 14 1 Overview 489 14 1 1 Features 489 14 1 2 Block Diagram SH7750 SH7750S 492 14 1 3 Pin Configuration SH7750 SH7750S 493 14 1 4 Register Configuration SH7750 SH7750S 494 14 2 Register Descriptions SH7750 SH7750S 496 14 2 1 DMA Source Address Register...

Page 29: ...DMA Operation Register DMAOR 583 14 8 Operation SH7750R 586 14 8 1 Channel Specification for a Normal DMA Transfer 586 14 8 2 Channel Specification for DDT Mode DMA Transfer 586 14 8 3 Transfer Channel Notification in DDT Mode 586 14 8 4 Clearing Request Queues by DTR Format 587 14 8 5 Interrupt Request Codes 588 14 9 Usage Notes 591 Section 15 Serial Communication Interface SCI 593 15 1 Overview ...

Page 30: ...erial Mode Register SCSMR2 663 16 2 6 Serial Control Register SCSCR2 665 16 2 7 Serial Status Register SCFSR2 668 16 2 8 Bit Rate Register SCBRR2 674 16 2 9 FIFO Control Register SCFCR2 675 16 2 10 FIFO Data Count Register SCFDR2 678 16 2 11 Serial Port Register SCSPTR2 679 16 2 12 Line Status Register SCLSR2 684 16 3 Operation 685 16 3 1 Overview 685 16 3 2 Serial Operation 686 16 4 SCIF Interrup...

Page 31: ...rial Port Register SCSPTR2 748 Section 19 Interrupt Controller INTC 751 19 1 Overview 751 19 1 1 Features 751 19 1 2 Block Diagram 751 19 1 3 Pin Configuration 753 19 1 4 Register Configuration 753 19 2 Interrupt Sources 754 19 2 1 NMI Interrupt 754 19 2 2 IRL Interrupts 755 19 2 3 On Chip Peripheral Module Interrupts 757 19 2 4 Interrupt Exception Handling and Priority 758 19 3 Register Descripti...

Page 32: ...ask Register B BDMRB 782 20 2 11 Break Bus Cycle Register B BBRB 783 20 2 12 Break Control Register BRCR 783 20 3 Operation 785 20 3 1 Explanation of Terms Relating to Accesses 785 20 3 2 Explanation of Terms Relating to Instruction Intervals 786 20 3 3 User Break Operation Sequence 787 20 3 4 Instruction Access Cycle Break 788 20 3 5 Operand Access Cycle Break 789 20 3 6 Condition Match Flag Sett...

Page 33: ...ge Notes 812 Section 22 Electrical Characteristics 813 22 1 Absolute Maximum Ratings 813 22 2 DC Characteristics 814 22 3 AC Characteristics 842 22 3 1 Clock and Control Signal Timing 844 22 3 2 Control Signal Timing 868 22 3 3 Bus Timing 871 22 3 4 Peripheral Module Signal Timing 924 22 3 5 AC Characteristic Test Conditions 934 22 3 6 Delay Time Variation Due to Load Capacitance 935 Appendix A Ad...

Page 34: ...T 1 68 Figure 3 7 UTLB Configuration 71 Figure 3 8 Relationship between Page Size and Address Format 72 Figure 3 9 ITLB Configuration 75 Figure 3 10 Flowchart of Memory Access Using UTLB 76 Figure 3 11 Flowchart of Memory Access Using ITLB 77 Figure 3 12 Operation of LDTLB Instruction 79 Figure 3 13 Memory Mapped ITLB Address Array 88 Figure 3 14 Memory Mapped ITLB Data Array 1 89 Figure 3 15 Memo...

Page 35: ...in Standby Interrupt Sequence 238 Figure 9 4 STATUS Output in Standby Power On Reset Sequence 238 Figure 9 5 STATUS Output in Standby Manual Reset Sequence 239 Figure 9 6 STATUS Output in Sleep Interrupt Sequence 240 Figure 9 7 STATUS Output in Sleep Power On Reset Sequence 240 Figure 9 8 STATUS Output in Sleep Manual Reset Sequence 241 Figure 9 9 STATUS Output in Deep Sleep Interrupt Sequence 242...

Page 36: ...ta Width SRAM Connection 391 Figure 13 10 Example of 8 Bit Data Width SRAM Connection 392 Figure 13 11 SRAM Interface Wait Timing Software Wait Only 393 Figure 13 12 SRAM Interface Wait State Timing Wait State Insertion by RDY Signal 394 Figure 13 13 SRAM Interface Read Strobe Negate Timing AnS 1 AnW 4 AnH 2 395 Figure 13 14 Example of DRAM Connection 64 Bit Data Width Area 3 396 Figure 13 15 Exam...

Page 37: ...chronous DRAM Mode Write Timing Mode Register Set 437 Figure 13 43 Basic Timing of Synchronous DRAM Burst Read Burst Length 4 438 Figure 13 44 Basic Timing of a Burst Write to Synchronous DRAM 440 Figure 13 45 Example of the Connection of Synchronous DRAM with 64 bit Bus Width 256 Mbits 441 Figure 13 46 Burst ROM Basic Access Timing 442 Figure 13 47 Burst ROM Wait Access Timing 443 Figure 13 48 Bu...

Page 38: ...al Wait Bus Width 32 Bits Transfer Data Size 64 Bytes 467 Figure 13 68 MPX Interface Timing 4 Burst Write Cycle AnW 1 One External Wait Inserted Bus Width 32 Bits Transfer Data Size 64 Bytes 468 Figure 13 69 MPX Interface Timing 5 Burst Read Cycle AnW 0 No External Wait Bus Width 32 Bits Transfer Data Size 32 Bytes 469 Figure 13 70 MPX Interface Timing 6 Burst Read Cycle AnW 0 External Wait Contro...

Page 39: ... Cycle 533 Figure 14 16 Dual Address Mode Cycle Steal Mode On Chip SCI Level Detection External Bus 534 Figure 14 17 Dual Address Mode Cycle Steal Mode External Bus On Chip SCI Level Detection 535 Figure 14 18 Single Address Mode Cycle Steal Mode External Bus External Bus DREQ Level Detection 536 Figure 14 19 Single Address Mode Cycle Steal Mode External Bus External Bus DREQ Edge Detection 537 Fi...

Page 40: ...nnel 0 On Demand Data Transfer 562 Figure 14 42 DDT Mode Setting 563 Figure 14 43 Single Address Mode Burst Mode Edge Detection External Device External Bus Data Transfer 563 Figure 14 44 Single Address Mode Burst Mode Level Detection External Bus External Device Data Transfer 564 Figure 14 45 Single Address Mode Burst Mode Edge Detection Byte Word Longword Quadword External Bus External Device Da...

Page 41: ...it Data Parity One Stop Bit 633 Figure 15 12 Example of Inter Processor Communication Using Multiprocessor Format Transmission of Data H AA to Receiving Station A 635 Figure 15 13 Sample Multiprocessor Serial Transmission Flowchart 636 Figure 15 14 Example of SCI Transmit Operation Example with 8 Bit Data Multiprocessor Bit One Stop Bit 638 Figure 15 15 Sample Multiprocessor Serial Reception Flowc...

Page 42: ...14 Figure 17 5 Sample Start Character Waveforms 715 Figure 17 6 Difference in Clock Output According to GM Bit Setting 717 Figure 17 7 Sample Initialization Flowchart 719 Figure 17 8 Sample Transmission Processing Flowchart 721 Figure 17 9 Sample Reception Processing Flowchart 723 Figure 17 10 Receive Data Sampling Timing in Smart Card Mode 725 Figure 17 11 Retransfer Operation in SCI Receive Mode...

Page 43: ... SRAM Bus Cycle Basic Bus Cycle One Internal Wait One External Wait 879 Figure 22 18 SRAM Bus Cycle Basic Bus Cycle No Wait Address Setup Hold Time Insertion AnS 1 AnH 1 880 Figure 22 19 Burst ROM Bus Cycle No Wait 881 Figure 22 20 Burst ROM Bus Cycle 1st Data One Internal Wait One External Wait 2nd 3rd 4th Data One Internal Wait 882 Figure 22 21 Burst ROM Bus Cycle No Wait Address Setup Hold Time...

Page 44: ... 1 0 01 AnW 2 0 001 TPC 2 0 010 900 Figure 22 38 DRAM Bus Cycle EDO Mode RCD 1 0 00 AnW 2 0 000 TPC 2 0 001 901 Figure 22 39 DRAM Burst Bus Cycle EDO Mode RCD 1 0 00 AnW 2 0 000 TPC 2 0 001 902 Figure 22 40 DRAM Burst Bus Cycle EDO Mode RCD 1 0 01 AnW 2 0 001 TPC 2 0 001 903 Figure 22 41 DRAM Burst Bus Cycle EDO Mode RCD 1 0 01 AnW 2 0 001 TPC 2 0 001 2 Cycle CAS Negate Pulse Width 904 Figure 22 4...

Page 45: ...Wait 3 1st Data One Internal Wait One External Wait 919 Figure 22 57 MPX Bus Cycle Burst Read 1 1st Data One Internal Wait 2nd to 8th Data One Internal Wait 2 1st Data One Internal Wait 2nd to 4th Data One Internal Wait One External Wait 920 Figure 22 58 MPX Bus Cycle Burst Write 1 No Internal Wait 2 1st Data One Internal Wait 2nd to 4th Data No Internal Wait External Wait Control 921 Figure 22 59...

Page 46: ...Pin Functions 31 Table 2 1 Initial Register Values 43 Table 3 1 MMU Registers 60 Table 4 1 Cache Features SH7750 SH7750S 95 Table 4 2 Cache Features SH7750R 95 Table 4 3 Features of Store Queues 96 Table 4 4 Cache Control Registers 96 Table 5 1 Exception Related Registers 127 Table 5 2 Exceptions 130 Table 5 3 Types of Reset 137 Table 6 1 Floating Point Number Formats and Parameters 162 Table 6 2 ...

Page 47: ...23 Table 13 6 MPX Interface is Selected Areas 0 to 6 350 Table 13 7 1 64 Bit External Device Big Endian Access and Data Alignment 372 Table 13 7 2 64 Bit External Device Big Endian Access and Data Alignment 373 Table 13 8 32 Bit External Device Big Endian Access and Data Alignment 374 Table 13 9 16 Bit External Device Big Endian Access and Data Alignment 375 Table 13 10 8 Bit External Device Big E...

Page 48: ... of Bit Rates and SCBRR1 Settings in Asynchronous Mode 615 Table 15 4 Examples of Bit Rates and SCBRR1 Settings in Synchronous Mode 618 Table 15 5 Maximum Bit Rate for Various Frequencies with Baud Rate Generator Asynchronous Mode 619 Table 15 6 Maximum Bit Rate with External Clock Input Asynchronous Mode 620 Table 15 7 Maximum Bit Rate with External Clock Input Synchronous Mode 620 Table 15 8 SCS...

Page 49: ...ns 801 Table 21 2 H UDI Registers 802 Table 21 3 Configuration of the Boundary Scan Register 1 807 Table 21 3 Configuration of the Boundary Scan Register 2 808 Table 21 3 Configuration of the Boundary Scan Register 3 809 Table 22 1 Absolute Maximum Ratings 813 Table 22 2 DC Characteristics HD6417750RBP240 814 Table 22 3 DC Characteristics HD6417750RF240 816 Table 22 4 DC Characteristics HD6417750R...

Page 50: ...17750BP200M HD6417750SBP200 852 Table 22 30 Clock and Control Signal Timing HD6417750SF200 854 Table 22 31 Clock and Control Signal Timing HD6417750F167 HD6417750F167I HD6417750SF167 HD6417750SF167I 856 Table 22 32 Clock and Control Signal Timing HD6417750SVF133 HD6417750SVBT133 858 Table 22 33 Clock and Control Signal Timing HD6417750VF128 860 Table 22 34 Control Signal Timing 1 868 Table 22 34 C...

Page 51: ...he SH7750 Series has an on chip bus state controller BSC that allows connection to DRAM and synchronous DRAM Its 16 bit fixed length instruction set enables program code size to be reduced by almost 50 compared with 32 bit instructions The features of the SH7750 Series are summarized in table 1 1 Table 1 1 SH7750 Series Features Item Features LSI Operating frequency 240 MHz 1 200 MHz 167 MHz 2 3 1...

Page 52: ...ction set upward compatible with SH Series Fixed 16 bit instruction length for improved code efficiency Load store architecture Delayed branch instructions Conditional execution C based instruction set Superscalar architecture providing simultaneous execution of two instructions including FPU Instruction execution time Maximum 2 instructions cycle Virtual address space 4 Gbytes 448 Mbyte external ...

Page 53: ...ecision 8 words 2 banks 32 bit CPU FPU floating point communication register FPUL Supports FMAC multiply and accumulate instruction Supports FDIV divide and FSQRT square root instructions Supports FLDI0 FLDI1 load constant 0 1 instructions Instruction execution times Latency FMAC FADD FSUB FMUL 3 cycles single precision 8 cycles double precision Pitch FMAC FADD FSUB FMUL 1 cycle single precision 6...

Page 54: ...Maximum frequency varies with models Power down modes Sleep mode Standby mode Module standby function Single channel watchdog timer Memory management unit MMU 4 Gbyte address space 256 address space identifiers 8 bit ASIDs Single virtual mode and multiple virtual memory mode Supports multiple page sizes 1 kbyte 4 kbytes 64 kbytes 1 Mbyte 4 entry fully associative TLB for instructions 64 entry full...

Page 55: ...e accessed directly by address mapping usable as on chip memory Store queue 32 bytes 2 entries Cache memory SH7750R Instruction cache IC 16 kbytes 2 way set associative 256 entries way 32 byte block length Cache double mode 16 kbyte cache Index mode SH7750 SH7750S compatible mode 8 kbytes direct mapping Operand cache OC 32 kbytes 2 way set associative 512 entries way 32 byte block length Cache dou...

Page 56: ...e controller BSC Supports external memory access 64 32 16 8 bit external data bus External memory space divided into seven areas each of up to 64 Mbytes with the following parameters settable for each area Bus size 8 16 32 or 64 bits Number of wait cycles hardware wait function also supported Connection of DRAM synchronous DRAM and burst ROM possible by setting space type Supports fast page mode a...

Page 57: ...ts on demand data transfer Timer unit TMU Auto reload 32 bit timer SH7750 SH7750S 3 channel SH7750R 5 channel Input capture function Choice of seven counter input clocks Realtime clock RTC On chip clock and calendar functions Built in 32 kHz crystal oscillator with maximum 1 256 second resolution cycle interrupts Serial communication interface SCI SCIF Two full duplex communication channels SCI SC...

Page 58: ...7 HD6417750F167I 1 5 V 128 MHz HD6417750VF128 208 pin QFP SH7750S 1 95 V 200 MHz HD6417750SBP200 256 pin BGA HD6417750SF200 1 8 V 167 MHz HD6417750SF167 HD6417750SF167I 1 5 V 133 MHz HD6417750SVF133 208 pin QFP HD6417750SVBT133 264 pin CSP SH7750R 1 5 V 240 MHz HD6417750RBP240 256 pin BGA HD6417750RF240 208 pin QFP 200 MHz HD6417750RBP200 256 pin BGA HD6417750RF200 208 pin QFP Notes 1 For SH7750R ...

Page 59: ...heral data bus UBC Lower 32 bit data Lower 32 bit data 32 bit data load 32 bit data store CPU I cache O cache ITLB UTLB Cache and TLB controller FPU 64 bit data store BSC Bus state controller CPG Clock pulse generator DMAC Direct memory access controller FPU Floating point unit INTC Interrupt controller ITLB Instruction TLB translation lookaside buffer UTLB Unified TLB translation lookaside buffer...

Page 60: ... A3 A2 RD DQM2 DQM3 DQM6 DQM7 D23 D24 D22 A B C D E F G H 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 19 20 18 J K L M N P R T U V W Y D47 D46 D45 D44 D43 D42 D32 D33 D34 D35 D36 D37 DRAK0 DRAK1 VSS PLL1 VSS PLL2 A1 A0 RD BGA256 Top view MD2 RXD2 RXD D41 D40 D15 D14 D13 D12 D11 D10 D9 D38 D39 D0 D1 D2 D3 D4 D5 D6 VDDQ IO VSSQ IO VDD internal VSS internal NC CA Note Power must be supplied to the on c...

Page 61: ...01 102 103 104 D8 D7 CKE DQM5 DQM4 DQM1 DQM0 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 CKIO A6 A5 A4 A3 A2 DRAK1 DRAK0 RD DQM2 DQM3 DQM6 DQM7 D23 D24 D22 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 EXTAL XTAL VSS CPG VDD CPG 3 3V VSS PLL...

Page 62: ...1 D37 VSSQ VSSQ D57 D53 D54 D58 VDDQ D39 D0 VSSQ D15 VDDQ D40 D56 VSSQ D31 D16 D55 VDDQ D1 VSS VSSQ VDD VDDQ D14 D30 VSSQ VSS D18 VDDQ D17 D2 D4 D3 VDDQ D13 D14 A9 VDDQ A6 A2 D29 D28 D27 VDDQ D19 VDD VSSQ D5 D11 D12 A16 VDDQ VDDQ A7 A4 DRAK0 VSSQ VSS D26 D21 VDDQ D20 VSSQ VDDQ VDDQ VDD A11 VSSQ VSSQ VSSQ VSSQ D25 D6 D10 CKE A17 VSS A12 A8 VDDQ VDDQ RXD VSSQ D8 VDDQ VSSQ A13 VSSQ CKIO2 A3 VDD RD D2...

Page 63: ...F3 VDDQ Power IO VDD 3 3 V 12 F4 VSSQ Power IO GND 0 V 13 E2 D47 I O Data port Port Port Port Port Port 14 E1 D32 I O Data port Port Port Port Port Port 15 G3 VDD Power Internal VDD 1 8 V 16 G4 VSS Power Internal GND 0 V 17 F2 D46 I O Data port Port Port Port Port Port 18 F1 D33 I O Data port Port Port Port Port Port 19 H3 VDDQ Power IO VDD 3 3 V 20 H4 VSSQ Power IO GND 0 V 21 G2 D45 I O Data port...

Page 64: ... M2 D39 I O Data port Port Port Port Port Port 37 L3 VDDQ Power IO VDD 3 3 V 38 L4 VSSQ Power IO GND 0 V 39 N1 D15 I O Data A15 40 N2 D0 I O Data A0 41 P1 D14 I O Data A14 42 P2 D1 I O Data A1 43 M3 VDDQ Power IO VDD 3 3 V 44 M4 VSSQ Power IO GND 0 V 45 R1 D13 I O Data A13 46 R2 D2 I O Data A2 47 P3 VDD Power Internal VDD 48 P4 VSS Power Internal GND 0 V 49 T1 D12 I O Data A12 50 T2 D3 I O Data A3...

Page 65: ...3 WE5 CAS5 DQM5 O D47 D40 select signal WE5 CAS5 DQM5 69 W4 WE4 CAS4 DQM4 O D39 D32 select signal WE4 CAS4 DQM4 70 Y4 WE1 CAS1 DQM1 O D15 D8 select signal WE1 CAS1 DQM1 WE1 71 W5 WE0 CAS0 DQM0 O D7 D0 select signal WE0 CAS0 DQM0 72 Y5 A17 O Address 73 V6 VDDQ Power IO VDD 3 3 V 74 U6 VSSQ Power IO GND 0 V 75 W6 A16 O Address 76 Y6 A15 O Address 77 V7 VDD Power Internal VDD 78 U7 VSS Power Internal...

Page 66: ...dress 97 W12 A5 O Address 98 Y13 A4 O Address 99 V11 VDDQ Power IO VDD 3 3 V 100 U11 VSSQ Power IO GND 0 V 101 W13 A3 O Address 102 Y14 A2 O Address 103 V12 DRAK1 O DMAC1 request acknowledge 104 U13 DRAK0 O DMAC0 request acknowledge 105 V13 VDDQ Power IO VDD 3 3 V 106 U12 VSSQ Power IO GND 0 V 107 W14 CS3 O Chip select 3 CS3 CS3 CS3 CS3 108 Y15 CS2 O Chip select 2 CS2 CS2 CS2 CS2 109 V14 VDD Power...

Page 67: ...VSSQ Power IO GND 0 V 121 W18 WE7 CAS7 DQM7 REG O D63 D56 select signal WE7 CAS7 DQM7 REG 122 Y19 D23 I O Data A23 123 W19 D24 I O Data A24 124 Y20 D22 I O Data A22 125 V17 RXD I SCI data input 126 U17 DREQ0 I Request from DMAC0 127 U18 DREQ1 I Request from DMAC1 128 W20 D25 I O Data A25 129 T18 VDDQ Power IO VDD 3 3 V 130 T17 VSSQ Power IO GND 0 V 131 V19 D21 I O Data A21 132 V20 D26 I O Data 133...

Page 68: ...154 L20 D57 I O Data 155 L18 VDDQ Power IO VDD 3 3 V 156 L17 VSSQ Power IO GND 0 V 157 K20 D53 I O Data 158 K19 D58 I O Data 159 J20 D52 I O Data 160 J19 D59 I O Data 161 K18 VDDQ Power IO VDD 3 3 V 162 K17 VSSQ Power IO GND 0 V 163 H20 D51 I O Data port Port Port Port Port Port 164 H19 D60 I O Data 165 G20 D50 I O Data port Port Port Port Port Port 166 G19 D61 I O Data ACCSIZE0 167 J18 VDDQ Power...

Page 69: ...D2 TXD2 TXD2 TXD2 TXD2 181 D18 MD2 RXD2 I Mode SCIF data input MD2 RXD2 RXD2 RXD2 RXD2 RXD2 182 C20 IRL0 I Interrupt 0 183 C19 IRL1 I Interrupt 1 184 B20 IRL2 I Interrupt 2 185 C18 IRL3 I Interrupt 3 186 A20 NMI I Nonmaskable interrupt 187 B19 XTAL2 O RTC crystal resonator pin 188 A19 EXTAL2 I RTC crystal resonator pin 189 B18 VSS RTC Power RTC GND 0 V 190 A18 VDD RTC Power RTC VDD 3 3 V 191 D17 C...

Page 70: ...ss 204 B14 A19 O Address 205 C13 VDDQ Power IO VDD 3 3 V 206 D13 VSSQ Power IO GND 0 V 207 A14 A20 O Address 208 B13 A21 O Address 209 A13 A22 O Address 210 B12 A23 O Address 211 C12 VDDQ Power IO VDD 3 3 V 212 D12 VSSQ Power IO GND 0 V 213 A12 A24 O Address 214 B11 A25 O Address 215 A11 MD3 CE2A I O Mode PCMCIA CE MD3 CE2A 216 A10 MD4 CE2B I O Mode PCMCIA CE MD4 CE2B 217 C11 VDDQ Power IO VDD 3 3...

Page 71: ...SEBRK BRKACK I O Pin break acknowledge H UDI 232 A6 TDO O Data out H UDI 233 C7 VDD Power Internal VDD 234 D7 VSS Power Internal GND 0 V 235 B6 TMS I Mode H UDI 236 A5 TCK I Clock H UDI 237 B5 TDI I Data in H UDI 238 C4 TRST I Reset H UDI 239 C3 CKIO2ENB I CKIO2 RD2 RD WR2 enable 240 C6 NC 241 A4 VDD PLL2 Power PLL2 VDD 3 3V 242 D6 VSS PLL2 Power PLL2 GND 0V 243 B4 VDD PLL1 Power PLL1 VDD 3 3V 244...

Page 72: ...lied to VDD PLL1 2 and VSS PLL1 2 regardless of whether or not the on chip PLL circuits are used 3 Power must be supplied to VDD CPG and VSS CPG regardless of whether or not the on chip crystal resonator is used 4 Power must be supplied to VDD RTC and VSS RTC regardless of whether or not the on chip RTC is used 5 VSSQ VSS VSS RTC VSS PLL1 2 and VSS CPG are connected inside the package 6 In the SH7...

Page 73: ... 13 VDD Power Internal VDD 14 VSS Power Internal GND 0 V 15 D46 I O Data port Port Port Port Port Port 16 D33 I O Data port Port Port Port Port Port 17 D45 I O Data port Port Port Port Port Port 18 D34 I O Data port Port Port Port Port Port 19 D44 I O Data port Port Port Port Port Port 20 D35 I O Data port Port Port Port Port Port 21 VDDQ Power IO VDD 3 3 V 22 VSSQ Power IO GND 0 V 23 D43 I O Data...

Page 74: ...r Internal VDD 1 8 V 40 VSS Power Internal GND 0 V 41 D12 I O Data A12 42 D3 I O Data A3 43 VDDQ Power IO VDD 3 3 V 44 VSSQ Power IO GND 0 V 45 D11 I O Data A11 46 D4 I O Data A4 47 D10 I O Data A10 48 D5 I O Data A5 49 D9 I O Data A9 50 D6 I O Data A6 51 BACK BSREQ O Bus acknowledge bus request 52 BREQ BSACK I Bus request bus acknowledge 53 D8 I O Data A8 54 D7 I O Data A7 55 CKE O Clock output e...

Page 75: ...O Address 64 A15 O Address 65 VDD Power Internal VDD 66 VSS Power Internal GND 0 V 67 A14 O Address 68 A13 O Address 69 VDDQ Power IO VDD 3 3 V 70 VSSQ Power IO GND 0 V 71 A12 O Address 72 A11 O Address 73 A10 O Address 74 A9 O Address 75 A8 O Address 76 A7 O Address 77 CKIO O Clock output CKIO 78 VDDQ Power IO VDD 3 3 V 79 VSSQ Power IO GND 0 V 80 A6 O Address 81 A5 O Address 82 A4 O Address 83 A...

Page 76: ...WR RD WR RD WR 96 WE2 CAS2 DQM2 ICIORD O D23 D16 select signal WE2 CAS2 DQM2 ICIORD 97 WE3 CAS3 DQM3 ICIOWR O D31 D24 select signal WE3 CAS3 DQM3 ICIOWR 98 WE6 CAS6 DQM6 O D55 D48 select signal WE6 CAS6 DQM6 99 VDDQ Power IO VDD 3 3 V 100 VSSQ Power IO GND 0 V 101 WE7 CAS7 DQM7 REG O D63 D56 select signal WE7 CAS7 DQM7 REG 102 D23 I O Data A23 103 D24 I O Data A24 104 D22 I O Data A22 105 RXD I SC...

Page 77: ...6 I O Data A16 124 D31 I O Data 125 VDDQ Power IO VDD 3 3 V 126 VSSQ Power IO GND 0 V 127 D55 I O Data 128 D56 I O Data 129 D54 I O Data 130 D57 I O Data 131 D53 I O Data 132 D58 I O Data 133 D52 I O Data 134 D59 I O Data 135 VDDQ Power IO VDD 3 3 V 136 VSSQ Power IO GND 0 V 137 D51 I O Data port Port Port Port Port Port 138 D60 I O Data 139 D50 I O Data port Port Port Port Port Port 140 D61 I O D...

Page 78: ...51 MD2 RXD2 I Mode SCIF data input MD2 RXD2 RXD2 RXD2 RXD2 RXD2 152 IRL0 I Interrupt 0 153 IRL1 I Interrupt 1 154 IRL2 I Interrupt 2 155 IRL3 I Interrupt 3 156 NMI I Nonmaskable interrupt 157 XTAL2 O RTC crystal resonator pin 158 EXTAL2 I RTC crystal resonator pin 159 VSS RTC Power RTC GND 0 V 160 VDD RTC Power RTC VDD 3 3 V 161 CA I 162 VSS Power Internal GND 0 V 163 VDDQ Power IO VDD 3 3 V 164 C...

Page 79: ...175 A22 O Address 176 A23 O Address 177 VDDQ Power IO VDD 3 3 V 178 VSSQ Power IO GND 0 V 179 A24 O Address 180 A25 O Address 181 MD3 CE2A I O Mode PCMCIA CE MD3 CE2A 182 MD4 CE2B I O Mode PCMCIA CE MD4 CE2B 183 MD5 RAS2 I O Mode RAS DRAM MD5 RAS2 184 DACK0 O DMAC0 bus acknowledge 185 DACK1 O DMAC1 bus acknowledge 186 A0 O Address 187 VDDQ Power IO VDD 3 3 V 188 VSSQ Power IO GND 0 V 189 A1 O Addr...

Page 80: ...rdware standby mode supply power to all power pins In hardware standby mode supply power to RTC as a minimum 2 Power must be supplied to VDD PLL1 2 and VSS PLL1 2 regardless of whether or not the on chip PLL circuits are used 3 Power must be supplied to VDD CPG and VSS CPG regardless of whether or not the on chip crystal resonator is used 4 Power must be supplied to VDD RTC and VSS RTC regardless ...

Page 81: ... Port Port Port 13 F5 D32 I O Data port Port Port Port Port Port 14 F1 VDD Power Internal VDD 1 5 V 15 G4 VSS Power Internal GND 0 V 16 G3 D46 I O Data port Port Port Port Port Port 17 F6 D33 I O Data port Port Port Port Port Port 18 G2 VDDQ Power IO VDD 3 3 V 19 G5 VSSQ Power IO GND 0 V 20 G1 D45 I O Data port Port Port Port Port Port 21 G6 D34 I O Data port Port Port Port Port Port 22 H3 D44 I O...

Page 82: ...wer IO GND 0 V 38 K4 D15 I O Data A15 39 K2 D0 I O Data A0 40 L6 D14 I O Data A14 41 L1 D1 I O Data A1 42 L5 VDDQ Power IO VDD 3 3 V 43 L3 VSSQ Power IO GND 0 V 44 M5 D13 I O Data A13 45 M1 D2 I O Data A2 46 L4 VDD Power Internal VDD 1 5 V 47 L2 VSS Power Internal GND 0 V 48 N5 D12 I O Data A12 49 M3 D3 I O Data A3 50 M4 VDDQ Power IO VDD 3 3 V 51 N1 VSSQ Power IO GND 0 V 52 N4 D11 I O Data A11 53...

Page 83: ...QM4 O D39 D32 select signal WE4 CAS4 DQM4 69 U5 WE1 CAS1 DQM1 O D15 D8 select signal WE1 CAS1 DQM1 WE1 70 P6 WE0 CAS0 DQM0 O D7 D0 select signal WE0 CAS0 DQM0 71 R6 A17 O Address 72 P4 VDDQ Power IO VDD 3 3 V 73 T6 VSSQ Power IO GND 0 V 74 N6 A16 O Address 75 U6 A15 O Address 76 P7 VDD Power Internal VDD 1 5 V 77 R7 VSS Power Internal GND 0 V 78 M6 A14 O Address 79 T7 A13 O Address 80 N7 VDDQ Powe...

Page 84: ...1 DRAK1 O DMAC1 request acknowledge 102 N11 DRAK0 O DMAC0 request acknowledge 103 R11 VDDQ Power IO VDD 3 3 V 104 N12 VSSQ Power IO GND 0 V 105 U12 CS3 O Chip select 3 CS3 CS3 CS3 CS3 106 P11 CS2 O Chip select 2 CS2 CS2 CS2 CS2 107 T11 VDD Power Internal VDD 1 5 V 108 N13 VSS Power Internal GND 0 V 109 R12 RAS O RAS RAS RAS 110 P12 RD CASS FRAME O Read CAS FRAME OE CAS OE FRAME 111 U13 VDDQ Power ...

Page 85: ... R16 RXD I SCI1 data input 124 T17 DREQ0 I Request from DMAC0 125 P17 DREQ1 I Request from DMAC1 126 P15 D25 I O Data A25 127 N16 VDDQ Power IO VDD 3 3 V 128 T16 VSSQ Power IO GND 0 V 129 N15 D21 I O Data A21 130 N14 D26 I O Data 131 N17 D20 I O Data A20 132 M14 D27 I O Data 133 M15 VDDQ Power IO VDD 3 3 V 134 P14 VSSQ Power IO GND 0 V 135 M16 D19 I O Data A19 136 M13 D28 I O Data 137 M17 VDD Powe...

Page 86: ...I O Data 158 H17 D59 I O Data 159 H13 VDDQ Power IO VDD 3 3 V 160 H15 VSSQ Power IO GND 0 V 161 H14 D51 I O Data port Port Port Port Port Port 162 H16 D60 I O Data 163 G12 D50 I O Data port Port Port Port Port Port 164 G17 D61 I O Data ACCSIZE0 165 G13 VDDQ Power IO VDD 3 3 V 166 G15 VSSQ Power IO GND 0 V 167 F13 D49 I O Data port Port Port Port Port Port 168 F17 D62 I O Data ACCSIZE1 169 G14 VDD ...

Page 87: ...183 C16 NMI I Nonmaskable interrupt 184 A15 XTAL2 O RTC crystal resonator pin 185 A16 EXTAL2 I RTC crystal resonator pin 186 A14 VSS RTC Power RTC GND 0 V 187 C14 VDD RTC Power RTC VDD 3 3 V 188 B13 CA I Hardware standby request 189 C13 VDDQ Power IO VDD 3 3 V 190 D13 CTS2 I O SCIF data control CTS 191 A13 TCLK I O RTC TMU clock 192 D12 MD8 RTS2 I O Mode SCIF data control RTS MD8 RTS2 RTS2 RTS2 RT...

Page 88: ... V 208 E10 VSSQ Power IO GND 0 V 209 B10 A24 O Address 210 F10 A25 O Address 211 C9 MD3 CE2A I O Mode PCMCIA CE MD3 CE2A 212 E9 MD4 CE2B I O Mode PCMCIA CE MD4 CE2B 213 A9 VDDQ Power IO VDD 3 3 V 214 F9 VSSQ Power IO GND 0 V 215 D9 MD5 RAS2 I O Mode RAS DRAM MD5 RAS2 216 B9 DACK0 O DMAC0 bus acknowledge 217 F8 DACK1 O DMAC1 bus acknowledge 218 A8 A0 O Address 219 E8 VDDQ Power IO VDD 3 3 V 220 C8 ...

Page 89: ...UDI 233 D6 TDI I Data in H UDI 234 A5 TRST I Reset H UDI 235 D5 CKIO2ENB I CKIO2 RD2 RD WR2 enable 236 B6 VDD PLL2 Power PLL2 VDD 3 3V 237 C3 VSS PLL2 Power PLL2 GND 0V 238 C5 VDD PLL1 Power PLL1 VDD 3 3V 239 C4 VSS PLL1 Power PLL1 GND 0V 240 A4 VDD CPG Power CPG VDD 3 3V 241 A1 VSS CPG Power CPG GND 0V 242 A2 XTAL O Crystal resonator 243 A3 EXTAL I External clock crystal resonator 244 B3 NC 1 245...

Page 90: ...ins In hardware standby mode supply power to RTC as a minimum 2 Power must be supplied to VDD PLL1 2 and VSS PLL1 2 regardless of whether or not the on chip PLL circuits are used 3 Power must be supplied to VDD CPG and VSS CPG regardless of whether or not the on chip crystal resonator is used 4 Power must be supplied to VDD RTC and VSS RTC regardless of whether or not the on chip RTC is used 5 At ...

Page 91: ... data formats handled by the SH7750 Series are shown in figure 2 1 Byte 8 bits Word 16 bits Longword 32 bits Single precision floating point 32 bits Double precision floating point 64 bits 0 7 0 15 0 31 0 31 30 22 fraction exp s 0 63 62 51 exp s fraction Figure 2 1 Data Formats ...

Page 92: ...NK0 to R7_BANK0 are accessed by the LDC STC instructions When the RB bit is 0 that is when bank 0 is selected the 16 registers comprising bank 0 general registers R0_BANK0 to R7_BANK0 and non banked general registers R8 to R15 can be accessed as general registers R0 to R15 In this case the eight registers comprising bank 1 general registers R0_BANK1 to R7_BANK1 are accessed by the LDC STC instruct...

Page 93: ...ix XMTRX Register values after a reset are shown in table 2 1 Table 2 1 Initial Register Values Type Registers Initial Value General registers R0_BANK0 R7_BANK0 R0_BANK1 R7_BANK1 R8 R15 Undefined SR MD bit 1 RB bit 1 BL bit 1 FD bit 0 I3 I0 1111 H F reserved bits 0 others undefined GBR SSR SPC SGR DBR Undefined Control registers VBR H 00000000 MACH MACL PR FPUL Undefined PC H A0000000 System regis...

Page 94: ..._BANK1 3 R7_BANK1 3 R8 R9 R10 R11 R12 R13 R14 R15 R0_BANK0 1 4 R1_BANK0 4 R2_BANK0 4 R3_BANK0 4 R4_BANK0 4 R5_BANK0 4 R6_BANK0 4 R7_BANK0 4 c Register configuration in privileged mode RB 0 GBR MACH MACL VBR PR SR SSR PC SPC SGR DBR SGR DBR Notes 1 The R0 register is used as the index register in indexed register indirect addressing mode and indexed GBR indirect addressing mode 2 Banked registers 3...

Page 95: ...ed as general registers R0 R15 in one processor mode The SH7750 Series has two processor modes user mode and privileged mode in which R0 R7 are assigned as shown below R0_BANK0 R7_BANK0 In user mode SR MD 0 R0 R7 are always assigned to R0_BANK0 R7_BANK0 In privileged mode SR MD 1 R0 R7 are assigned to R0_BANK0 R7_BANK0 only when SR RB 0 R0_BANK1 R7_BANK1 In user mode R0_BANK1 R7_BANK1 cannot be ac...

Page 96: ...NK1 R7_BANK1 R0 R1 R2 R3 R4 R5 R6 R7 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R8 R9 R10 R11 R12 R13 R14 R15 R8 R9 R10 R11 R12 R13 R14 R15 SR MD 1 SR RB 1 Figure 2 3 General Registers Programming Note As the user s R0 R7 are assigned to R0_BANK0 R7_BANK0 and after an exception or interrupt R0 R7 are assigned to R0_BANK1 R7_BANK1 it is not necessary for the interrupt handler to save and...

Page 97: ... FPR15_BANK1 Single precision floating point registers FRi 16 registers When FPSCR FR 0 FR0 FR15 are assigned to FPR0_BANK0 FPR15_BANK0 When FPSCR FR 1 FR0 FR15 are assigned to FPR0_BANK1 FPR15_BANK1 Double precision floating point registers or single precision floating point register pairs DRi 8 registers A DR register comprises two FR registers DR0 FR0 FR1 DR2 FR2 FR3 DR4 FR4 FR5 DR6 FR6 FR7 DR8...

Page 98: ... XF14 XF15 FR0 FR1 FR2 FR3 FR4 FR5 FR6 FR7 FR8 FR9 FR10 FR11 FR12 FR13 FR14 FR15 DR0 DR2 DR4 DR6 DR8 DR10 DR12 DR14 FV0 FV4 FV8 FV12 XD0 XMTRX XD2 XD4 XD6 XD8 XD10 XD12 XD14 FPR0_BANK1 FPR1_BANK1 FPR2_BANK1 FPR3_BANK1 FPR4_BANK1 FPR5_BANK1 FPR6_BANK1 FPR7_BANK1 FPR8_BANK1 FPR9_BANK1 FPR10_BANK1 FPR11_BANK1 FPR12_BANK1 FPR13_BANK1 FPR14_BANK1 FPR15_BANK1 XF0 XF1 XF2 XF3 XF4 XF5 XF6 XF7 XF8 XF9 XF10...

Page 99: ...an be accessed using LDC STC R0_BANK R7_BANK instructions RB 1 R0_BANK1 R7_BANK1 are accessed as general registers R0 R7 R0_BANK0 R7_BANK0 can be accessed using LDC STC R0_BANK R7_BANK instructions BL Exception interrupt block bit set to 1 by a reset exception or interrupt BL 1 Interrupt requests are masked If a general exception other than a user break occurs while BL 1 the processor switches to ...

Page 100: ...2 bits privilege protection initial value undefined The contents of R15 are saved to SGR in the event of an exception or interrupt Debug base register DBR 32 bits privilege protection initial value undefined When the user break debug function is enabled BRCR UBDE 1 DBR is referenced as the user break handler branch destination address instead of VBR 2 2 5 System Registers Multiply and accumulate r...

Page 101: ...R 0 Floating point instructions are executed as single precision operations PR 1 Floating point instructions are executed as double precision operations the result of instructions for which double precision is not supported is undefined Do not set SZ and PR to 1 simultaneously this setting is reserved SZ PR 11 Reserved FPU operation instruction is undefined DN Denormalization mode DN 0 A denormali...

Page 102: ...sion floating point number 2 3 Memory Mapped Registers Appendix A Address List shows the control registers mapped to memory The control registers are double mapped to the following two memory areas All registers have two addresses H 1C00 0000 H 1FFF FFFF H FC00 0000 H FFFF FFFF These two areas are used as follows H 1C00 0000 H 1FFF FFFF This area must be accessed using the address translation func...

Page 103: ... rule is not observed A byte operand can be accessed from any address Big endian or little endian byte order can be selected for the data format The endian should be set with the MD5 external pin in a power on reset Big endian is selected when the MD5 pin is low and little endian when high The endian cannot be changed dynamically Bit positions are numbered left to right from most significant to le...

Page 104: ...s for further details Exception Handling State This is a transient state during which the CPU s processor state flow is altered by a reset general exception or interrupt exception handling source In the case of a reset the CPU branches to address H A000 0000 and starts executing the user coded exception handling program In the case of a general exception or interrupt the program counter PC content...

Page 105: ...y state when 0 and 1 From any state when 0 and 0 Reset state Power down state Bus request Bus request Standby mode Sleep mode Figure 2 6 Processor State Transitions 2 7 Processor Modes There are two processor modes user mode and privileged mode The processor mode is determined by the processor mode bit MD in the status register SR User mode is selected when the MD bit is cleared to 0 and privilege...

Page 106: ...Rev 6 0 07 02 page 56 of 986 ...

Page 107: ...ring execution onto physical memory on an ad hoc basis 1 Having this mapping onto physical memory executed consciously by the process itself imposes a heavy burden on the process The virtual memory system was devised as a means of handling all physical memory mapping to reduce this burden 2 With a virtual memory system the size of the available virtual memory is much larger than the actual physica...

Page 108: ...requently used address translation information is placed here The TLB can be described as a cache for address translation information However unlike a cache if address translation fails that is if an exception occurs switching of the address translation information is normally performed by software Thus memory management can be performed in a flexible manner by software There are two methods by wh...

Page 109: ...ess 1 Process 1 Physical memory Process 1 Process 2 Process 3 Virtual memory Process 1 Process 1 Process 2 Process 3 MMU MMU 4 3 1 Physical memory Physical memory Physical memory Physical memory Virtual memory Figure 3 1 Role of the MMU ...

Page 110: ...0034 H 1F00 0034 32 Translation table base register TTB R W Undefined H FF00 0008 H 1F00 0008 32 TLB exception address register TEA R W Undefined H FF00 000C H 1F00 000C 32 MMU control register MMUCR R W H 0000 0000 H FF00 0010 H 1F00 0010 32 Notes 1 The initial value is the value after a power on reset or manual reset 2 This is the address when using the virtual physical address space P4 area Whe...

Page 111: ...6 5 4 3 2 1 0 V SZ PR SZ C D SH WT 2 PTEL 31 4 3 2 0 TC SA 3 PTEA 31 0 TTB 4 TTB 31 Virtual address at which MMU exception or address error occurred 5 TEA 31 26 24 23 18 17 16 15 10 9 8 7 6 5 4 3 2 1 0 LRUI URC SQMD SV TI AT 6 MMUCR indicates a reserved bit the write value must be 0 and a read will return 0 URB 25 Figure 3 2 MMU Related Registers ...

Page 112: ...tance register PTEA Longword access to PTEA can be performed from H FF00 0034 in the P4 area and H 1F00 0034 in area 7 PTEL is used to store assistance bits for PCMCIA access to the UTLB by means of the LDTLB instruction When performing access from the CPU in the SH7750S and SH7750R with MMUCR AT 0 access is always performed using the values of the SA and TC bits in this register In the SH7750 it ...

Page 113: ...decide the ITLB entry to be replaced in the event of an ITLB miss The entry to be purged from the ITLB can be confirmed using the LRUI bits LRUI is updated by means of the algorithm shown below A dash in this table means that updating is not performed LRUI 5 4 3 2 1 0 When ITLB entry 0 is used 0 0 0 When ITLB entry 1 is used 1 0 0 When ITLB entry 2 is used 1 1 0 When ITLB entry 3 is used 1 1 1 Oth...

Page 114: ...ed ensure that 1 is also written to the TI bit TI TLB invalidation bit Writing 1 to this bit invalidates clears to 0 all valid UTLB ITLB bits This bit always returns 0 when read AT Address translation enable bit Specifies MMU enabling or disabling 0 MMU disabled 1 MMU enabled MMU exceptions are not generated when the AT bit is 0 In the case of software that does not use the MMU therefore the AT bi...

Page 115: ...An CHCRn DSAn CHCRn STC and CHCRn DTC in the DMAC For details see section 14 Direct Memory Access Controller DMAC P0 P1 P3 U0 Areas The P0 P1 P3 and U0 areas can be accessed using the cache Whether or not the cache is used is determined by the cache control register CCR When the cache is used with the exception of the P1 area switching between the copy back method and the write through method for ...

Page 116: ...Unified TLB data arrays 1 and 2 Reserved area Control register area Figure 3 4 P4 Area The area from H E000 0000 to H E3FF FFFF comprises addresses for accessing the store queues SQs When the MMU is disabled MMUCR AT 0 the SQ access right is specified by the MMUCR SQMD bit For details see section 4 7 Store Queues The area from H F000 0000 to H F0FF FFFF is used for direct access to the instruction...

Page 117: ...Array The area from H F700 0000 to H F7FF FFFF is used for direct access to unified TLB data arrays 1 and 2 For details see sections 3 7 5 UTLB Data Array 1 and 3 7 6 UTLB Data Array 2 The area from H FF00 0000 to H FFFF FFFF is the on chip peripheral module control register area For details see appendix A Address List 3 3 2 External Memory Space The SH7750 Series supports a 29 bit external memory...

Page 118: ...rol register area in the physical memory space Virtual memory space is illustrated in figure 3 6 Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 External memory space 256 256 U0 area Cacheable Address translation possible Address error Address error Store queue area P0 area Cacheable Address translation possible User mode Privileged mode P1 area Cacheable Address translation not possible P...

Page 119: ... this case the C bit for the corresponding page must be cleared to 0 P1 P2 P4 Areas Address translation using the TLB cannot be performed for the P1 P2 or P4 area except for the store queue area Accesses to these areas are the same as for physical memory space The store queue area can be mapped onto any external memory space by the MMU However operation in the case of an exception differs from tha...

Page 120: ...ected with the MMUCR SV bit In the single virtual memory system a number of processes run simultaneously using virtual address space on an exclusive basis and the physical address corresponding to a particular virtual address is uniquely determined In the multiple virtual memory system a number of processes run while sharing the virtual address space and a particular virtual address may be transla...

Page 121: ...ess translation table contains virtual page numbers and address space identifiers and corresponding physical page numbers and page management information Figure 3 7 shows the overall configuration of the UTLB The UTLB consists of 64 fully associative type entries Figure 3 8 shows the relationship between the address format and page size PPN 28 10 PPN 28 10 PPN 28 10 SZ 1 0 SZ 1 0 SZ 1 0 SH SH SH C...

Page 122: ... Page Size and Address Format VPN Virtual page number For 1 kbyte page upper 22 bits of virtual address For 4 kbyte page upper 20 bits of virtual address For 64 kbyte page upper 16 bits of virtual address For 1 Mbyte page upper 12 bits of virtual address ASID Address space identifier Indicates the process that can access a virtual page In single virtual memory mode and user mode or in multiple vir...

Page 123: ...yte page PPN bits 28 20 are valid The synonym problem must be taken into account when setting the PPN see section 3 5 5 Avoiding Synonym Problems PR Protection key data 2 bit data expressing the page access right as a code 00 Can be read only in privileged mode 01 Can be read and written in privileged mode 10 Can be read only in privileged or user mode 11 Can be read and written in privileged mode...

Page 124: ...ts Valid only when the page is mapped onto PCMCIA connected to area 5 or 6 000 Undefined 001 Variable size I O space base size according to IOIS16 signal 010 8 bit I O space 011 16 bit I O space 100 8 bit common memory space 101 16 bit common memory space 110 8 bit attribute memory space 111 16 bit attribute memory space TC Timing control bit Used to select wait control register bits in the bus co...

Page 125: ...ation is almost the same as that in the UTLB but with the following differences 1 D and WT bits are not supported 2 There is only one PR bit corresponding to the upper of the PR bits in the UTLB PPN 28 10 PPN 28 10 PPN 28 10 PPN 28 10 SZ 1 0 SZ 1 0 SZ 1 0 SZ 1 0 SH SH SH SH C C C C PR PR PR PR ASID 7 0 ASID 7 0 ASID 7 0 ASID 7 0 VPN 31 10 VPN 31 10 VPN 31 10 VPN 31 10 V V V V Entry 0 Entry 1 Entry...

Page 126: ... exception Data TLB miss exception Initial page write exception Data TLB protection violation exception Cache access in copy back mode Data access to virtual address VA On chip I O access R W R W VA is in P4 area VA is in P2 area VA is in P1 area VA is in P0 U0 or P3 area Yes No 1 1 0 Yes Yes No No Yes Yes Yes No No 1 Privileged 1 0 0 PR 0 User D R W W W W R R R R W R W Non cacheable WT C 1 and CC...

Page 127: ...miss exception Instruction access to virtual address VA VA is in P4 area VA is in P2 area VA is in P1 area VA is in P0 U0 or P3 area Yes No 1 0 Yes Yes No No Yes Yes No Non cacheable C 1 and CCR ICE 1 No PR Instruction TLB protection violation exception Match Record in ITLB Access prohibited 0 1 No Yes Yes No Hardware ITLB miss handling 0 User 1 Privileged Search UTLB Cache access Figure 3 11 Flow...

Page 128: ... Setting of MMU related registers Some registers are also partially updated by hardware automatically 2 Recording deletion and reading of TLB entries There are two methods of recording UTLB entries by using the LDTLB instruction or by writing directly to the memory mapped UTLB ITLB entries can only be recorded by writing directly to the memory mapped ITLB For deleting or reading UTLB ITLB entries ...

Page 129: ...UI URB URC SV SQMD TI AT MMUCR VPN 10 PPN 31 4 3 2 0 SA TC PTEA Entry specification Figure 3 12 Operation of LDTLB Instruction 3 5 4 Hardware ITLB Miss Handling In an instruction access the SH7750 Series searches the ITLB If it cannot find the necessary address translation information i e in the event of an ITLB miss the UTLB is searched by hardware and if the necessary address translation informa...

Page 130: ...ranslation information in UTLB entries 1 When address translation information whereby a number of 1 kbyte page UTLB entries are translated into the same physical address is recorded in the UTLB ensure that the VPN 13 10 values are the same 2 When address translation information whereby a number of 4 kbyte page UTLB entries are translated into the same physical address is recorded in the UTLB ensur...

Page 131: ...instruction access has been made If multiple hits occur when the UTLB is searched by hardware in hardware ITLB miss handling a data TLB multiple hit exception will result When an instruction TLB multiple hit exception occurs a reset is executed and cache coherency is not guaranteed Hardware Processing In the event of an instruction TLB multiple hit exception hardware carries out the following proc...

Page 132: ...mode 7 Sets the BL bit in SR to 1 and masks subsequent exception requests 8 Sets the RB bit in SR to 1 9 Branches to the address obtained by adding offset H 0000 0400 to the contents of VBR and starts the instruction TLB miss exception handling routine Software Processing Instruction TLB Miss Exception Handling Routine Software is responsible for searching the external memory page table and assign...

Page 133: ...e PC value indicating the address of the instruction at which the exception occurred in SPC If the exception occurred at a delay slot sets the PC value indicating the address of the delayed branch instruction in SPC 5 Sets the SR contents at the time of the exception in SSR The R15 contents at this time are saved in SGR 6 Sets the MD bit in SR to 1 and switches to privileged mode 7 Sets the BL bit...

Page 134: ...TLB miss exception occurs when address translation information for the virtual address to which a data access is made is not found in the UTLB entries The data TLB miss exception processing carried out by hardware and software is shown below Hardware Processing In the event of a data TLB miss exception hardware carries out the following processing 1 Sets the VPN of the virtual address at which the...

Page 135: ...n exception occurs when even though a UTLB entry contains address translation information matching the virtual address to which a data access is made the actual access type is not permitted by the access right specified by the PR bit The data TLB protection violation exception processing carried out by hardware and software is shown below Hardware Processing In the event of a data TLB protection v...

Page 136: ...are Processing In the event of an initial page write exception hardware carries out the following processing 1 Sets the VPN of the virtual address at which the exception occurred in PTEH 2 Sets the virtual address at which the exception occurred in TEA 3 Sets exception code H 080 in EXPEVT 4 Sets the PC value indicating the address of the instruction at which the exception occurred in SPC If the e...

Page 137: ...n handling routine and return control to the normal flow The RTE instruction should be issued at least one instruction after the LDTLB instruction 3 7 Memory Mapped TLB Configuration To enable the ITLB and UTLB to be managed by software their contents can be read and written by a P2 area program with a MOV instruction in privileged mode Operation is not guaranteed if access is made from a program ...

Page 138: ...As longword access is used 0 should be specified for address field bits 1 0 In the data field VPN is indicated by bits 31 10 V by bit 8 and ASID by bits 7 0 The following two kinds of operation can be used on the ITLB address array 1 ITLB address array read VPN V and ASID are read into the data field from the ITLB entry corresponding to the entry set in the address field 2 ITLB address array write...

Page 139: ...ndicated by bits 28 10 V by bit 8 SZ by bits 7 and 4 PR by bit 6 C by bit 3 and SH by bit 1 The following two kinds of operation can be used on ITLB data array 1 1 ITLB data array 1 read PPN V SZ PR C and SH are read into the data field from the ITLB entry corresponding to the entry set in the address field 2 ITLB data array 1 write PPN V SZ PR C and SH specified in the data field are written to t...

Page 140: ...SA and TC are read into the data field from the ITLB entry corresponding to the entry set in the address field 2 ITLB data array 2 write SA and TC specified in the data field are written to the ITLB entry corresponding to the entry set in the address field Address field 31 23 0 1 1 1 1 0 0 1 1 1 E Data field 31 4 0 TC E 24 Timing control bit Entry 8 9 7 3 2 SA Space attribute bits Reserved bits 0 ...

Page 141: ...rite is performed with the A bit in the address field set to 1 comparison of all the UTLB entries is carried out using the VPN specified in the data field and PTEH ASID The usual address comparison rules are followed but if a UTLB miss occurs the result is no operation and an exception is not generated If the comparison identifies a UTLB entry corresponding to the VPN specified in the data field D...

Page 142: ...Z by bits 7 and 4 PR by bits 6 5 C by bit 3 D by bit 2 SH by bit 1 and WT by bit 0 The following two kinds of operation can be used on UTLB data array 1 1 UTLB data array 1 read PPN V SZ PR C D SH and WT are read into the data field from the UTLB entry corresponding to the entry set in the address field 2 UTLB data array 1 write PPN V SZ PR C D SH and WT specified in the data field are written to ...

Page 143: ...ng UTLB data array 2 and the entry is selected by bits 13 8 In the data field TC is indicated by bit 3 and SA by bits 2 0 The following two kinds of operation can be used on UTLB data array 2 1 UTLB data array 2 read SA and TC are read into the data field from the UTLB entry corresponding to the entry set in the address field 2 UTLB data array 2 write SA and TC specified in the data field are writ...

Page 144: ...Rev 6 0 07 02 page 94 of 986 ...

Page 145: ...when the EMODE bit in the CCR register is 1 are given in table 4 2 The EMODE bit is initialized to 0 after a power on reset or manual reset For high speed writing to external memories the SH7750 series supports 32 bytes 2 of store queues SQ Table 4 3 lists the features of these SQs Table 4 1 Cache Features SH7750 SH7750S Item Instruction Cache Operand Cache Capacity 8 kbyte cache 16 kbyte cache or...

Page 146: ...4 Cache Control Registers Name Abbreviation R W Initial Value 1 P4 Address 2 Area 7 Address 2 Access Size Cache control register CCR R W H 0000 0000 H FF00 001C H 1F00 001C 32 Queue address control register 0 QACR0 R W Undefined H FF00 0038 H 1F00 0038 32 Queue address control register 1 QACR1 R W Undefined H FF00 003C H 1F00 003C 32 Notes 1 The initial value is the value after a power on or manua...

Page 147: ...or SH7750 and SH7750S IIX IC index enable ICI IC invalidation ICE IC enable OIX OC index enable ORA OC RAM enable OCI OC invalidation CB Copy back enable WT Write through enable OCE OC enable Longword access to CCR can be performed from H FF00 001C in the P4 area and H 1F00 001C in area 7 The CCR bits are used for the cache settings described below Consequently CCR modifications must only be made ...

Page 148: ...e IC is to be used When address translation is performed the IC cannot be used unless the C bit in the page management information is also 1 0 IC not used 1 IC used OIX OC index enable bit 2 0 Effective address bits 13 5 used for OC entry selection 1 Effective address bits 25 and 12 5 used for OC entry selection ORA OC RAM enable bit 3 When the OC is enabled OCE 1 the ORA bit specifies whether the...

Page 149: ...Queue Address Control Register 0 QACR0 Longword access to QACR0 can be performed from H FF00 0038 in the P4 area and H 1F00 0038 in area 7 QACR0 specifies the area onto which store queue 0 SQ0 is mapped when the MMU is off 3 Queue Address Control Register 1 QACR1 Longword access to QACR1 can be performed from H FF00 003C in the P4 area and H 1F00 003C in area 7 QACR1 specifies the area onto which ...

Page 150: ...32 bits LW6 32 bits LW7 32 bits MMU RAM area determination ORA OIX 13 12 11 5 511 19 bits 1 bit 1 bit Tag U V Address array Data array Entry selection Longword LW selection Effective address 3 9 22 19 0 Write data Read data Hit signal Compare 13 12 11 10 9 0 Figure 4 2 Configuration of Operand Cache SH7750 SH7750S ...

Page 151: ... 32 bits 1 bit MMU RAM area judgment OIX ORA 13 12 5 511 19 bits 1 bit 1 bit Tag address U V Address array way 0 way 1 Data array way 0 way 1 LRU Entry selection Longword LW selection Effective address 3 9 22 19 0 Write data Read data Hit signal Compare way 0 Compare way 1 13 12 10 0 Figure 4 3 Configuration of Operand Cache SH7750R ...

Page 152: ...gh mode unless it is modified by accessing the memory mapped cache see section 4 5 Memory Mapped Cache Configuration The U bit is initialized to 0 by a power on reset but retains its value in a manual reset Data field The data field holds 32 bytes 256 bits of data per cache line The data array is not initialized by a power on or manual reset LRU SH7750R only In a 2 way set associative cache up to ...

Page 153: ...aparound method in order from the longword data corresponding to the effective address and when the corresponding data arrives in the cache the read data is returned to the CPU While the remaining one cache line of data is being read the CPU can execute the next processing When reading of one line of data is completed the tag corresponding to the effective address is recorded in the cache and 1 is...

Page 154: ...size quadword longword word byte is performed for the data indexed by bits 4 0 of the effective address of the data field of the cache line indexed by effective address bits 13 5 A write is also performed to the corresponding external memory using the specified access size 3c Cache miss no copy back write back A data write in accordance with the access size quadword longword word byte is performed...

Page 155: ...ress is recorded in the cache and 1 is written to the V bit and U bit The data in the write back buffer is then written back to external memory 4 3 4 Write Back Buffer In order to give priority to data reads to the cache and improve performance the SH7750 Series has a write back buffer which holds the relevant cache entry when it becomes necessary to purge a dirty cache entry into external memory ...

Page 156: ...nd the 4 kbytes comprising OC entries 384 to 511 as RAM area 2 When OC index mode is off CCR OIX 0 H 7C00 0000 to H 7C00 0FFF 4 kB Corresponds to RAM area 1 H 7C00 1000 to H 7C00 1FFF 4 kB Corresponds to RAM area 1 H 7C00 2000 to H 7C00 2FFF 4 kB Corresponds to RAM area 2 H 7C00 3000 to H 7C00 3FFF 4 kB Corresponds to RAM area 2 H 7C00 4000 to H 7C00 4FFF 4 kB Corresponds to RAM area 1 RAM areas 1...

Page 157: ... of the RAM area are created in 16 kbyte blocks until H 7FFF FFFF is reached 4 3 7 OC Index Mode Setting CCR OIX to 1 enables OC indexing to be performed using bit 25 of the effective address This is called OC index mode In normal mode with CCR OIX cleared to 0 OC indexing is performed using bits 13 5 of the effective address Using index mode allows the OC to be handled as two areas by means of ef...

Page 158: ... if the prefetch address results in a UTLB miss or a protection violation the result is no operation and an exception is not generated Details of the prefetch instruction are given in the Programming Manual Prefetch instruction PREF Rn 4 4 Instruction Cache IC 4 4 1 Configuration The instruction cache of the SH7750 or SH7750S is of the direct mapping type and consists of 256 cache lines each compo...

Page 159: ...LW5 32 bits LW6 32 bits LW7 32 bits 255 19 bits 1 bit Tag V Address array Longword LW selection Data array 0 Read data Hit signal Compare 31 26 25 5 4 3 2 1 MMU IIX 12 11 5 Entry selection Effective address 8 3 22 19 13 1211 10 9 0 Figure 4 6 Configuration of Instruction Cache SH7750 SH7750S ...

Page 160: ... 13 12 1110 0 Figure 4 7 Configuration of Instruction Cache SH7750R Tag Stores the upper 19 bits of the 29 bit external address of the data line to be cached The tag is not initialized by a power on or manual reset V bit validity bit Indicates that valid data is stored in the cache line When this bit is 1 the cache line data is valid The V bit is initialized to 0 by a power on reset but retains it...

Page 161: ...e V bit is 1 3a If the tag matches and the V bit is 0 3b If the tag does not match and the V bit is 0 3b If the tag does not match and the V bit is 1 3b 3a Cache hit The data indexed by effective address bits 4 2 is read as an instruction from the data field of the cache line indexed by effective address bits 12 5 3b Cache miss Data is read into the cache line from the external memory space corres...

Page 162: ...hether or not association is performed when writing to the IC address array As only longword access is used 0 should be specified for address field bits 1 0 In the data field the tag is indicated by bits 31 10 and the V bit by bit 0 As the IC address array tag is 19 bits in length data field bits 31 29 are not used in the case of a write in which association is not performed Data field bits 31 29 ...

Page 163: ...iting and a 32 bit data field specification The entry to be accessed is specified in the address field and the longword data to be written is specified in the data field In the address field bits 31 24 have the value H F1 indicating the IC data array and the entry is specified by bits 12 5 CCR IIX has no effect on this entry specification Address field bits 4 2 are used for the longword data speci...

Page 164: ...e specified for address field bits 1 0 In the data field the tag is indicated by bits 31 10 the U bit by bit 1 and the V bit by bit 0 As the OC address array tag is 19 bits in length data field bits 31 29 are not used in the case of a write in which association is not performed Data field bits 31 29 are used for the virtual address specification only in the case of a write in which association is ...

Page 165: ...ltiple hit exception occurs during address translation processing switches to the data TLB multiple hit exception handling routine Address field 31 23 5 4 3 2 1 0 1 1 1 1 0 1 0 0 Entry A Data field 31 10 9 1 0 V Tag 24 13 14 2 U V U A Validity bit Dirty bit Association bit Reserved bits 0 write value undefined read value Figure 4 10 Memory Mapped OC Address Array 4 5 4 OC Data Array The OC data ar...

Page 166: ...ed mode is allowed to access their contents The contents of IC can be read and written by using MOV instructions in a P2 area program running in the privileged mode Operation is not guaranteed for access from a program in some other area Any branching to other areas must take place at least 8 instructions after this MOV instruction The contents of IC can be read and written by using MOV instructio...

Page 167: ...ead into the data field from the IC entry corresponding to the way and the entry set in the address field In a read associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0 2 IC address array write non associative The tag and V bit specified in the data field are written to the IC entry corresponding to the way and the entry set in t...

Page 168: ...icating the IC data array the way is specified by bit 13 and the entry by bits 12 5 CCR IIX has no effect on this entry specification Address field bits 4 2 are used for the longword data specification in the entry As only longword access is used 0 should be specified for address field bits 1 0 The data field is used for the longword data specification The following two kinds of operation can be u...

Page 169: ...n 4 6 5 The address array bit 3 association bit A bit specifies whether or not association is performed when writing to the OC address array As only longword access is used 0 should be specified for address field bits 1 0 In the data field the tag is indicated by bits 31 10 the U bit by bit 1 and the V bit by bit 0 As the OC address array tag is 19 bits in length data field bits 31 29 are not used...

Page 170: ...performed and the write is not executed If a data TLB multiple hit exception occurs during address translation processing switches to the data TLB multiple hit exception handling routine Address field 31 23 5 4 3 2 1 0 1 1 1 1 0 1 0 0 Entry A Data field 31 10 9 1 0 V Tag 24 13 14 15 2 U V U A Validity bit Dirty bit Association bit Reserved bits 0 write value undefined read value Way Figure 4 14 Me...

Page 171: ...ddress field 31 23 5 4 2 1 0 1 1 1 1 0 1 0 1 Entry L Data field 31 0 Longword data 24 13 14 15 L Longword specification bits Reserved bits 0 write value undefined read value Way Figure 4 15 Memory Mapped OC Data Array 4 6 5 Summary of the Memory Mapping of the OC The address ranges to which the OC is memory mapped in the double sized cache mode of the SH7750R are summarized below using examples of...

Page 172: ...7 4B 4B 4B 4B 4B 4B 4B 4B Figure 4 16 Store Queue Configuration 4 7 2 SQ Writes A write to the SQs can be performed using a store instruction MOV on P4 area H E000 0000 to H E3FF FFFC A longword or quadword access size can be used The meaning of the address bits is as follows 31 26 111000 Store queue specification 25 6 Don t care Used for external memory transfer access right 5 0 1 0 SQ0 specifica...

Page 173: ...r to address translation is generated in the same way as when the MMU is off External memory address bits 4 0 are fixed at 0 Transfer from the SQs to external memory is performed to this address When MMU is off The SQ area H E000 0000 to H E3FF FFFF is specified as the address to issue a PREF instruction The meaning of address bits 31 0 is as follows 31 26 111000 Store queue specification 25 6 Add...

Page 174: ...ry PREF instruction and a TLB miss exception protection violation exception or initial page write exception is generated However if SQ access is enabled in privileged mode only by MMUCR SQMD an address error will be flagged in user mode even if address translation is successful When MMU is off Operation is in accordance with MMUCR SQMD 0 Privileged user access possible 1 Privileged access possible...

Page 175: ...rred to external memory within an exception handling routine erroneous data may be transferred to external memory Example 1 When an SQ store instruction is executed after a PREF instruction for transfer from that same SQ to external memory PREF instruction PREF instruction for transfer from SQ to external memory Address of this instruction is saved to SPC when exception occurs Instruction 1 instru...

Page 176: ...inserted between the above two instructions 2 There must not be a PREF instruction to transfer data from the store queue to external memory in the delay slot of the branch instruction B There must be no PREF instruction to transfer data from the store queue to external memory executed in the exception handling routine If such an instruction is executed and if there is a store to the store queue in...

Page 177: ...e generic name of exception handling SH7750 Series exception handling is of three kinds for resets general exceptions and interrupts 5 1 2 Register Configuration The registers used in exception handling are shown in table 5 1 Table 5 1 Exception Related Registers Name Abbrevia tion R W Initial Value 1 P4 Address 2 Area 7 Address 2 Access Size TRAPA exception register TRA R W Undefined H FF00 0020 ...

Page 178: ... FF00 0028 and contains a 12 bit exception code The exception code set in INTEVT is that for an interrupt request The exception code is set automatically by hardware when an exception occurs INTEVT can also be modified by software 3 The TRAPA exception register TRA resides at P4 address H FF00 0020 and contains 8 bit immediate data imm for the TRAPA instruction TRA is set automatically by hardware...

Page 179: ...e individual SR bits 1 The PC SR and R15 contents are saved in SPC SSR and SGR 2 The block bit BL in SR is set to 1 3 The mode bit MD in SR is set to 1 4 The register bank bit RB in SR is set to 1 5 In a reset the FPU disable bit FD in SR is cleared to 0 6 The exception code is written to bits 11 0 of the exception event register EXPEVT or interrupt event register INTEVT 7 The CPU branches to the ...

Page 180: ...LB miss exception 2 2 VBR H 400 H 040 Instruction TLB protection violation exception 2 3 VBR H 100 H 0A0 General illegal instruction exception 2 4 VBR H 100 H 180 Slot illegal instruction exception 2 4 VBR H 100 H 1A0 General FPU disable exception 2 4 VBR H 100 H 800 Slot FPU disable exception 2 4 VBR H 100 H 820 Data address error read 2 5 VBR H 100 H 0E0 Data address error write 2 5 VBR H 100 H ...

Page 181: ...2A0 6 H 2C0 7 H 2E0 8 H 300 9 H 320 A H 340 B H 360 C H 380 D H 3A0 External interrupts IRL3 IRL0 E 4 2 VBR H 600 H 3C0 TMU0 TUNI0 H 400 TMU1 TUNI1 H 420 TUNI2 H 440 TMU2 TICPI2 H 460 TMU3 TUNI3 H B00 TMU4 TUNI4 H B80 ATI H 480 PRI H 4A0 RTC CUI H 4C0 SCI ERI H 4E0 RXI H 500 TXI H 520 TEI H 540 WDT ITI H 560 RCMI H 580 REF ROVI 4 2 VBR H 600 H 5A0 Interrupt Completion type Peripheral module interr...

Page 182: ...et and to VBR offset in other cases Exception code Stored in EXPEVT for a reset or general exception and in INTEVT for an interrupt IRL Interrupt request level pins IRL3 IRL0 Module source See the sections on the relevant peripheral modules Notes 1 When BRCR UBDE 1 PC DBR In other cases PC VBR H 100 2 The priority order of external interrupts and peripheral module interrupts can be set by software...

Page 183: ...t requested General exception requested Reset requested Figure 5 2 Instruction Execution and Exception Handling 5 5 2 Exception Source Acceptance A priority ranking is provided for all exceptions for use in determining which of two or more simultaneously generated exceptions should be accepted Five of the general exceptions the general illegal instruction exception slot illegal instruction excepti...

Page 184: ...er 1 Instruction n 2 General illegal instruction exception IF ID EX MA WB IF ID EX MA WB TLB miss instruction access 2 3 4 IF Instruction fetch ID Instruction decode EX Instruction execution MA Memory access WB Write back Instruction n 3 TLB miss instruction n Re execution of instruction n General illegal instruction exception instruction n 1 Re execution of instruction n 1 TLB miss instruction n ...

Page 185: ...errupt NMI occurs it can be held pending or accepted according to the setting made by software Thus normally SPC and SSR are saved and then the BL bit in SR is cleared to 0 to enable multiple exception state acceptance 5 5 4 Return from Exception Handling The RTE instruction is used to return from exception handling When the RTE instruction is executed the SPC contents are restored to PC and the S...

Page 186: ...BL bits are set to 1 the FD bit is cleared to 0 and the interrupt mask bits I3 I0 are set to B 1111 CPU and on chip peripheral module initialization is performed For details see the register descriptions in the relevant sections For some CPU functions the TRST pin and RESET pin must be driven low It is therefore essential to execute a power on reset and drive the TRST pin low when powering on If t...

Page 187: ...nitialization processing the VBR register is set to H 0000 0000 and in SR the MD RB and BL bits are set to 1 the FD bit is cleared to 0 and the interrupt mask bits I3 I0 are set to B 1111 CPU and on chip peripheral module initialization is performed For details see the register descriptions in the relevant sections Manual_reset EXPEVT H 00000020 VBR H 00000000 SR MD 1 SR RB 1 SR BL 1 SR I0 I3 B 11...

Page 188: ... In the initialization processing the VBR register is set to H 0000 0000 and in SR the MD RB and BL bits are set to 1 the FD bit is cleared to 0 and the interrupt mask bits I3 I0 are set to B 1111 CPU and on chip peripheral module initialization is performed For details see the register descriptions in the relevant sections H UDI_reset EXPEVT H 00000000 VBR H 00000000 SR MD 1 SR RB 1 SR BL 1 SR I0...

Page 189: ...n of VBR and SR is performed and a branch is made to PC H A000 0000 In the initialization processing the VBR register is set to H 0000 0000 and in SR the MD RB and BL bits are set to 1 the FD bit is cleared to 0 and the interrupt mask bits I3 I0 are set to B 1111 CPU and on chip peripheral module initialization is performed in the same way as in a manual reset For details see the register descript...

Page 190: ...of VBR and SR is performed and a branch is made to PC H A000 0000 In the initialization processing the VBR register is set to H 0000 0000 and in SR the MD RB and BL bits are set to 1 the FD bit is cleared to 0 and the interrupt mask bits I3 I0 are set to B 1111 CPU and on chip peripheral module initialization is performed in the same way as in a manual reset For details see the register descriptio...

Page 191: ...xception occurred The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR and the contents of R15 are saved in SGR Exception code H 040 for a read access or H 060 for a write access is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0400 To speed up TLB miss processing the offset is separate from that of other exc...

Page 192: ...dicates the ASID when this exception occurred The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR and the contents of R15 are saved in SGR Exception code H 040 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0400 To speed up TLB miss processing the offset is separate from that of other exceptions ITLB_miss_...

Page 193: ...bits is set in PTEH 31 10 ASID in PTEH indicates the ASID when this exception occurred The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR and the contents of R15 are saved in SGR Exception code H 080 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 Initial_write_exception TEA EXCEPTION_ADDRESS PTEH VPN...

Page 194: ... 32 bits at which this exception occurred is set in TEA and the corresponding virtual page number 22 bits is set in PTEH 31 10 ASID in PTEH indicates the ASID when this exception occurred The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR and the contents of R15 are saved in SGR Exception code H 0A0 for a read access or H 0C0 for a write access is ...

Page 195: ...ion occurred is set in TEA and the corresponding virtual page number 22 bits is set in PTEH 31 10 ASID in PTEH indicates the ASID when this exception occurred The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR and the contents of R15 are saved in SGR Exception code H 0A0 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made...

Page 196: ...set in TEA and the corresponding virtual page number 22 bits is set in PTEH 31 10 ASID in PTEH indicates the ASID when this exception occurred The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR and the contents of R15 are saved in SGR Exception code H 0E0 for a read access or H 100 for a write access is set in EXPEVT The BL MD and RB bits are set t...

Page 197: ...mber 22 bits is set in PTEH 31 10 ASID in PTEH indicates the ASID when this exception occurred The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR and the contents of R15 are saved in SGR Exception code H 0E0 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 For details see section 3 Memory Management Un...

Page 198: ...PA instruction are saved in SPC The values of SR and R15 when the TRAPA instruction is executed are saved in SSR and SGR The 8 bit immediate value in the TRAPA instruction is multiplied by 4 and the result is set in TRA 9 0 Exception code H 160 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 TRAPA_exception SPC PC 2 SSR SR SGR R15 TRA imm 2 EXPEVT H ...

Page 199: ...excluding LDC STC instructions that access GBR Transition address VBR H 0000 0100 Transition operations The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR and the contents of R15 are saved in SGR Exception code H 180 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 Operation is not guaranteed if an und...

Page 200: ...ons LDC STC RTE LDTLB SLEEP but excluding LDC STC instructions that access GBR Decoding of a PC relative MOV instruction or MOVA instruction in a delay slot Transition address VBR H 0000 0100 Transition operations The PC contents for the preceding delayed branch instruction are saved in SPC The SR and R15 contents when this exception occurred are saved in SSR and SGR Exception code H 1A0 is set in...

Page 201: ... SSR and the contents of R15 are saved in SGR Exception code H 800 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 Note FPU instructions are instructions in which the first 4 bits of the instruction code are F but excluding undefined instruction H FFFD and the LDS STS LDS L and STS L instructions corresponding to FPUL and FPSCR General_fpu_disable_ex...

Page 202: ... The PC contents for the preceding delayed branch instruction are saved in SPC The SR and R15 contents when this exception occurred are saved in SSR and SGR Exception code H 820 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 Slot_fpu_disable_exception SPC PC 2 SSR SR SGR R15 EXPEVT H 00000820 SR MD 1 SR RB 1 SR BL 1 PC VBR H 00000100 ...

Page 203: ...execution break the PC contents for the instruction at which the breakpoint is set are set in SPC The SR and R15 contents when the break occurred are saved in SSR and SGR Exception code H 1E0 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 It is also possible to branch to PC DBR For details of PC etc when a data break is set see section 20 User Break...

Page 204: ...rations The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR and the contents of R15 are saved in SGR Exception code H 120 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 FPU_exception SPC PC SSR SR SGR R15 EXPEVT H 00000120 SR MD 1 SR RB 1 SR BL 1 PC VBR H 00000100 ...

Page 205: ...GR Exception code H 1C0 is set in INTEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0600 When the BL bit in SR is 0 this interrupt is not masked by the interrupt mask bits in SR and is accepted at the highest priority level When the BL bit in SR is 1 a software setting can specify whether this interrupt is to be masked or accepted For details see section 19 Interrupt...

Page 206: ...ontents at the time of acceptance are set in SSR and SGR The code corresponding to the IRL 3 0 level is set in INTEVT See table 19 5 Interrupt Exception Handling Sources and Priority Order for the corresponding codes The BL MD and RB bits are set to 1 in SR and a branch is made to VBR H 0600 The acceptance level is not set in the interrupt mask bits in SR When the BL bit in SR is 1 the interrupt i...

Page 207: ... which the interrupt is accepted are set in SPC The SR and R15 contents at the time of acceptance are set in SSR and SGR The code corresponding to the interrupt source is set in INTEVT The BL MD and RB bits are set to 1 in SR and a branch is made to VBR H 0600 The module interrupt levels should be set as values between B 0000 and B 1111 in the interrupt priority registers IPRA IPRC in the interrup...

Page 208: ...slot instruction As a delayed branch instruction and its associated delay slot instruction are indivisible they are treated as a single instruction Consequently the priority order for exceptions that occur in these instructions differs from the usual priority order The priority order shown below is for the case where the delay slot instruction has only one data transfer a A check is performed for ...

Page 209: ...errupt request is held pending and is accepted after the BL bit in SR has been cleared to 0 by software If a nonmaskable interrupt NMI occurs it can be held pending or accepted according to the setting made by software In the sleep or standby state however an interrupt is accepted even if the BL bit in SR is set to 1 3 SPC when an exception occurs a Re execution type exception The PC value for the...

Page 210: ...F BT S BF S BRA or BSR instruction at address VBR H 100 VBR H 400 or VBR H 600 When the UBDE bit in the BRCR register is set to 1 and the user break debug support function is used do not locate a BT BF BT S BF S BRA or BSR instruction at the address indicated by the DBR register Note See section 20 4 User Break Debug Support Function ...

Page 211: ...n Divide By Zero Overflow Underflow and Inexact Comprehensive instructions Single precision double precision graphics support system control When the FD bit in SR is set to 1 the FPU cannot be used and an attempt to execute an FPU instruction will cause an FPU disable exception 6 2 Data Formats 6 2 1 Floating Point Format A floating point number consists of the following three fields Sign s Expone...

Page 212: ...1 Floating Point Number Formats and Parameters Parameter Single Precision Double Precision Total bit width 32 bits 64 bits Sign bit 1 bit 1 bit Exponent field 8 bits 11 bits Fraction field 23 bits 52 bits Precision 24 bits 53 bits Bias 127 1023 Emax 127 1023 Emin 126 1022 Floating point number value v is determined as follows If E Emax 1 and f 0 v is a non number NaN irrespective of sign s If E Em...

Page 213: ...ative zero H 80000000 H 80000000 00000000 Negative denormalized number H 80000001 to H 807FFFFF H 80000000 00000001 to H 800FFFFF FFFFFFFF Negative normalized number H 80800000 to H FF7FFFFF H 80100000 00000000 to H FFEFFFFF FFFFFFFF Negative infinity H FF800000 H FFF00000 00000000 Quiet non number H FF800001 to H FFBFFFFF H FFF00000 00000001 to H FFF7FFFF FFFFFFFF Signaling non number H FFC00000 ...

Page 214: ...on will not be generated in this case The qNAN values generated by the SH7750 Series as operation results are as follows Single precision qNaN H 7FBFFFFF Double precision qNaN H 7FF7FFFF FFFFFFFF See the individual instruction descriptions for details of floating point operations when a non number NaN is input 6 2 3 Denormalized Numbers For a denormalized number floating point value the exponent f...

Page 215: ...0 FR1 DR2 FR2 FR3 DR4 FR4 FR5 DR6 FR6 FR7 DR8 FR8 FR9 DR10 FR10 FR11 DR12 FR12 FR13 DR14 FR14 FR15 4 Single precision floating point vector registers FVi 4 registers An FV register comprises four FR registers FV0 FR0 FR1 FR2 FR3 FV4 FR4 FR5 FR6 FR7 FV8 FR8 FR9 FR10 FR11 FV12 FR12 FR13 FR14 FR15 5 Single precision floating point extended registers XFi 16 registers When FPSCR FR 0 XF0 XF15 indicate ...

Page 216: ...2 DR4 DR6 DR8 DR10 DR12 DR14 FV0 FV4 FV8 FV12 XD0 XMTRX XD2 XD4 XD6 XD8 XD10 XD12 XD14 FPR0_BANK1 FPR1_BANK1 FPR2_BANK1 FPR3_BANK1 FPR4_BANK1 FPR5_BANK1 FPR6_BANK1 FPR7_BANK1 FPR8_BANK1 FPR9_BANK1 FPR10_BANK1 FPR11_BANK1 FPR12_BANK1 FPR13_BANK1 FPR14_BANK1 FPR15_BANK1 XF0 XF1 XF2 XF3 XF4 XF5 XF6 XF7 XF8 XF9 XF10 XF11 XF12 XF13 XF14 XF15 FR0 FR1 FR2 FR3 FR4 FR5 FR6 FR7 FR8 FR9 FR10 FR11 FR12 FR13 F...

Page 217: ... bit register pair 64 bits PR Precision mode PR 0 Floating point instructions are executed as single precision operations PR 1 Floating point instructions are executed as double precision operations graphics support instructions are undefined Do not set SZ and PR to 1 simultaneously this setting is reserved SZ PR 11 Reserved FPU operation instruction is undefined DN Denormalization mode DN 0 A den...

Page 218: ...eral register R1 to a single precision floating point number the processing flow is as follows R1 LDS instruction FPUL single precision FLOAT instruction FR1 6 4 Rounding In a floating point instruction rounding is performed when generating the final operation result from the intermediate result Therefore the result of combination instructions such as FMAC FTRV and FIPR will differ from the result...

Page 219: ...sources E V Z O U and I and the FPSCR flag and enable fields contain bits corresponding to sources V Z O U and I but not E Thus FPU errors cannot be disabled When an exception source occurs the corresponding bit in the cause field is set to 1 and 1 is added to the corresponding bit in the flag field When an exception source does not occur the corresponding bit in the cause field is cleared to 0 bu...

Page 220: ...en rounding mode RN infinity with the same sign as the unrounded value is generated Underflow U When FPSCR DN 0 a denormalized number with the same sign as the unrounded value or zero with the same sign as the unrounded value is generated When FPSCR DN 1 zero with the same sign as the unrounded value is generated Inexact exception I An inexact result is generated 6 6 Graphics Support Functions The...

Page 221: ...processing for angle parallel movement basically requires a 4 4 matrix the SH7750 Series supports 4 dimensional operations Matrix 4 4 matrix 4 4 This operation requires the execution of four FTRV instructions Since approximate value computations are performed to enable high speed computation the inexact exception I bit in the cause field and flag field is always set to 1 when an FTRV instruction i...

Page 222: ...4 6 8 10 12 14 n 0 to 15 These instructions enable two single precision 2 32 bit data items to be transferred that is the transfer performance of these instructions is doubled FSCHG This instruction changes the value of the SZ bit in FPSCR enabling fast switching between use and non use of pair single precision data transfer Programming Note When FPSCR SZ 1 and big endian mode is used FMOV can be ...

Page 223: ...uted directly in memory operands in an operation that requires memory access are loaded into registers and the operation is executed between the registers Delayed Branches Except for the two branch instructions BF and BT the SH7750 Series branch instructions and RTE are delayed branches In a delayed branch the instruction following the branch is executed before the branch destination instruction T...

Page 224: ...TC L SR instructions access all SR bits after modification Constant Values An 8 bit constant value can be specified by the instruction code and an immediate value 16 bit and 32 bit constant values can be defined as literal constant values in memory and can be referenced by a PC relative load instruction MOV W disp PC Rn MOV L disp PC Rn There are no PC relative load instructions for floating point...

Page 225: ...Rn Operand is register Rn contents Register indirect Rn Effective address is register Rn contents Rn Rn Rn EA EA effective address Register indirect with post increment Rn Effective address is register Rn contents A constant is added to Rn after instruction execution 1 for a byte operand 2 for a word operand 4 for a longword operand 8 for a quadword operand Rn Rn 1 2 4 8 Rn 1 2 4 8 Rn EA After ins...

Page 226: ... 2 4 disp zero extended Byte Rn disp EA Word Rn disp 2 EA Longword Rn disp 4 EA Indexed register indirect R0 Rn Effective address is sum of register Rn and R0 contents Rn R0 Rn R0 Rn R0 EA GBR indirect with displacement disp 8 GBR Effective address is register GBR contents with 8 bit displacement disp added After disp is zero extended it is multiplied by 1 byte 2 word or 4 longword according to th...

Page 227: ... is zero extended it is multiplied by 2 word or 4 longword according to the operand size With a longword operand the lower 2 bits of PC are masked PC H FFFFFFFC PC 4 disp 2 or PC H FFFFFFFC 4 disp 4 4 2 4 disp zero extended With longword operand Word PC 4 disp 2 EA Longword PC H FFFFFFFC 4 disp 4 EA PC relative disp 8 Effective address is PC 4 with 8 bit displacement disp added after being sign ex...

Page 228: ... TST AND OR or XOR instruction is zero extended imm 8 8 bit immediate data imm of MOV ADD or CMP EQ instruction is sign extended imm 8 8 bit immediate data imm of TRAPA instruction is zero extended and multiplied by 4 Note For the addressing modes below that use a displacement disp the assembler descriptions in this manual show the value before scaling 1 2 or 4 is performed according to the operan...

Page 229: ... individual bits Logical NOT of individual bits n n n bit shift Instruction code MSB LSB mmmm Register number Rm FRm nnnn Register number Rn FRn 0000 R0 FR0 0001 R1 FR1 1111 R15 FR15 mmm Register number DRm XDm Rm_BANK nnn Register number DRm XDm Rn_BANK 000 DR0 XD0 R0_BANK 001 DR2 XD2 R1_BANK 111 DR14 XD14 R7_BANK mm Register number FVm nn Register number FVn 00 FV0 01 FV4 10 FV8 11 FV12 iiii Imm...

Page 230: ... W Rm Rn Rn 2 Rn Rm Rn 0010nnnnmmmm0101 MOV L Rm Rn Rn 4 Rn Rm Rn 0010nnnnmmmm0110 MOV B Rm Rn Rm sign extension Rn Rm 1 Rm 0110nnnnmmmm0100 MOV W Rm Rn Rm sign extension Rn Rm 2 Rm 0110nnnnmmmm0101 MOV L Rm Rn Rm Rn Rm 4 Rm 0110nnnnmmmm0110 MOV B R0 disp Rn R0 disp Rn 10000000nnnndddd MOV W R0 disp Rn R0 disp 2 Rn 10000001nnnndddd MOV L Rm disp Rn Rm disp 4 Rn 0001nnnnmmmmdddd MOV B disp Rm R0 di...

Page 231: ...sp 4 GBR 11000010dddddddd MOV B disp GBR R0 disp GBR sign extension R0 11000100dddddddd MOV W disp GBR R0 disp 2 GBR sign extension R0 11000101dddddddd MOV L disp GBR R0 disp 4 GBR R0 11000110dddddddd MOVA disp PC R0 disp 4 PC H FFFFFFFC 4 R0 11000111dddddddd MOVT Rn T Rn 0000nnnn00101001 SWAP B Rm Rn Rm swap lower 2 bytes Rn 0110nnnnmmmm1000 SWAP W Rm Rn Rm swap upper lower words Rn 0110nnnnmmmm1...

Page 232: ...HI Rm Rn When Rn Rm unsigned 1 T Otherwise 0 T 0011nnnnmmmm0110 Comparison result CMP GT Rm Rn When Rn Rm signed 1 T Otherwise 0 T 0011nnnnmmmm0111 Comparison result CMP PZ Rn When Rn 0 1 T Otherwise 0 T 0100nnnn00010001 Comparison result CMP PL Rn When Rn 0 1 T Otherwise 0 T 0100nnnn00010101 Comparison result CMP STR Rm Rn When any bytes are equal 1 T Otherwise 0 T 0010nnnnmmmm1100 Comparison res...

Page 233: ...n 4 Rn Rm 4 Rm 32 32 64 64 bits 0000nnnnmmmm1111 MAC W Rm Rn Signed Rn Rm MAC MAC Rn 2 Rn Rm 2 Rm 16 16 64 64 bits 0100nnnnmmmm1111 MUL L Rm Rn Rn Rm MACL 32 32 32 bits 0000nnnnmmmm0111 MULS W Rm Rn Signed Rn Rm MACL 16 16 32 bits 0010nnnnmmmm1111 MULU W Rm Rn Unsigned Rn Rm MACL 16 16 32 bits 0010nnnnmmmm1110 NEG Rm Rn 0 Rm Rn 0110nnnnmmmm1011 NEGC Rm Rn 0 Rm T Rn borrow T 0110nnnnmmmm1010 Borrow...

Page 234: ...m R0 11001011iiiiiiii OR B imm R0 GBR R0 GBR imm R0 GBR 11001111iiiiiiii TAS B Rn When Rn 0 1 T Otherwise 0 T In both cases 1 MSB of Rn 0100nnnn00011011 Test result TST Rm Rn Rn Rm when result 0 1 T Otherwise 0 T 0010nnnnmmmm1000 Test result TST imm R0 R0 imm when result 0 1 T Otherwise 0 T 11001000iiiiiiii Test result TST B imm R0 GBR R0 GBR imm when result 0 1 T Otherwise 0 T 11001100iiiiiiii Te...

Page 235: ...hen Rn 0 Rn Rm Rn When Rn 0 Rn Rm MSB Rn 0100nnnnmmmm1100 SHAL Rn T Rn 0 0100nnnn00100000 MSB SHAR Rn MSB Rn T 0100nnnn00100001 LSB SHLD Rm Rn When Rn 0 Rn Rm Rn When Rn 0 Rn Rm 0 Rn 0100nnnnmmmm1101 SHLL Rn T Rn 0 0100nnnn00000000 MSB SHLR Rn 0 Rn T 0100nnnn00000001 LSB SHLL2 Rn Rn 2 Rn 0100nnnn00001000 SHLR2 Rn Rn 2 Rn 0100nnnn00001001 SHLL8 Rn Rn 8 Rn 0100nnnn00011000 SHLR8 Rn Rn 8 Rn 0100nnnn0...

Page 236: ... 4 PC When T 0 nop 10001001dddddddd BT S label Delayed branch when T 1 disp 2 PC 4 PC When T 0 nop 10001101dddddddd BRA label Delayed branch disp 2 PC 4 PC 1010dddddddddddd BRAF Rn Delayed branch Rn PC 4 PC 0000nnnn00100011 BSR label Delayed branch PC 4 PR disp 2 PC 4 PC 1011dddddddddddd BSRF Rn Delayed branch PC 4 PR Rn PC 4 PC 0000nnnn00000011 JMP Rn Delayed branch Rn PC 0100nnnn00101011 JSR Rn ...

Page 237: ... Rm SSR Rm SSR Rm 4 Rm 0100mmmm00110111 Privileged LDC L Rm SPC Rm SPC Rm 4 Rm 0100mmmm01000111 Privileged LDC L Rm DBR Rm DBR Rm 4 Rm 0100mmmm11110110 Privileged LDC L Rm Rn_BANK Rm Rn_BANK Rm 4 Rm 0100mmmm1nnn0111 Privileged LDS Rm MACH Rm MACH 0100mmmm00001010 LDS Rm MACL Rm MACL 0100mmmm00011010 LDS Rm PR Rm PR 0100mmmm00101010 LDS L Rm MACH Rm MACH Rm 4 Rm 0100mmmm00000110 LDS L Rm MACL Rm MA...

Page 238: ...0010 Privileged STC L SR Rn Rn 4 Rn SR Rn 0100nnnn00000011 Privileged STC L GBR Rn Rn 4 Rn GBR Rn 0100nnnn00010011 STC L VBR Rn Rn 4 Rn VBR Rn 0100nnnn00100011 Privileged STC L SSR Rn Rn 4 Rn SSR Rn 0100nnnn00110011 Privileged STC L SPC Rn Rn 4 Rn SPC Rn 0100nnnn01000011 Privileged STC L SGR Rn Rn 4 Rn SGR Rn 0100nnnn00110010 Privileged STC L DBR Rn Rn 4 Rn DBR Rn 0100nnnn11110010 Privileged STC L...

Page 239: ... Rm DRn Rm DRn Rm 8 Rm 1111nnn0mmmm1001 FMOV DRm Rn DRm Rn 1111nnnnmmm01010 FMOV DRm Rn Rn 8 Rn DRm Rn 1111nnnnmmm01011 FMOV DRm R0 Rn DRm R0 Rn 1111nnnnmmm00111 FLDS FRm FPUL FRm FPUL 1111mmmm00011101 FSTS FPUL FRn FPUL FRn 1111nnnn00001101 FABS FRn FRn H 7FFF FFFF FRn 1111nnnn01011101 FADD FRm FRn FRn FRm FRn 1111nnnnmmmm0000 FCMP EQ FRm FRn When FRn FRm 1 T Otherwise 0 T 1111nnnnmmmm0100 Compar...

Page 240: ...FPUL DRn 1111nnn010101101 FLOAT FPUL DRn float FPUL DRn 1111nnn000101101 FMUL DRm DRn DRn DRm DRn 1111nnn0mmm00010 FNEG DRn DRn H 8000 0000 0000 0000 DRn 1111nnn001001101 FSQRT DRn DRn DRn 1111nnn001101101 FSUB DRm DRn DRn DRm DRn 1111nnn0mmm00001 FTRC DRm FPUL long DRm FPUL 1111mmm000111101 Table 7 11 Floating Point Control Instructions Instruction Operation Instruction Code Privileged T Bit LDS ...

Page 241: ...mm11100 FMOV Rm XDn Rm XDn 1111nnn1mmmm1000 FMOV Rm XDn Rm XDn Rm 8 Rm 1111nnn1mmmm1001 FMOV R0 Rm XDn R0 Rm XDn 1111nnn1mmmm0110 FMOV XDm Rn XDm Rn 1111nnnnmmm11010 FMOV XDm Rn Rn 8 Rn XDm Rn 1111nnnnmmm11011 FMOV XDm R0 Rn XDm R0 Rn 1111nnnnmmm10111 FIPR FVm FVn inner_product FVm FVn FR n 3 1111nnmm11101101 FTRV XMTRX FVn transform_vector XMTRX FVn FVn 1111nn0111111101 FRCHG FPSCR FR SPFCR FR 11...

Page 242: ...Rev 6 0 07 02 page 192 of 986 ...

Page 243: ...the implementation of a processor Definitions in this section may not be applicable to SH 4 Series models other than the SH7750 Series 8 1 Pipelines Figure 8 1 shows the basic pipelines Normally a pipeline consists of five or six stages instruction fetch I decode and register read D execution EX SX F0 F1 F2 F3 data access NA MA and write back S FS An instruction is executed as a combination of bas...

Page 244: ... Register read Non memory data access Write back I D SX Operation NA S 4 Special Load Store Pipeline Instruction fetch Instruction decode Issue Register read Memory data access Write back I D SX Address calculation MA S 5 Floating Point Pipeline Instruction fetch Instruction decode Issue Register read Computation 2 Computation 3 Write back I D F1 Computation 1 F2 FS 6 Floating Point Extended Pipel...

Page 245: ...S L to FPUL LDTLB PREF STS L from FPUL FPSCR I D EX MA S 3 GBR based load store 1 issue cycle MOV BWL d GBR I D SX MA S 4 JMP RTS BRAF 2 issue cycles I D EX NA S D EX NA S 5 TST B 3 issue cycles I D SX MA S D SX NA S D SX NA S 6 AND B OR B XOR B 4 issue cycles I D SX MA S D SX NA S D SX NA S D SX MA S 7 TAS B 5 issue cycles I D EX MA S D EX MA S D EX NA S D EX NA S D EX MA S 8 RTE 5 issue cycles I...

Page 246: ...A S D EX NA S D EX NA S D EX NA S D EX NA S D EX NA S D EX NA S 14 LDC to DBR Rp_BANK SSR SPC VBR BSR 1 issue cycle I D EX NA S SX SX 15 LDC to GBR 3 issue cycles I D EX NA S D D SX SX 16 LDC to SR 4 issue cycles I D EX NA S D D D SX SX SX I D EX MA S 17 LDC L to DBR Rp_BANK SSR SPC VBR 1 issue cycle SX SX 18 LDC L to GBR 3 issue cycles I D EX MA S D D SX SX Figure 8 2 Instruction Execution Patter...

Page 247: ...A S D SX MA S 23 STC L from SGR 3 issue cycles I D SX NA S D SX NA S D SX MA S 24 LDS to PR JSR BSRF 2 issue cycles I D EX NA S D SX SX 25 LDS L to PR 2 issue cycles I D EX MA S D SX SX 26 STS from PR 2 issue cycles I D SX NA S D SX NA S 27 STS L from PR 2 issue cycles I D SX NA S D SX MA S 28 CLRMAC LDS to MACH L 1 issue cycle I D EX NA S F1 F1 F2 FS 29 LDS L to MACH L 1 issue cycle I D EX MA S F...

Page 248: ...X MA S CPU D EX MA S f1 FPU f1 f1 f1 F2 FS 36 Single precision floating point computation 1 issue cycle FCMP EQ FCMP GT FADD FLOAT FMAC FMUL FSUB FTRC FRCHG FSCHG I D F1 F2 FS 37 Single precision FDIV SQRT 1 issue cycle I D F1 F2 FS F3 F1 F2 FS 38 Double precision floating point computation 1 1 issue cycle FCNVDS FCNVSD FLOAT FTRC I D F1 F2 FS d F1 F2 FS 39 Double precision floating point computat...

Page 249: ...F1 F2 FS F1 F2 FS 42 FIPR 1 issue cycle I D F0 F1 F2 FS 43 FTRV 1 issue cycle F1 F2 FS D F0 I F1 F2 FS d F0 F1 F2 FS d F0 F1 F2 FS d F0 Notes Locks D stage Register read only Locks but no operation is executed Can overlap another f1 but not another F1 d D f1 Cannot overlap a stage of the same kind except when two instructions are executed in parallel Figure 8 2 Instruction Execution Patterns cont ...

Page 250: ...MP EQ Rm Rn CMP PL Rn SETT CMP GE Rm Rn CMP PZ Rn TST imm R0 CMP GT Rm Rn CMP STR Rm Rn TST Rm Rn 2 EX Group ADD imm Rn MOVT Rn SHLL2 Rn ADD Rm Rn NEG Rm Rn SHLL8 Rn ADDC Rm Rn NEGC Rm Rn SHLR Rn ADDV Rm Rn NOT Rm Rn SHLR16 Rn AND imm R0 OR imm R0 SHLR2 Rn AND Rm Rn OR Rm Rn SHLR8 Rn DIV0S Rm Rn ROTCL Rn SUB Rm Rn DIV0U ROTCR Rn SUBC Rm Rn DIV1 Rm Rn ROTL Rn SUBV Rm Rn DT Rn ROTR Rn SWAP B Rm Rn E...

Page 251: ...n MOV B disp GBR R0 MOV W R0 Rm Rn FMOV Rm DRn MOV B disp Rm R0 MOV W Rm Rn FMOV Rm XDn MOV B R0 Rm Rn MOV W Rm Rn FMOV DRm R0 Rn MOV B Rm Rn MOV W R0 disp GBR FMOV DRm Rn MOV B Rm Rn MOV W R0 disp Rn FMOV DRm Rn MOV B R0 disp GBR MOV W Rm R0 Rn FMOV DRm DRn MOV B R0 disp Rn MOV W Rm Rn FMOV DRm XDn MOV B Rm R0 Rn MOV W Rm Rn FMOV FRm FRn MOV B Rm Rn MOVCA L R0 Rn FMOV XDm R0 Rn MOV B Rm Rn OCBI R...

Page 252: ...FIPR FVm FVn FSQRT DRn FADD FRm FRn FLOAT FPUL DRn FSQRT FRn FCMP EQ FRm FRn FLOAT FPUL FRn FSUB DRm DRn FCMP GT FRm FRn FMAC FR0 FRm FRn FSUB FRm FRn FCNVDS DRm FPUL FMUL DRm DRn FTRC DRm FPUL FCNVSD FPUL DRn FMUL FRm FRn FTRC FRm FPUL FDIV DRm DRn FRCHG FTRV XMTRX FVn FDIV FRm FRn FSCHG ...

Page 253: ... DRm DRn LDS L Rm PR STC L SR Rn JMP Rn LDTLB STC L SSR Rn JSR Rn MAC L Rm Rn STC L VBR Rn LDC Rm DBR MAC W Rm Rn STS FPSCR Rn LDC Rm GBR MUL L Rm Rn STS MACH Rn LDC Rm Rp_BANK MULS W Rm Rn STS MACL Rn LDC Rm SPC MULU W Rm Rn STS PR Rn LDC Rm SR OR B imm R0 GBR STS L FPSCR Rn LDC Rm SSR RTE STS L FPUL Rn LDC Rm VBR RTS STS L MACH Rn LDC L Rm DBR SETS STS L MACL Rn LDC L Rm GBR SLEEP STS L PR Rn LD...

Page 254: ...e clocks are determined with the frequency control register FRQCR In this section machine cycles are based on the I clock unless otherwise specified For details of FRQCR see section 10 Clock Oscillation Circuits Instruction execution cycles are summarized in table 8 3 Penalty cycles due to a pipeline stall or freeze are not considered in this table Issue rate Interval between the issue of an instr...

Page 255: ... precision FADD FSUB or FMUL is the preceding instruction 2 cycles In the case of flow dependency latency may be exceptionally increased or decreased depending on the combination of sequential instructions figure 8 3 e When a floating point FP computation is followed by an FP register store the latency of the FP computation may be decreased by 1 cycle If there is a load of the shift amount immedia...

Page 256: ...tall of the ADD is eliminated by inserting three instructions without dependency Software performance can be improved by such instruction scheduling Other penalties arise in the event of exceptions or external data accesses as follows Instruction TLB miss Instruction access to external memory instruction cache miss etc Data access to external memory operand cache miss etc Data access to a memory m...

Page 257: ... A S 4 stall cycles EX group SHAD and EX group ADD cannot be executed in parallel Therefore SHAD is issued first and the following ADD is recombined with the next instruction EX group ADD and LS group MOV L can be executed in parallel Overlapping of stages in the 2nd instruction is possible AND B and MOV are fetched simultaneously but MOV is stalled due to resource locking After the lock is releas...

Page 258: ... write FR2 write I D F1 F2 FS d F1 F2 FS I D EX MA S 3 cycle latency for upper lower FR FR1 write FR0 write FLDI1 FR3 FIPR FV0 FV4 FMOV R1 XD14 FTRV XMTRX FV0 I D EX NA S I D d F0 F1 F2 FS Zero cycle latency 3 cycle increase 3 stall cycles I D EX MA S I D d F0 F1 F2 FS d F0 F1 FS F2 d F0 F2 F1 FS d F1 F0 F2 FS 2 cycle latency 1 cycle increase 3 stall cycles The following instruction ADD is not sta...

Page 259: ...2 FS 11 cycle latency 10 stall cycles latency 11 1 The registers are written back in program order D F1 F2 FS I d F1 F2 FS d F1 F2 FS d F1 F2 FS d F1 F2 FS F1 F2 FS EX NA S I D 7 cycle latency for lower FR 8 cycle latency for upper FR 6 stall cycles longest latency 8 2 FR2 write FR3 write D F1 F2 FS I d F1 F2 FS d F1 F2 FS d F1 F0 F0 F0 F0 F2 FS g Anti flow dependency EX MA S I D 5 stall cycles D ...

Page 260: ... DR2 I D F1 F2 FS d F1 F2 FS d F1 F2 FS d F1 F2 FS d F1 F2 FS F1 F2 FS EX MA S f1 EX MA S D f1 f1 F2 FS f1 F2 FS I D 5 stall cycles MAC W R1 R2 I D EX MA S f1 f1 f1 F2 FS f1 F2 FS I f1 D EX MA S f1 D EX MA S f1 F2 FS f1 F2 FS F1 F2 FS d F1 F2 FS d F1 F2 FS d F1 F2 FS d F1 F2 FS F1 I D 3 stall cycles 1 stall cycle 2 stall cycles MAC W R1 R2 MAC W R1 R2 FADD DR4 DR6 f1 stage can overlap preceding f1...

Page 261: ... Rm Rn LS 1 2 2 11 MOV W Rm Rn LS 1 2 2 12 MOV L Rm Rn LS 1 2 2 13 MOV B Rm Rn LS 1 1 2 2 14 MOV W Rm Rn LS 1 1 2 2 15 MOV L Rm Rn LS 1 1 2 2 16 MOV B disp Rm R0 LS 1 2 2 17 MOV W disp Rm R0 LS 1 2 2 18 MOV L disp Rm Rn LS 1 2 2 19 MOV B R0 Rm Rn LS 1 2 2 20 MOV W R0 Rm Rn LS 1 2 2 21 MOV L R0 Rm Rn LS 1 2 2 22 MOV B disp GBR R0 LS 1 2 3 23 MOV W disp GBR R0 LS 1 2 3 24 MOV L disp GBR R0 LS 1 2 3 ...

Page 262: ... 1 3 7 12 MA 4 3 7 41 MOVT Rn EX 1 1 1 42 OCBI Rn LS 1 1 2 10 MA 4 1 2 43 OCBP Rn LS 1 1 5 11 MA 4 1 5 44 OCBWB Rn LS 1 1 5 11 MA 4 1 5 45 PREF Rn LS 1 1 2 46 SWAP B Rm Rn EX 1 1 1 47 SWAP W Rm Rn EX 1 1 1 Data transfer instructions 48 XTRCT Rm Rn EX 1 1 1 49 ADD Rm Rn EX 1 1 1 50 ADD imm Rn EX 1 1 1 51 ADDC Rm Rn EX 1 1 1 52 ADDV Rm Rn EX 1 1 1 53 CMP EQ imm R0 MT 1 1 1 54 CMP EQ Rm Rn MT 1 1 1 5...

Page 263: ... Rn CO 2 4 4 34 F1 4 2 71 MULS W Rm Rn CO 2 4 4 34 F1 4 2 72 MULU W Rm Rn CO 2 4 4 34 F1 4 2 73 NEG Rm Rn EX 1 1 1 74 NEGC Rm Rn EX 1 1 1 75 SUB Rm Rn EX 1 1 1 76 SUBC Rm Rn EX 1 1 1 Fixed point arithmetic instructions 77 SUBV Rm Rn EX 1 1 1 78 AND Rm Rn EX 1 1 1 79 AND imm R0 EX 1 1 1 80 AND B imm R0 GBR CO 4 4 6 81 NOT Rm Rn EX 1 1 1 82 OR Rm Rn EX 1 1 1 83 OR imm R0 EX 1 1 1 84 OR B imm R0 GBR ...

Page 264: ...1 1 1 99 SHLD Rm Rn EX 1 1 1 100 SHLL Rn EX 1 1 1 101 SHLL2 Rn EX 1 1 1 102 SHLL8 Rn EX 1 1 1 103 SHLL16 Rn EX 1 1 1 104 SHLR Rn EX 1 1 1 105 SHLR2 Rn EX 1 1 1 106 SHLR8 Rn EX 1 1 1 Shift instructions 107 SHLR16 Rn EX 1 1 1 108 BF disp BR 1 2 or 1 1 109 BF S disp BR 1 2 or 1 1 110 BT disp BR 1 2 or 1 1 111 BT S disp BR 1 2 or 1 1 112 BRA disp BR 1 2 1 113 BRAF Rn CO 2 3 4 114 BSR disp BR 1 2 14 SX...

Page 265: ... 3 2 132 LDC Rm SR CO 4 4 16 SX 3 2 133 LDC Rm SSR CO 1 3 14 SX 3 2 134 LDC Rm SPC CO 1 3 14 SX 3 2 135 LDC Rm VBR CO 1 3 14 SX 3 2 136 LDC L Rm DBR CO 1 1 3 17 SX 3 2 137 LDC L Rm GBR CO 3 3 3 18 SX 3 2 138 LDC L Rm Rp_BANK CO 1 1 3 17 SX 3 2 139 LDC L Rm SR CO 4 4 4 19 SX 3 2 140 LDC L Rm SSR CO 1 1 3 17 SX 3 2 141 LDC L Rm SPC CO 1 1 3 17 SX 3 2 142 LDC L Rm VBR CO 1 1 3 17 SX 3 2 143 LDS Rm MA...

Page 266: ...2 161 STC L SR Rn CO 2 2 2 22 162 STC L SSR Rn CO 2 2 2 22 163 STC L SPC Rn CO 2 2 2 22 164 STC L VBR Rn CO 2 2 2 22 165 STS MACH Rn CO 1 3 30 166 STS MACL Rn CO 1 3 30 167 STS PR Rn CO 2 2 26 168 STS L MACH Rn CO 1 1 1 31 169 STS L MACL Rn CO 1 1 1 31 System control instructions 170 STS L PR Rn CO 2 2 2 27 171 FLDI0 FRn LS 1 0 1 172 FLDI1 FRn LS 1 0 1 173 FMOV FRm FRn LS 1 0 1 174 FMOV S Rm FRn L...

Page 267: ... 10 1 192 FSUB FRm FRn FE 1 3 4 36 193 FTRC FRm FPUL FE 1 3 4 36 194 FMOV DRm DRn LS 1 0 1 195 FMOV Rm DRn LS 1 2 2 196 FMOV Rm DRn LS 1 1 2 2 197 FMOV R0 Rm DRn LS 1 2 2 198 FMOV DRm Rn LS 1 1 2 199 FMOV DRm Rn LS 1 1 1 2 Single precision floating point instructions 200 FMOV DRm R0 Rn LS 1 1 2 201 FABS DRn LS 1 0 1 202 FADD DRm DRn FE 1 7 8 9 39 F1 2 6 203 FCMP EQ DRm DRn CO 2 3 5 40 F1 2 2 204 F...

Page 268: ...1 2 FPU system control instructions 221 STS L FPSCR Rn CO 1 1 1 2 222 FMOV DRm XDn LS 1 0 1 223 FMOV XDm DRn LS 1 0 1 224 FMOV XDm XDn LS 1 0 1 225 FMOV Rm XDn LS 1 2 2 226 FMOV Rm XDn LS 1 1 2 2 227 FMOV R0 Rm XDn LS 1 2 2 228 FMOV XDm Rn LS 1 1 2 229 FMOV XDm Rm LS 1 1 1 2 230 FMOV XDm R0 Rn LS 1 1 2 231 FIPR FVm FVn FE 1 4 5 42 F1 3 1 232 FRCHG FE 1 1 4 36 233 FSCHG FE 1 1 4 36 F0 2 4 Graphics ...

Page 269: ...truction the latency of the floating point computation is decreased by 1 cycle 2 When the preceding instruction loads the shift amount of the following SHAD SHLD the latency of the load is increased by 1 cycle 3 When an LS group instruction with a latency of less than 3 cycles is followed by a double precision floating point instruction FIPR or FTRV the latency of the first instruction is increase...

Page 270: ...Rev 6 0 07 02 page 220 of 986 ...

Page 271: ...er Down Modes The following power down modes and functions are provided Sleep mode Deep sleep mode Standby mode Hardware standby mode Module standby function TMU RTC SCI SCIF DMAC SQ and UBC on chip peripheral modules Note SH7750S SH7750R only Table 9 1 shows the conditions for entering these modes from the program execution state the status of the CPU and peripheral modules in each mode and the m...

Page 272: ...STBCR and DSLP bit is 1 in STBCR2 Operating Halted registers held Held Operating DMA halted Held Self refreshing Interrupt Reset Standby SLEEP instruction executed while STBY bit is 1 in STBCR Halted Halted registers held Held Halted Held Self refreshing Interrupt Reset Hardware standby SH7750S SH7750R Setting CA pin low Halted Halted Undefined Halted High impedance Undefined Power on reset Module...

Page 273: ...00000 H FE0A0000 H 1E0A0000 32 Clock release register 00 CLKSTPCLR00 W H 00000000 H FE0A0008 H 1E0A0008 32 Note SH7750R only 9 1 3 Pin Configuration Table 9 3 shows the pins used for power down mode control Table 9 3 Power Down Mode Pins Pin Name Abbreviation I O Function Processor status 1 Processor status 0 STATUS1 STATUS0 Output Indicate the processor s operating status STATUS1 STATUS0 HH Reset...

Page 274: ... the PHZ bit is set to 1 peripheral module related pins go to the high impedance state in standby mode For the relevant pins see section 9 2 2 Peripheral Module Pin High Impedance Control Bit 6 PHZ Description 0 Peripheral module related pins are in normal state Initial value 1 Peripheral module related pins go to high impedance state Bit 5 Peripheral Module Pin Pull Up Control PPU Controls the st...

Page 275: ...nit TMU among the on chip peripheral modules The clock supply to the TMU is stopped when the MSTP2 bit is set to 1 Bit 2 MSTP2 Description 0 TMU operates Initial value 1 TMU clock supply is stopped Bit 1 Module Stop 1 MSTP1 Specifies stopping of the clock supply to the realtime clock RTC among the on chip peripheral modules The clock supply to the RTC is stopped when the MSTP1 bit is set to 1 When...

Page 276: ...bove pins are used as port output pins For details of pin states see Appendix E Pin Functions 9 2 3 Peripheral Module Pin Pull Up Control When bit 5 in the standby control register STBCR is cleared to 0 peripheral module related pins are pulled up when in the input or high impedance state Relevant Pins SCI related pins MD0 SCK MD1 TXD2 MD2 RXD2 MD7 TXD MD8 RTS2 SCK2 MRESET RXD CTS2 DMA related pin...

Page 277: ...Initial value 1 Transition to deep sleep mode on execution of SLEEP instruction Note When the STBY bit in the STBCR register is 0 Bit 6 SH7750R Only STATUS Pin High Impedance Control STHZ This bit selects whether the STATUS0 and 1 pins are set to high impedance when in hardware standby mode Bit 6 STHZ Description 0 Sets STATUS0 1 pins to high impedance when in hardware standby mode Initial value 1...

Page 278: ... 9 2 5 Clock Stop Register 00 CLKSTP00 SH7750R Only Clock stop register 00 CLKSTP00 controls the operation clock for peripheral modules To resume supply of the clock signal write a 1 to the corresponding bit in the CLKSTPCLR00 register Writing a 0 to the CLKSTP00 register does not affect the register s value The CLKSTP00 register is a 32 bit register that can be read from or written to It is initi...

Page 279: ...TMU 9 2 6 Clock Stop Clear Register 00 CLKSTPCLR00 SH7750R Only The clock stop clear register 00 CLKSTPCLR00 is a 32 bit write only register that clears the corresponding bits of the CLKSTP00 register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W W W W W W W W W W W W W W W W W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0...

Page 280: ...e corresponding to the interrupt source is set in the INTEVT register Exit by Reset Sleep mode is exited by means of a power on or manual reset via the RESET pin or a power on or manual reset executed when the watchdog timer overflows 9 4 Deep Sleep Mode 9 4 1 Transition to Deep Sleep Mode If a SLEEP instruction is executed when the STBY bit in STBCR is cleared to 0 and the DSLP bit in STBCR2 is s...

Page 281: ...ate controller All registers On chip oscillation circuits All registers Timer unit TSTR register All registers except TSTR Realtime clock All registers Direct memory access controller All registers Serial communication interface See Appendix A Address List See Appendix A Address List Notes DMA transfer should be terminated before making a transition to standby mode Transfer results are not guarant...

Page 282: ...level is higher than the SR register I3 I0 mask level 2 GPIO can be used to cancel standby mode when the RTC clock 32 768 kHz is operating when the GPIO level is higher than the SR register I3 I0 mask level Exit by Reset Standby mode is exited by means of a reset power on or manual via the RESET pin The RESET pin should be held low until clock oscillation stabilizes The internal clock continues to...

Page 283: ...gister to 1 enables the clock supply to the corresponding on chip peripheral modules to be halted Use of this function allows power consumption in sleep mode to be further reduced In the module standby state the on chip peripheral module external pins retain their states prior to halting of the modules and most registers retain their states prior to halting of the modules ...

Page 284: ...pped 2 MSTP0 0 SCI operates 1 Clock supplied to SCI is stopped Notes 1 The register initialized is the same as in standby mode but initialization is not performed if the RTC clock is not in use see section 12 Timer Unit TMU 2 The counter operates when the START bit in RCR2 is 1 see section 11 Realtime Clock RTC 3 Terminate DMA transfers prior to making the transition to module standby mode If you ...

Page 285: ...n in the standby mode depends on the CPG status as follows 1 In standby mode The clock remains stopped and a transition is made to the hardware standby state 2 When WDT is operating when standby mode is exited by interrupt Standby mode is momentarily exited the CPU restarts and then a transition is made to hardware standby mode Note that the level of the CA pin must be kept low while in hardware s...

Page 286: ... is shown below The meaning of the STATUS pin settings is as follows Reset HH STATUS1 high STATUS0 high Sleep HL STATUS1 high STATUS0 low Standby LH STATUS1 low STATUS0 high Normal LL STATUS1 low STATUS0 low The meaning of the clock units is as follows Bcyc Bus clock cycle Pcyc Peripheral clock cycle ...

Page 287: ...c PLL stabilization time Figure 9 1 STATUS Output in Power On Reset Manual Reset CKIO STATUS Normal Reset Normal SCK2 0 30 Bcyc 0 Bcyc Note In a manual reset STATUS HH reset is set and an internal reset started after waiting until the end of the currently executing bus cycle Figure 9 2 STATUS Output in Manual Reset ...

Page 288: ...9 3 STATUS Output in Standby Interrupt Sequence Standby Power On Reset Reset CKIO 1 STATUS Normal Reset Normal 0 10 Bcyc Standby Oscillation stops SCK2 2 0 30 Bcyc Notes 1 When standby mode is exited by means of a power on reset a WDT count is not performed Hold low for the PLL oscillation stabilization time 2 Undefined Figure 9 4 STATUS Output in Standby Power On Reset Sequence ...

Page 289: ...Reset Normal 0 10 Bcyc Standby Oscillation stops SCK2 2 0 30 Bcyc Notes 1 When standby mode is exited by means of a manual reset a WDT count is not performed Hold low for the PLL oscillation stabilization time 2 Undefined Figure 9 5 STATUS Output in Standby Manual Reset Sequence ...

Page 290: ...Figure 9 6 STATUS Output in Sleep Interrupt Sequence Sleep Power On Reset Reset CKIO STATUS Normal Reset Sleep Normal 0 10 Bcyc 0 30 Bcyc 1 SCK2 2 Notes 1 When sleep mode is exited by means of a power on reset hold low for the oscillation stabilization time 2 Undefined Figure 9 7 STATUS Output in Sleep Power On Reset Sequence ...

Page 291: ...v 6 0 07 02 page 241 of 986 Sleep Manual Reset Reset STATUS Normal Reset Sleep Normal CKIO 0 30 Bcyc 0 30 Bcyc Note Hold low until STATUS reset SCK2 Figure 9 8 STATUS Output in Sleep Manual Reset Sequence ...

Page 292: ...e 9 9 STATUS Output in Deep Sleep Interrupt Sequence Deep Sleep Power On Reset Reset CKIO STATUS Normal Sleep Reset Normal 0 10 Bcyc 0 30 Bcyc 1 SCK2 2 Notes 1 When deep sleep mode is exited by means of a power on reset hold low for the oscillation stabilization time 2 Undefined Figure 9 10 STATUS Output in Deep Sleep Power On Reset Sequence ...

Page 293: ...07 02 page 243 of 986 Deep Sleep Manual Reset Reset STATUS Normal Sleep Reset Normal CKIO 0 30 Bcyc 0 30 Bcyc Note Hold low until STATUS reset SCK2 Figure 9 11 STATUS Output in Deep Sleep Manual Reset Sequence ...

Page 294: ...ust be kept low while in hardware standby mode After setting the RESET pin level low the clock starts when the CA pin level is switched to high CKIO CA SCK2 High STATUS Reset 0 10 Bcyc 0 10 Bcyc Waiting for end of bus cycle 2 Notes 1 Same at sleep and reset 2 Undefined 3 High impedance when STBCR2 STHZ 0 Normal 1 Standby 3 Figure 9 12 Hardware Standby Mode Timing When CA Low in Normal Operation ...

Page 295: ...45 of 986 CKIO High CA STATUS Standby 0 10 Bcyc Normal High SCK2 WDT count WDT overflow Interrupt request Note High impedance when STBCR2 STHZ 0 Standby Figure 9 13 Hardware Standby Mode Timing When CA Low in WDT Operation ...

Page 296: ...0s Max 50 µs Note VDDQ VDD CPG VDD PLL1 VDD PLL2 VDD min Figure 9 14 Timing When Power Other than VDD RTC is Off CA VDD RTC SCK2 VDD VDDQ Min 0s Note VDD VDD PLL1 2 VDDQ VDD CPG Power on oscillation setting time Figure 9 15 Timing When VDD RTC Power is Off On ...

Page 297: ...k Pφ used by the peripheral modules and the bus clock CKIO used by the external bus interface Six clock modes Any of six clock operating modes can be selected with different combinations of CPU clock bus clock and peripheral module clock division ratios after a power on reset Frequency change function PLL phase locked loop circuits and a frequency divider in the CPG enable the CPU clock bus clock ...

Page 298: ...Internal reset generation in watchdog timer mode An internal reset is executed on counter overflow Power on reset or manual reset can be selected Interrupt generation in interval timer mode An interval timer interrupt is generated on counter overflow Selection of eight counter input clocks Any of eight clocks can be selected scaled from the 1 clock of frequency divider 2 shown in figure 10 1 The C...

Page 299: ...l register STBCR2 Standby control register 2 Oscillator circuit PLL circuit 1 Frequency divider 2 Crystal oscillator Frequency divider 1 PLL circuit 2 CPU clock Iø cycle Icyc Peripheral module clock Pø cycle Pcyc Bus clock Bø cycle Bcyc CPG control unit Clock frequency control circuit Standby control circuit Bus interface Internal bus XTAL EXTAL MD8 CKIO MD2 MD1 MD0 FRQCR STBCR2 1 1 2 1 3 1 4 1 6 ...

Page 300: ... Frequency divider 2 Crystal oscillator CPU clock Iø cycle Icyc Peripheral module clock Pø cycle Pcyc Bus clock Bø cycle Bcyc CPG control unit Clock frequency control circuit Standby control circuit Bus interface Internal bus XTAL EXTAL MD8 CKIO MD2 MD1 MD0 FRQCR STBCR2 1 1 2 1 3 1 4 1 6 1 8 6 12 PLL circuit 2 1 STBCR Figure 10 1 2 Block Diagram of CPG SH7750R ...

Page 301: ...nput from the EXTAL pin is supplied internally without using PLL circuit 1 Frequency Divider 2 Frequency divider 2 generates the CPU clock Iφ bus clock Bφ and peripheral module clock Pφ The division ratio is set in the frequency control register Clock Frequency Control Circuit The clock frequency control circuit controls the clock frequency by means of the MD pins and frequency control register St...

Page 302: ... resonator is connected directly to EXTAL and XTAL Clock output pin CKIO Output Used as external clock output pin Level can also be fixed CKIO enable pin CKE Output 0 when CKIO output clock is unstable and in case of synchronous DRAM self refreshing Note Set to 1 in a power on reset For details of synchronous DRAM self refreshing see section 13 3 5 Synchronous DRAM Interface 10 2 3 CPG Register Co...

Page 303: ...n off of the frequency divider is solely determined by the clock operating mode 2 For the ranges of input clock frequency see the descriptions of the EXTAL clock input frequency fEX and CKIO clock output fOP in section 22 3 1 Clock and Control Signal Timing Table 10 3 2 Clock Operating Modes SH7750R External Pin Combination Frequency vs Input Clock Clock Operating Mode MD2 MD1 MD0 PLL1 PLL2 CPU Cl...

Page 304: ...e For the lower 9 bits of FRQCR do not set values other than those shown in the table 10 4 CPG Register Description 10 4 1 Frequency Control Register FRQCR The frequency control register FRQCR is a 16 bit readable writable register that specifies use non use of clock output from the CKIO pin PLL circuit 1 and 2 on off control and the CPU clock bus clock and peripheral module clock frequency divisi...

Page 305: ...he CKIO pin goes to the high impedance state operation continues at the operating frequency before this state was entered When the CKIO pin becomes high impedance it is pulled up Bit 11 CKOEN Description 0 CKIO pin goes to high impedance state pulled up 1 Clock is output from CKIO pin Initial value Note It is not pulled up in hardware standby mode Bit 10 PLL Circuit 1 Enable PLL1EN Specifies wheth...

Page 306: ...ecify the bus clock frequency division ratio with respect to the input clock 1 2 frequency divider or PLL circuit 1 output frequency Bit 5 BFC2 Bit 4 BFC1 Bit 3 BFC0 Description 0 0 0 1 1 1 2 1 0 1 3 1 1 4 1 0 0 1 6 1 1 8 Other than the above Setting prohibited Do not set Bits 2 to 0 Peripheral Module Clock Frequency Division Ratio PFC These bits specify the peripheral module clock frequency divis...

Page 307: ...LL1EN bit to 1 3 Internal processor operation stops temporarily and the WDT starts counting up The internal clock stops and an unstable clock is output to the CKIO pin 4 After the WDT count overflows clock supply begins within the chip and the processor resumes operation The WDT stops after overflowing 10 5 2 Changing PLL Circuit 1 Starting Stopping When PLL Circuit 2 is On When PLL circuit 2 is o...

Page 308: ...DT stops after overflowing 10 5 4 Changing Bus Clock Division Ratio When PLL Circuit 2 is Off If PLL circuit 2 is off when the bus clock frequency division ratio is changed a WDT count is not performed 1 Set the BFC2 BFC0 bits to the desired value 2 The set clock is switched to immediately 10 5 5 Changing CPU or Peripheral Module Clock Division Ratio When the CPU or peripheral module clock frequen...

Page 309: ...release Internal reset request Interrupt request Standby control Reset control Interrupt control WTCSR WTCNT Bus interface Clock selection Overflow Frequency divider Clock selector Clock WDT WTCSR Watchdog timer control status register WTCNT Watchdog timer counter Standby mode Frequency divider 2 1 clock Figure 10 2 Block Diagram of WDT ...

Page 310: ...te with the upper byte set to H 5A or H A5 respectively Byte and longword size writes cannot be used Use byte access when reading 10 8 WDT Register Descriptions 10 8 1 Watchdog Timer Counter WTCNT The watchdog timer counter WTCNT is an 8 bit readable writable counter that counts up on the selected clock When WTCNT overflows a reset is generated in watchdog timer mode or an interrupt in interval ti...

Page 311: ...WOVF IOVF CKS2 CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 Timer Enable TME Specifies starting and stopping of timer operation Clear this bit to 0 when using the WDT in standby mode or to change a clock frequency Bit 7 TME Description 0 Up count stopped WTCNT value retained Initial value 1 Up count started Bit 6 Timer Mode Select WT IT IT IT IT Specifies wheth...

Page 312: ...to 0 CKS2 CKS0 These bits select the clock used for the WTCNT count from eight clocks obtained by dividing the frequency divider 2 input clock The overflow periods shown in the following table are for use of a 33 MHz input clock with frequency divider 1 off and PLL circuit 1 on 6 Note When PLL1 is switched on or off the clock following the switch is used Description Bit 2 CKS2 Bit 1 CKS1 Bit 0 CKS...

Page 313: ...rite data Address H FFC0000C H 1FC0000C WTCSR write WTCNT write Figure 10 3 Writing to WTCNT and WTCSR 10 9 Using the WDT 10 9 1 Standby Clearing Procedure The WDT is used when clearing standby mode by means of an NMI or other interrupt The procedure is shown below As the WDT does not operate when standby mode is cleared with a reset the RESET pin should be held low until the clock stabilizes 1 Be...

Page 314: ...illation stabilization time see section 22 3 1 Clock and Control Signal Timing 3 When the frequency control register FRQCR is modified the clock stops and the standby state is entered temporarily The WDT starts counting 4 When the WDT count overflows the CPG starts clock supply and the processor resumes operation The WOVF flag in the WTCSR register is not set at this time 5 The counter stops at a ...

Page 315: ...egister to 1 and sends an interval timer interrupt request to INTC The counter continues counting 10 10 Notes on Board Design When Using a Crystal Resonator Place the crystal resonator and capacitors close to the EXTAL and XTAL pins To prevent induction from interfering with correct oscillation ensure that no other signal lines cross the signal lines for these pins EXTAL XTAL SH7750 Series CL1 CL2...

Page 316: ...ower supply source and insert resistors RCB and RB and bypass capacitors CPB and CB close to the pins as noise filters VDD PLL1 CPB1 CPB2 CB RCB1 Recommended values RCB1 RCB2 10 CPB1 CPB2 10 F RB 10 CB 10 F RCB2 RB 3 3 V VSS PLL1 VDD PLL2 SH7750 Series VSS PLL2 VDD CPG VSS CPG Figure 10 5 Points for Attention when Using PLL Oscillator Circuit ...

Page 317: ...ister indicates a state of 64 Hz to 1 Hz within the RTC frequency divider Start stop function 30 second adjustment function Alarm interrupts Comparison with second minute hour day of week day month or year year is available only with the SH7750R can be selected as the alarm interrupt condition Periodic interrupts An interrupt period of 1 256 second 1 64 second 1 16 second 1 4 second 1 2 second 1 s...

Page 318: ...I PRI CUI RCR1 RCR2 RCR3 RYRCNT RMONCNT RWKCNT RDAYCNT RHRCNT RMINCNT RSECCNT RSECAR RMINAR RHRAR RDAYAR RWKAR RMONAR Prescaler RTC crystal oscillator RTC operation control unit RESET STBY etc Counter unit Interrupt control unit To registers Bus interface RYRAR Internal peripheral module bus Note SH7750R only Figure 11 1 Block Diagram of RTC ...

Page 319: ...he RTC power supply pins even when the RTC is not used 11 1 4 Register Configuration Table 11 2 summarizes the RTC registers Table 11 2 RTC Registers Initialization Name Abbrevia tion R W Power On Reset Manual Reset Standby Mode Initial Value P4 Address Area 7 Address Access Size 64 Hz counter R64CNT R Counts Counts Counts Undefined H FFC80000 H 1FC80000 8 Second counter RSECCNT R W Counts Counts ...

Page 320: ...k alarm register RWKAR R W Initialized 1 Held Held Undefined 1 H FFC8002C H 1FC8002C 8 Day alarm register RDAYAR R W Initialized 1 Held Held Undefined 1 H FFC80030 H 1FC80030 8 Month alarm register RMONAR R W Initialized 1 Held Held Undefined 1 H FFC80034 H 1FC80034 8 RTC control register 1 RCR1 R W Initialized Initialized Held H 00 3 H FFC80038 H 1FC80038 8 RTC control register 2 RCR2 R W Initial...

Page 321: ...ot be modified Bit 7 6 5 4 3 2 1 0 1 Hz 2 Hz 4 Hz 8 Hz 16 Hz 32 Hz 64 Hz Initial value 0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined R W R R R R R R R R 11 2 2 Second Counter RSECCNT RSECCNT is an 8 bit readable writable register used as a counter for setting and counting the BCD coded second value in the RTC It counts on the carry transition of the R64CNT 1Hz bit from 0 ...

Page 322: ...ts Initial value 0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined R W R R W R W R W R W R W R W R W 11 2 4 Hour Counter RHRCNT RHRCNT is an 8 bit readable writable register used as a counter for setting and counting the BCD coded hour value in the RTC It counts on the carry generated once per hour by the minute counter The setting range is decimal 00 to 23 The RTC will not o...

Page 323: ...te normally if any other value is set Write processing should be performed after stopping the count with the START bit in RCR2 or by using the carry flag RWKCNT is not initialized by a power on or manual reset or in standby mode Bits 7 to 3 are always read as 0 A write to these bits is invalid but the write value should always be 0 Bit 7 6 5 4 3 2 1 0 Day of week code Initial value 0 0 0 0 0 Undef...

Page 324: ...med according to whether or not the value is divisible by 400 100 and 4 Bits 7 and 6 are always read as 0 A write to these bits is invalid but the write value should always be 0 Bit 7 6 5 4 3 2 1 0 10 day units 1 day units Initial value 0 0 Undefined Undefined Undefined Undefined Undefined Undefined R W R R R W R W R W R W R W R W 11 2 7 Month Counter RMONCNT RMONCNT is an 8 bit readable writable ...

Page 325: ...0000 to 9999 The RTC will not operate normally if any other value is set Write processing should be performed after stopping the count with the START bit in RCR2 or by using the carry flag RYRCNT is not initialized by a power on or manual reset or in standby mode Bit 15 14 13 12 11 10 9 8 1000 year units 100 year units Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undef...

Page 326: ...ial value 0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined R W R W R W R W R W R W R W R W R W 11 2 10 Minute Alarm Register RMINAR RMINAR is an 8 bit readable writable register used as an alarm register for the RTC s BCD coded minute value counter RMINCNT When the ENB bit is set to 1 the RMINAR value is compared with the RMINCNT value Comparison between the counter and the ...

Page 327: ...alue should always be 0 Bit 7 6 5 4 3 2 1 0 ENB 10 hour units 1 hour units Initial value 0 0 Undefined Undefined Undefined Undefined Undefined Undefined R W R W R R W R W R W R W R W R W 11 2 12 Day of Week Alarm Register RWKAR RWKAR is an 8 bit readable writable register used as an alarm register for the RTC s BCD coded day of week value counter RWKCNT When the ENB bit is set to 1 the RWKAR value...

Page 328: ...AR RWKAR RDAYAR and RMONAR in which the ENB bit is set to 1 and the RCR1 alarm flag is set when the respective values all match The setting range is decimal 01 to 31 ENB bit The RTC will not operate normally if any other value is set The setting range for RDAYAR depends on the month and whether the year is a leap year so care is required when making the setting The ENB bit in RDAYAR is initialized...

Page 329: ...et The other fields in RMONAR are not initialized by a power on or manual reset or in standby mode Bits 6 and 5 are always read as 0 A write to these bits is invalid but the write value should always be 0 Bit 7 6 5 4 3 2 1 0 ENB 0 month unit 1 month units Initial value 0 0 0 Undefined Undefined Undefined Undefined Undefined R W R W R R R W R W R W R W R W 11 2 15 RTC Control Register 1 RCR1 RCR1 i...

Page 330: ...er is read Setting conditions Generation of a second counter carry or a 64 Hz counter carry when the 64 Hz counter is read When 1 is written to CF Bit 4 Carry Interrupt Enable Flag CIE Enables or disables interrupt generation when the carry flag CF is set to 1 Bit 4 CIE Description 0 Carry interrupt is not generated when CF flag is set to 1 Initial value 1 Carry interrupt is generated when CF flag...

Page 331: ...2 and 1 Reserved The initial value of these bits is undefined A write to these bits is invalid but the write value should always be 0 11 2 16 RTC Control Register 2 RCR2 RCR2 is an 8 bit readable writable register used for periodic interrupt control 30 second adjustment and frequency divider RESET and RTC count control RCR2 is basically initialized to H 09 by a power on reset except that the value...

Page 332: ...ES2 PES0 These bits specify the period for periodic interrupts Bit 6 PES2 Bit 5 PES1 Bit 4 PES0 Description 0 0 0 No periodic interrupt generation Initial value 1 Periodic interrupt generated at 1 256 second intervals 1 0 Periodic interrupt generated at 1 64 second intervals 1 Periodic interrupt generated at 1 16 second intervals 1 0 0 Periodic interrupt generated at 1 4 second intervals 1 Periodi...

Page 333: ...ter clock operation Bit 0 START Description 0 Second minute hour day day of week month and year counters are stopped 1 Second minute hour day day of week month and year counters operate normally Initial value Note The 64 Hz counter continues to operate unless stopped by means of the RTCEN bit 11 2 17 RTC Control Register 3 RCR3 and Year Alarm Register RYRAR SH7750R Only RCR3 and RYRAR are readable...

Page 334: ...tial value 0 0 0 0 0 0 0 0 R W R W R R R R R R R RYRAR Bit 15 14 13 12 11 10 9 8 1000 years 100 years Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 10 years 1 year Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R W R W R W R W R W R W R W R W R W ...

Page 335: ...y order Set RCR2 START to 1 a Setting time after stopping clock Clear carry flag Write to counter register Carry flag 1 No Yes Clear RCR1 CF to 0 Write 1 to RCR1 AF so that alarm flag is not cleared Set RYRCNT first and RSECCNT last Read RCR1 register and check CF bit b Setting time while clock is running Figure 11 2 Examples of Time Setting Procedures The procedure for setting the time after stop...

Page 336: ... a carry occurs during the write operation the write data is automatically updated and there will be an error in the set data The carry flag should therefore be used to check the write status If the carry flag RCR1 CF is set to 1 the write must be repeated The interrupt function can also be used to determine the carry flag status 11 3 2 Time Reading Procedures Figure 11 3 shows examples of the tim...

Page 337: ...ter Interrupt generated Yes Disable carry interrupts No b Reading time using interrupts Set RCR1 CIE to 1 Clear RCR1 CF to 0 Write 1 to RCR1 AF so that alarm flag is not cleared Clear RCR1 CIE to 0 Figure 11 3 Examples of Time Reading Procedures If a carry occurs while the time is being read the correct time will not be obtained and the read must be repeated The procedure for reading the time with...

Page 338: ...y with the SH7750R value or a combination of these Write 1 to the ENB bit in the alarm registers involved in the alarm setting and set the alarm time in the lower bits Write 0 to the ENB bit in registers not involved in the alarm setting When the counter and the alarm time match RCR1 AF is set to 1 Alarm detection can be confirmed by reading this bit but normally an interrupt is used If 1 has been...

Page 339: ...o set to 1 11 5 Usage Notes 11 5 1 Register Initialization After powering on and making the RCR1 register settings reset the frequency divider by setting RCR2 RESET to 1 and make initial settings for all the other registers 11 5 2 Carry Flag and Interrupt Flag in Standby Mode When the carry flag or interrupt flag is set to 1 at the same time this LSI transits to normal mode from standby mode by a ...

Page 340: ...ard 4 The crystal oscillation stabilization time depends on the mounted circuit constants floating capacitance etc and should be decided after consultation with the crystal resonator manufacturer 5 Place the crystal resonator and load capacitors Cin and Cout as close as possible to the chip Correct oscillation may not be possible if there is externally induced noise in the EXTAL2 and XTAL2 pins 6 ...

Page 341: ...unter provided for each channel For channels 0 to 2 selection of seven counter input clocks for each channel External clock TCLK on chip RTC output clock five internal clocks Pφ 4 Pφ 16 Pφ 64 Pφ 256 Pφ 1024 Pφ is the peripheral module clock For channels 3 and 4 selection is made among five internal clocks SH7750R only Channels 0 to 2 can also operate in module standby mode when the on chip RTC out...

Page 342: ...unit Interrupt contrun unit Counter unit Ch 0 1 Ch 2 Ch 3 4 2 Bus interface Internal peripheral module bus TCR TCOR TCNT TCR TCOR TCNT TCR2 TCOR2 TCNT2 TCPR2 Notes 1 Signals with 1 4 1 16 and 1 64 the Pφ frequency supplied to the on chip peripheral functions 2 SH7750R only Figure 12 1 Block Diagram of TMU 12 1 3 Pin Configuration Table 12 1 shows the TMU pins Table 12 1 TMU Pins Pin Name Abbreviat...

Page 343: ...Timer counter 0 TCNT0 R W Ini tialized Ini tialized Held 2 H FFFFFFFF H FFD8000C H 1FD8000C 32 Timer control register 0 TCR0 R W Ini tialized Ini tialized Held H 0000 H FFD80010 H 1FD80010 16 1 Timer constant register 1 TCOR1 R W Ini tialized Ini tialized Held H FFFFFFFF H FFD80014 H 1FD80014 32 Timer counter 1 TCNT1 R W Ini tialized Ini tialized Held 2 H FFFFFFFF H FFD80018 H 1FD80018 32 Timer co...

Page 344: ...mer control register 3 TCR3 R W Ini tialized Held Held H 0000 H FE100010 H 1E100010 16 4 3 Timer constant register 4 TCOR4 R W Ini tialized Held Held H FFFFFFFF H FE100014 H 1E100014 32 Timer counter 4 TCNT4 R W Ini tialized Held Held H FFFFFFFF H FE100018 H 1E100018 32 Timer control register 4 TCR4 R W Ini tialized Held Held H 0000 H FE10001C H 1E10001C 16 Notes 1 Not initialized in module standb...

Page 345: ...2 1 0 TCOE Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R W Bits 7 to 1 Reserved These bits are always read as 0 A write to these bits is invalid but the write value should always be 0 Bit 0 Timer Clock Pin Control TCOE Specifies whether timer clock pin TCLK is used as the external clock or input capture control input pin or as the on chip RTC output clock output pin Bit 0 TCOE Description 0 Ti...

Page 346: ...0 0 0 0 0 R W R R R R R R W R W R W Bits 7 to 3 Reserved These bits are always read as 0 A write to these bits is invalid but the write value should always be 0 Bit 2 Counter Start 2 STR2 Specifies whether timer counter 2 TCNT2 is operated or stopped Bit 2 STR2 Description 0 TCNT2 count operation is stopped Initial value 1 TCNT2 performs count operation Bit 1 Counter Start 1 STR1 Specifies whether...

Page 347: ...s restarted on resumption of the clock signal supply Bit 7 6 5 4 3 2 1 0 STR4 STR3 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R W R W Bits 7 to 2 Reserved These bits are always read as 0 Writing to these bits is invalid If a value is written to these bits it should always be 0 Bit 1 Counter Start 4 STR4 Specifies whether timer counter 4 TCNT4 runs or is stopped Bit 1 STR4 Description 0 Counting...

Page 348: ...gisters There are TCNT registers one for each channel Each TCNT counts down on the input clock selected by TPSC2 TPSC0 in the timer control register TCR When a TCNT counter underflows while counting down the underflow flag UNF is set in the corresponding timer control register TCR At the same time the timer constant register TCOR value is set in TCNT and the count down operation continues from the...

Page 349: ... used for channel 2 input capture control and control of interrupt generation in the event of input capture The TCR registers for channels 0 to 2 are initialized to H 0000 by a power on or manual reset but are not initialized and retain their contents in standby mode The TCR registers for channels 3 and 4 of the SH7750R are initialized to H 0000 by a power on reset but are not initialized and reta...

Page 350: ... 4 3 2 1 0 UNIE TPSC2 TPSC1 TPSC0 Initial value 0 0 0 0 0 0 0 0 R W R R R W R R R W R W R W Bits 15 to 9 7 and 6 Channels 0 and 1 Bits 15 to 10 Channel 2 Reserved These bits are always read as 0 A write to these bits is invalid but the write value should always be 0 Bit 9 Input Capture Interrupt Flag ICPF Channel 2 Only Status flag provided in channel 2 only that indicates the occurrence of input ...

Page 351: ... the TCOE bit in the TOCR register The CKEG bits specify whether the rising edge or falling edge of the TCLK signal is used to set the TCNT2 value in the input capture register TCPR2 The TCNT2 value is set in TCPR2 only when the TCR2 ICPF bit is 0 When the TCR2 ICPF bit is 1 TCPR2 is not set in the event of input capture When input capture occurs a DMAC transfer request is generated regardless of ...

Page 352: ...lue 1 Count input capture register set on falling edge 1 X Count input capture register set on both rising and falling edges Note X 0 or 1 don t care Bits 2 to 0 Timer Prescaler 2 to 0 TPSC2 TPSC0 These bits select the TCNT count clock With channels 0 to 2 when the on chip RTC output clock is selected as the count clock for a channel that channel can operate even in module standby mode When anothe...

Page 353: ...input capture function is controlled by means of the input capture control bits ICPE and clock edge bits CKEG in TCR2 When input capture occurs the TCNT2 value is copied into TCPR2 The value is set in TCPR2 only when the ICPF bit in TCR2 is 0 TCPR2 is not initialized by a power on or manual reset or in standby mode Bit 31 30 29 2 1 0 Initial value Undefined R W R R R R R R ...

Page 354: ...e same time the value is copied from TCOR into TCNT and the count down continues auto reload function Example of Count Operation Setting Procedure Figure 12 2 shows an example of the count operation setting procedure 1 Select the count clock for channel 0 1 or 2 with bits TPSC2 TPSC0 in the timer control register TCR When an external clock is selected set the TCLK pin to input mode with the TCOE b...

Page 355: ...r value Start count Note When an interrupt is generated clear the source flag in the interrupt handler If the interrupt enabled state is set without clearing the flag another interrupt will be generated Figure 12 2 Example of Count Operation Setting Procedure Auto Reload Count Operation Figure 12 3 shows the TCNT auto reload operation TCOR H 00000000 STR0 STR2 UNF TCNT value TCOR value set in TCNT...

Page 356: ...T N 1 N N 1 Figure 12 4 Count Timing when Operating on Internal Clock Operating on external clock For channels 0 to 2 external clock pin TCLK input can be selected as the timer clock by means of the TPSC2 TPSC0 bits in TCR The rising edge falling edge or both edges can be selected as the detected edge of the external clock with the CKEG1 and CKEG0 bits in TCR Figure 12 5 shows the timing for both ...

Page 357: ...imer control register TCR to set an internal clock or the on chip RTC output clock as the timer operating clock 3 Use bits IPCE1 and IPCE0 in TCR to specify use of the input capture function and whether interrupts are to generated when this function is used 4 Use bits CKEG1 and CKEG0 in TCR to specify whether the rising or falling edge of the TCLK signal is to be used to set the timer counter TCNT...

Page 358: ... is used Underflow interrupts are generated on each of the channels and input capture interrupts on channel 2 only An underflow interrupt request is generated for each channel when the UNF bit in TCR is 1 and the interrupt enable bit for the corresponding channel is 1 When the input capture function is used and an input capture request is generated an interrupt is requested if the input capture in...

Page 359: ...ure flag ICPF of the timer control registers TRCR0 to TCR4 can be cleared while the count is in progress When the flags UNF ICPF are cleared while the count is in progress make sure not to change the values of bits other than those being cleared 12 5 2 TCNT Register Reads When performing a TCNT register read processing for synchronization with the timer count operation is performed If a timer coun...

Page 360: ...Rev 6 0 07 02 page 310 of 986 ...

Page 361: ...ich uses an external pin setting Wait state insertion by RDY pin Wait state insertion can be controlled by program Specification of types of memory connectable to each area Output the control signals of memory to each area Automatic wait cycle insertion to prevent data bus collisions in case of consecutive memory accesses to different areas or a read access followed by a write access to the same a...

Page 362: ...uting the number of transfers set in a register Connectable areas 0 5 6 Settable bus widths 64 32 16 8 MPX interface Address data multiplexing Connectable areas 0 to 6 Settable bus widths 64 32 Byte control SRAM interface SRAM interface with byte control Connectable areas 1 4 Settable bus widths 64 32 16 PCMCIA interface Wait state insertion can be controlled by program Bus sizing function for I O...

Page 363: ...l unit Memory control unit Area control unit Wait control unit Interrupt controller BSC Peripheral bus WCR Wait control register BCR Bus control register MCR Memory control register PCR PCMCIA control register Note SH7750R only MCR Module bus RFCR Refresh count register RTCNT Refresh timer count register RTCOR Refresh time constant register RTCSR Refresh timer control status register Figure 13 1 B...

Page 364: ...ce asserted once for a burst transfer For other burst transfers asserted each data cycle Chip select 6 0 CS6 CS0 O Chip select signals that indicate the area being accessed CS5 and CS6 are also used as PCMCIA CE1A and CE1B Read write RD WR O Data bus input output direction designation signal Also used as the DRAM synchronous DRAM PCMCIA interface write designation signal Row address strobe RAS O R...

Page 365: ...n other cases write strobe signal for D23 D16 Data enable 3 WE3 CAS3 DQM3 ICIOWR O When setting synchronous DRAM interface selection signal for D31 D24 When setting DRAM interface CAS signal for D31 D24 When setting PCMCIA interface ICIOWR signal When setting MPX interface high level output In other cases write strobe signal for D31 D24 Data enable 4 WE4 CAS4 DQM4 O When setting synchronous DRAM i...

Page 366: ...r on reset Designates area 0 bus as MPX interface 1 SRAM 0 MPX When setting PCMCIA interface 16 bit I O designation signal Valid only in little endian mode Clock enable CKE O Synchronous DRAM clock enable control signal Bus release request BREQ BSACK I Bus release request signal bus acknowledge signal Bus use permission BACK BSREQ O Bus use permission signal bus request Area 0 bus width PCMCIA car...

Page 367: ...WR2 O Same signal as RD WR This signal is used when the RD WR signal load is heavy Notes 1 MD3 CE2A input output switching is performed by BCR1 A56PCM Output is selected when BCR1 A56PCM 1 2 MD4 CE2B input output switching is performed by BCR1 A56PCM Output is selected when BCR1 A56PCM 1 3 MD5 RAS2 input output switching is performed by BCR1 DRAMTP Output is selected when BCR1 DRAMTP 2 0 101 4 In ...

Page 368: ...FE0A 00F0 H 1E0A 00F0 32 Wait state control register 1 WCR1 R W H 7777 7777 H FF80 0008 H 1F80 0008 32 Wait state control register 2 WCR2 R W H FFFE EFFF H FF80 000C H 1F80 000C 32 Wait state control register 3 WCR3 R W H 0777 7777 H FF80 0010 H 1F80 0010 32 Memory control register MCR R W H 0000 0000 H FF80 0014 H 1F80 0014 32 PCMCIA control register PCR R W H 0000 H FF80 0018 H 1F80 0018 16 Refr...

Page 369: ...to area 2 or 3 signals such as RAS CAS RD WR and DQM are also asserted When the PCMCIA interface is selected for area 5 or 6 CE2A CE2B is asserted in addition to CS5 CS6 for the byte to be accessed H 0000 0000 H 8000 0000 H A000 0000 H C000 0000 H E000 0000 H FFFF FFFF H E400 0000 H 0000 0000 H 0400 0000 H 0800 0000 H 0C00 0000 H 1000 0000 H 1400 0000 H 1800 0000 H 1FFF FFFF H 1C00 0000 Area 0 Are...

Page 370: ... 32 64 2 MPX 32 64 2 Burst ROM 8 16 32 2 64 7 5 H 14000000 H 17FFFFFF 64 Mbytes PCMCIA 8 16 2 4 8 16 32 64 6 bits 32 bytes SRAM 8 16 32 64 2 MPX 32 64 2 Burst ROM 8 16 32 2 64 7 6 H 18000000 H 1BFFFFFF 64 Mbytes PCMCIA 8 16 2 4 8 16 32 64 6 bits 32 bytes 7 5 H 1C000000 H 1FFFFFFF 64 Mbytes Notes 1 Memory bus width specified by external pins 2 Memory bus width specified by register 3 With synchrono...

Page 371: ...ernal pins The relationship between the external pins MD4 and MD3 and the bus width in a power on reset is shown below MD4 MD3 Bus Width 0 0 64 bits 1 8 bits 1 0 16 bits 1 32 bits When SRAM interface or ROM is used in areas 1 to 6 a bus width of 8 16 32 or 64 bits can be selected with bus control register 2 BCR2 When burst ROM is used a bus width of 8 16 32 or 64 bits can be selected When byte con...

Page 372: ...t interface specifications for external memory space areas 5 and 6 The interfaces supported are the IC memory card interface and I O card interface stipulated in JEIDA specifications version 4 2 PCMCIA2 1 External memory space areas 5 and 6 support both the IC memory card interface and the I O card interface The PCMCIA interface is supported only in little endian mode Table 13 4 PCMCIA Interface F...

Page 373: ...dress A11 11 A9 I Address A9 I Address A9 12 A8 I Address A8 I Address A8 13 A13 I Address A13 I Address A13 14 A14 I Address A14 I Address A14 15 WE PGM I Write enable WE PGM I Write enable WE1 16 RDY BSY O Ready busy IREQ O Interrupt request Sensed on port 17 VCC Operating power supply VCC Operating power supply 18 VPP1 Programming power supply VPP1 Programming peripheral power supply 19 A16 I A...

Page 374: ...D12 I O Data D12 39 D13 I O Data D13 I O Data D13 40 D14 I O Data D14 I O Data D14 41 D15 I O Data D15 I O Data D15 42 CE2 I Card enable CE2 I Card enable CE2A or CE2B 43 RFSH I Refresh request RFSH I Refresh request Output from port 44 RFU Reserved IORD I I O read ICIORD 45 RFU Reserved IOWR I I O write ICIOWR 46 A17 I Address A17 I Address A17 47 A18 I Address A18 I Address A18 48 A19 I Address ...

Page 375: ...IT O Wait request RDY 60 RFU Reserved INPACK O Input acknowledge 61 REG I Attribute memory space select REG I Attribute memory space select WE7 62 BVD2 O Battery voltage detection SPKR O Digital speech signal Sensed on port 63 BVD1 O Battery voltage detection STSCHG O Card status change Sensed on port 64 D8 I O Data D8 I O Data D8 65 D9 I O Data D9 I O Data D9 66 D10 I O Data D10 I O Data D10 67 C...

Page 376: ... 31 30 29 28 27 26 25 24 ENDIAN MASTER A0MPX DPUP 2 IPUP OPUP Initial value 0 1 1 0 1 1 0 1 1 0 0 0 0 0 R W R R R R R R R W R W Bit 23 22 21 20 19 18 17 16 A1MBC A4MBC BREQEN PSHR MEMMPX DMABST 2 Initial value 0 0 0 0 0 0 0 0 R W R R R W R W R W R W R W R Bit 15 14 13 12 11 10 9 8 HIZMEM HIZCNT A0BST2 A0BST1 A0BST0 A5BST2 A5BST1 A5BST0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W ...

Page 377: ...ER is a read only bit Bit 30 MASTER Description 0 In a power on reset the master slave setting external pin MD7 is high designating master mode 1 In a power on reset the master slave setting external pin MD7 is low designating slave mode Bit 29 Area 0 Memory Type A0MPX Samples the value of the area 0 memory type specification external pin MD6 in a power on reset by the RESET pin The memory type of...

Page 378: ...ol input pins NMI IRL0 IRL3 BREQ MD6 IOIS16 RDY Initial value 1 Pull up resistor is off for control input pins NMI IRL0 IRL3 BREQ MD6 IOIS16 RDY Bit 24 Control Output Pin Pull Up Resistor Control OPUP Specifies the pull up resistor status for control output pins A 25 0 BS CSn RD WEn RD WR RAS RAS2 CE2A CE2B RD2 RD WR2 when high impedance OPUP is initialized by a power on reset Bit 24 OPUP Descript...

Page 379: ... Description 0 External requests are not accepted Initial value 1 External requests are accepted Bit 18 Partial Sharing Bit PSHR Sets partial sharing mode PSHR is valid only in the case of a master mode startup Bit 18 PSHR Description 0 Master mode Initial value 1 Partial sharing mode Bit 17 Area 1 to 6 MPX Interface Specification MEMMPX Sets the MPX interface when areas 1 to 6 are set as SRAM int...

Page 380: ...state of address and other signals A 25 0 BS CSn RD WR CE2A CE2B in software standby mode Bit 15 HIZMEM Description 0 The A 25 0 BS CSn RD WR CE2A and CE2B signals go to high impedance High Z in standby mode and when the bus is released Initial value 1 The A 25 0 BS CSn RD WR CE2A and CE2B signals are driven in standby mode When the bus is released they go to high impedance Bit 14 High Impedance C...

Page 381: ...M interface Initial value 1 Area 0 is accessed as burst ROM interface 4 consecutive accesses Can be used with 8 16 32 or 64 bit bus width 1 0 Area 0 is accessed as burst ROM interface 8 consecutive accesses Can only be used with 8 16 or 32 bit bus width 1 Area 0 is accessed as burst ROM interface 16 consecutive accesses Can only be used with 8 or 16 bit bus width Do not specify for 32 bit bus widt...

Page 382: ...e 1 Area 5 is accessed as burst ROM interface 4 consecutive accesses Can be used with 8 16 32 or 64 bit bus width 1 0 Area 5 is accessed as burst ROM interface 8 consecutive accesses Can only be used with 8 16 or 32 bit bus width 1 Area 5 is accessed as burst ROM interface 16 consecutive accesses Can only be used with 8 or 16 bit bus width Do not specify for 32 bit bus width 1 0 0 Area 5 is access...

Page 383: ... 1 Area 6 is accessed as burst ROM interface 4 consecutive accesses Can be used with 8 16 32 or 64 bit bus width 1 0 Area 6 is accessed as burst ROM interface 8 consecutive accesses Can only be used with 8 16 or 32 bit bus width 1 Area 6 is accessed as burst ROM interface 16 consecutive accesses Can only be used with 8 or 16 bit bus width Do not specify for 32 bit bus width 1 0 0 Area 6 is accesse...

Page 384: ...rea 3 is DRAM interface 1 Areas 2 and 3 are DRAM interface 2 1 0 Reserved Cannot be set 1 Reserved Cannot be set Note 1 Selection of SRAM interface or MPX interface is determined by the setting of the MEMMPX bit 2 When this mode is selected 16 or 32 bits should be specified as the bus width for areas 2 and 3 In this mode the MD5 pin is designated for output as the RAS2 pin Bit 0 Area 5 and 6 Bus T...

Page 385: ...t name A0SZ1 A0SZ0 A6SZ1 A6SZ0 A5SZ1 A5SZ0 A4SZ1 A4SZ0 Initial value 0 1 0 1 1 1 1 1 1 1 R W R R R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Bit name A3SZ1 A3SZ0 A2SZ1 A2SZ0 A1SZ1 A0SZ0 PORTEN Initial value 1 1 1 1 1 1 0 0 R W R W R W R W R W R W R W R W Note These bits sample the values of the external pins that specify the area 0 bus size Bits 15 and 14 Area 0 Bus Width A0SZ1 A0SZ0 These bits sa...

Page 386: ...2 bits Initial value 1 0 0 Reserved Setting prohibited 1 Bus width is 8 bits 1 0 Bus width is 16 bits 1 Bus width is 32 bits Bit 1 Reserved This bit is always read as 0 and should only be written with 0 Bit 0 Port Function Enable PORTEN Specifies whether pins D51 to D32 are used as a 20 bit port When this function is used a bus width of 8 16 or 32 bits should be set for all areas Bit 0 PORTEN Desc...

Page 387: ...6 5 4 3 2 1 0 Bit name SDBL Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R W Bit 15 A1MPX A4MPX Enable MEMMODE Determines whether or not the selection of either the MPX interface or the SRAM interface is by A1MPX and A4MPX rather than by MEMMPX Bit 15 MEMMODE Description 0 MPX or SRAM interface is selected by MEMMPX Initial value 1 MPX or SRAM interface is selected by A1MPX and A4MPX Bits 14 an...

Page 388: ...ronous input to the pin corresponding to each bit BCR4 is initialized to H 00000000 by a power on reset but is not initialized by a manual reset or in standby mode When asynchronous input is set ASYNCn 1 the sampling timing is one cycle earlier than when synchronous input is set ASYNCn 0 see figure 13 4 The timings shown in this section and section 22 Electrical Characteristics are all for the cas...

Page 389: ...it 7 6 5 4 3 2 1 0 Bit name ASYNC Initial value 0 0 0 0 0 0 0 0 R W R R R R W R W R W R W R W Bits 31 to 5 Reserved These bits are always read as 0 and should only be written with 0 Bits 4 to 0 Asynchronous Input These bits enable asynchronous input to the corresponding pin Bits 4 to 0 ASYNCn Description 0 Input to corresponding pin is synchronous with CKIO Initial value 1 Input to corresponding p...

Page 390: ...s set in the WCR1 register are inserted automatically if there is a possibility of this kind of data bus collision WCR1 is initialized to H 77777777 by a power on reset but is not initialized by a manual reset or in standby mode Bit 31 30 29 28 27 26 25 24 Bit name DMAIW2 DMAIW1 DMAIW0 A6IW2 A6IW1 A6IW0 Initial value 0 1 1 1 0 1 1 1 R W R R W R W R W R R W R W R W Bit 23 22 21 20 19 18 17 16 Bit n...

Page 391: ... a write access on the same device The DMAIW bits are valid only for DMA single address transfer with DMA dual address transfer inter area idle cycles are inserted Bits 4n 2 to 4n Area n 6 to 0 Inter Cycle Idle Specification AnlW2 AnlW0 These bits specify the number of idle cycles between bus cycles to be inserted when switching from external memory space area n n 6 to 0 to another space or from a...

Page 392: ...MAIW2 DMAIW0 to 000 and bits A3IW2 A3IW0 to 000 1 Inserted when device is switched 2 On the MPX interface a WCR1 idle wait may be inserted before an access either read or write to the same area after a write access The specific conditions for idle wait insertion in accesses to the same area are shown below a Synchronous DRAM set to RAS down mode b Synchronous DRAM accessed by on chip DMAC Apart fr...

Page 393: ...set but is not initialized by a manual reset or in standby mode Bit 31 30 29 28 27 26 25 24 Bit name A6W2 A6W1 A6W0 A6B2 A6B1 A6B0 A5W2 A5W1 Initial value 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W Bit 23 22 21 20 19 18 17 16 Bit name A5W0 A5B2 A5B1 A5B0 A4W2 A4W1 A4W0 Initial value 1 1 1 1 1 1 1 0 R W R W R W R W R W R W R W R W R Bit 15 14 13 12 11 10 9 8 Bit name A3W2 A3W1 A3W0 A2W2 A2...

Page 394: ...1 0 2 Enabled 1 3 Enabled 1 0 0 6 Enabled 1 9 Enabled 1 0 12 Enabled 1 15 Initial value Enabled Bits 28 to 26 Area 6 Burst Pitch A6B2 A6B0 These bits specify the number of wait states to be inserted from the second data access onward in a burst transfer with the burst ROM interface selected Description Burst Cycle Excluding First Cycle Bit 28 A6B2 Bit 27 A6B1 Bit 26 A6B0 Wait States Inserted from ...

Page 395: ...1 0 2 Enabled 1 3 Enabled 1 0 0 6 Enabled 1 9 Enabled 1 0 12 Enabled 1 15 Initial value Enabled Bits 22 to 20 Area 5 Burst Pitch A5B2 A5B0 These bits specify the number of wait states to be inserted from the second data access onward in a burst transfer with the burst ROM interface selected Description Burst Cycle Excluding First Cycle Bit 22 A5B2 Bit 21 A5B1 Bit 20 A5B0 Wait States Inserted from ...

Page 396: ...nd 12 Reserved These bits are always read as 0 and should only be written with 0 Bits 15 to 13 Area 3 Wait Control A3W2 A3W0 These bits specify the number of wait states to be inserted for area 3 External wait input is only enabled when SRAM interface or MPX interface is used and is ignored when DRAM or synchronous DRAM is used For details on MPX interface setting see table 13 6 MPX Interface is S...

Page 397: ...Bits 11 to 9 Area 2 Wait Control A2W2 A2W0 These bits specify the number of wait states to be inserted for area 2 External wait input is only enabled when the SRAM interface or MPX interface is used and is ignored when DRAM or synchronous DRAM is used For details on MPX interface setting see table 13 6 MPX Interface is Selected Areas 0 to 6 When SRAM Interface is Set Description Bit 11 A2W2 Bit 10...

Page 398: ...hibited Notes 1 External wait input is always ignored 2 RAS down mode is prohibited Bits 8 to 6 Area 1 Wait Control A1W2 A1W0 These bits specify the number of wait states to be inserted for area 1 For details on MPX interface setting see table 13 6 MPX Interface is Selected Areas 0 to 6 Description Bit 8 A1W2 Bit 7 A1W1 Bit 6 A1W0 Inserted Wait States RDY RDY RDY RDY Pin 0 0 0 0 Ignored 1 1 Enable...

Page 399: ...d 1 0 2 Enabled 1 3 Enabled 1 0 0 6 Enabled 1 9 Enabled 1 0 12 Enabled 1 15 Initial value Enabled Bits 2 to 0 Area 0 Burst Pitch A0B2 A0B0 These bits specify the number of wait states to be inserted afterwards the second data access in a burst transfer with the burst ROM interface selected Description Burst Cycle Excluding First Cycle Bit 2 A0B2 Bit 1 A0B1 Bit 0 A0B0 Wait States Inserted from Seco...

Page 400: ... Selected Areas 0 to 6 Description Inserted Wait States 1st Data AnW2 AnW1 AnW0 Read Write 2nd Data Onward RDY RDY RDY RDY Pin 0 0 0 1 0 0 Enabled 1 1 Enabled 1 0 2 2 Enabled 1 3 3 Enabled 1 0 0 1 0 1 Enabled 1 1 Enabled 1 0 2 2 Enabled 1 3 3 Enabled n 6 to 0 ...

Page 401: ...l reset or in standby mode Bit 31 30 29 28 27 26 25 24 Bit name A6S0 A6H1 A6H0 Initial value 0 0 0 0 0 1 1 1 R W R R R R R R W R W R W Bit 23 22 21 20 19 18 17 16 Bit name A5S0 A5H1 A5H0 A4RDH A4S0 A4H1 A4H0 Initial value 0 1 1 1 0 1 1 1 R W R R W R W R W R W R W R W R W Bit 15 14 13 12 11 10 9 8 Bit name A3S0 A3H1 A3H0 A2S0 A2H1 A2H0 Initial value 0 1 1 1 0 1 1 1 R W R R W R W R W R R W R W R W B...

Page 402: ... 1 Read Strobe Negate Timing AnRDH Setting Only Possible in the SH7750R When reading these bits specify the timing for the negation of read strobe These bits should be cleared to 0 when a byte control SRAM setting is made Bit 4n 3 AnRDH Read Strobe Negate Timing 0 Negation occurs after insertion of the number of hold wait cycles specified by the AnH setting Initial value 1 Negation occurs based on...

Page 403: ... 0 0 0 0 0 R W R W R R W R W R W R R W R W Bit 15 14 13 12 11 10 9 8 Bit name TRWL2 TRWL1 TRWL0 TRAS2 TRAS1 TRAS0 BE SZ1 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Bit name SZ0 AMXEXT AMX2 AMX1 AMX0 RFSH RMODE EDO MODE Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 31 RAS Down RASD Sets RAS down mode When DRAM RAS down mode is used ...

Page 404: ...e at End of Refresh TRC2 TRC0 Synchronous DRAM auto and self refresh both enabled DRAM auto and self refresh both enabled Bit 29 TRC2 Bit 28 TRC1 Bit 27 TRC0 RAS Precharge Interval Immediately after Refresh 0 0 0 0 Initial value 1 3 1 0 6 1 9 1 0 0 12 1 15 1 0 18 1 21 Bits 26 to 24 22 and 18 Reserved These bits are always read as 0 and should only be written with 0 Bit 23 CAS Negation Period TCAS ...

Page 405: ...ce is set these bits set the bank active read write command delay time Description Bit 17 RCD1 Bit 16 RCD0 DRAM Synchronous DRAM 0 0 2 cycles Reserved Setting prohibited 1 3 cycles 2 cycles 1 0 4 cycles 3 cycles 1 5 cycles 4 cycles Note Inhibited in RAS down mode Bits 15 to 13 Write Precharge Delay TRWL2 TRWL0 These bits set the synchronous DRAM write precharge delay time In auto precharge mode th...

Page 406: ... set the bank active command is not issued for a period of TRC TRAS after an auto refresh command is issued Note Bits 29 to 27 RAS precharge interval at end of refresh Bit 12 TRAS2 Bit 11 TRAS1 Bit 10 TRAS0 RAS RAS RAS RAS DRAM Assertion Period Command Interval after Synchronous DRAM Refresh 0 0 0 2 4 TRC Initial value 1 3 5 TRC 1 0 4 6 TRC 1 5 7 TRC 1 0 0 6 8 TRC 1 7 9 TRC 1 0 8 10 TRC 1 9 11 TRC...

Page 407: ...bited Reserved Setting prohibited 1 0 16 bits Reserved Setting prohibited 1 32 bits 32 bits Bits 6 to 3 Address Multiplexing AMXEXT AMX2 AMX0 These bits specify address multiplexing for DRAM and synchronous DRAM The address shift value is different for the DRAM interface and the synchronous DRAM interface For DRAM Interface Description Bit 6 AMXEXT Bit 5 AMX2 Bit 4 AMX1 Bit 3 AMX0 DRAM 0 0 0 0 8 b...

Page 408: ... a 22 1 6 0 64 128M 4M 8 bits 4 8 2 a 26 25 1 1 64 256M 4M 16 bits 4 4 2 a 26 25 1 0 32 128M 4M 8 bits 4 4 3 a 25 24 1 1 32 256M 4M 16 bits 4 2 3 a 25 24 1 7 64 16M 256k 32 bits 2 2 a 21 1 32 16M 256k 32 bits 2 1 a 20 1 Notes 1 a Not an address pin but an external address 2 Can only be set in the SH7750R 3 Can only be set in the SH7750S SH7750R Setting prohibited in the SH7750 4 For details on add...

Page 409: ...d when RFSH 1 Bit 0 EDO Mode EDOMODE Used to specify the data sampling timing for data reads when using EDO mode DRAM interface The setting of this bit does not affect the operation timing of memory other than DRAM Set this bit to 1 only when DRAM is used 13 2 9 PCMCIA Control Register PCR The PCMCIA control register PCR is a 16 bit readable writable register that specifies the OE and WE signal as...

Page 410: ...its to be added to the number of waits specified by WCR2 in a low speed PCMCIA wait cycle The setting of these bits is selected when the PCMCIA interface access TC bit is set to 1 Bit 13 A6PCW1 Bit 12 A6PCW0 Waits Inserted 0 0 0 Initial value 1 15 1 0 30 1 50 Bits 11 to 9 Address OE OE OE OE WE WE WE WE Assertion Delay A5TED2 A5TED0 These bits set the delay time from address output to OE WE assert...

Page 411: ...ess hold delay time from OE WE negation in a write on the connected PCMCIA interface or in an I O card read The setting of these bits is selected when the PCMCIA interface access TC bit is cleared to 0 Bit 5 A5TEH2 Bit 4 A5TEH1 Bit 3 A5TEH0 Waits Inserted 0 0 0 0 Initial value 1 1 1 0 2 1 3 1 0 0 6 1 9 1 0 12 1 15 Bits 2 to 0 OE OE OE OE WE WE WE WE Negation Address Delay A6TEH2 A6TEH0 These bits ...

Page 412: ...5 14 13 12 11 10 9 8 Bit name Initial value R W W W W W W W W W Bit 7 6 5 4 3 2 1 0 Bit name Initial value R W W W W W W W W W Since the address bus not the data bus is used to write to the synchronous DRAM mode register if the value to be set is X and the SDMR register address is Y value X is written to the synchronous DRAM mode register by performing a write to address X Y When the synchronous D...

Page 413: ...32 bits the burst length is 4 and 8 When the bus width is 64 bits the burst length is fixed at 4 When a setting is made in SDMR byte size writes are performed at the following addresses Bus Width Burst Length CAS Latency Area 2 Area 3 32 4 1 2 3 H FF900048 H FF900088 H FF9000C8 H FF940048 H FF940088 H FF9400C8 32 8 1 2 3 H FF90004C H FF90008C H FF9000CC H FF94004C H FF94008C H FF9400CC 64 4 1 2 3 ...

Page 414: ...egister RTCSR is a 16 bit readable writable register that specifies the refresh cycle and whether interrupts are to be generated RTCSR is initialized to H 0000 by a power on reset but is not initialized by a manual reset or in standby mode Bit 15 14 13 12 11 10 9 8 Bit name Initial value 0 0 0 0 0 0 0 0 R W Bit 7 6 5 4 3 2 1 0 Bit name CMF CMIE CKS2 CKS1 CKS0 OVF OVIE LMTS Initial value 0 0 0 0 0 ...

Page 415: ...or suppression of an interrupt request when the CMF flag is set to 1 in RTCSR Do not set this bit to 1 when CAS before RAS refreshing or auto refreshing is used Bit 6 CMIE Description 0 Interrupt requests initiated by CMF are disabled Initial value 1 Interrupt requests initiated by CMF are enabled Bits 5 to 3 Clock Select Bits CKS2 CKS0 These bits select the input clock for RTCNT The base clock is...

Page 416: ...nt limit set by LMTS Note If 1 is written the original value is retained Bit 1 Refresh Count Overflow Interrupt Enable OVIE Controls generation or suppression of an interrupt request when the OVF flag is set to 1 in RTCSR Bit 1 OVIE Description 0 Interrupt requests initiated by OVF are disabled Initial value 1 Interrupt requests initiated by OVF are enabled Bit 0 Refresh Count Overflow Limit Selec...

Page 417: ...value matches the RTCOR register value the CMF bit is set in the RTCSR register and the RTCNT counter is cleared RTCNT is initialized to H 0000 by a power on reset but continues to count when a manual reset is performed In standby mode RTCNT is not initialized and retains its contents Bit 15 14 13 12 11 10 9 8 Bit name Initial value 0 0 0 0 0 0 0 0 R W Bit 7 6 5 4 3 2 1 0 Bit name Initial value 0 ...

Page 418: ...ister and the RTCNT counter is cleared to 0 If the refresh bit RFSH has been set to 1 in the memory control register MCR and CAS before RAS has been selected as the refresh mode a memory refresh cycle is generated when the CMF bit is set RTCOR is initialized to H 0000 by a power on reset but is not initialized and retains its contents in a manual reset and in standby mode Bit 15 14 13 12 11 10 9 8...

Page 419: ...0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W 13 2 15 Notes on Accessing Refresh Control Registers When the refresh timer control status register RTCSR refresh timer counter RTCNT refresh time constant register RTCOR and refresh count register RFCR are written to a special code is added to the data to prevent inadvertent rewriting in the event of program runaway etc The following procedures sh...

Page 420: ... 16 bits for the PCMCIA interface Data alignment is carried out according to the data bus width and endian mode of each device If the data bus width is smaller than the access size a number of bus cycles will be generated automatically until the access size is reached In this case address incrementing is performed automatically according to the bus width as access is performed For example if longw...

Page 421: ...LSB Byte Data 7 to 0 MSB LSB Word Data 15 to 8 Data 7 to 0 MSB LSB Longword Data 31 to 24 Data 23 to 16 Data 15 to 8 Data 7 to 0 MSB LSB Quadword Data 63 to 56 Data 55 to 48 Data 47 to 40 Data 39 to 32 Data 31 to 24 Data 23 to 16 Data 15 to 8 Data 7 to 0 ...

Page 422: ... 1 1 Data 7 0 8n 2 1 Data 7 0 8n 3 1 Data 7 0 8n 4 1 Data 7 0 8n 5 1 Data 7 0 8n 6 1 Data 7 0 8n 7 1 Data 7 0 Word 8n 1 Data 15 8 Data 7 0 8n 2 1 Data 15 8 Data 7 0 8n 4 1 Data 15 8 Data 7 0 8n 6 1 Data 15 8 Data 7 0 Long word 8n 1 Data 31 24 Data 23 16 Data 15 8 Data 7 0 8n 4 1 Data 31 24 Data 23 16 Data 15 8 Data 7 0 Quad word 8n 1 Data 63 56 Data 55 48 Data 47 40 Data 39 32 Data 31 24 Data 23 1...

Page 423: ...CAS3 DQM3 WE2 WE2 WE2 WE2 CAS2 CAS2 CAS2 CAS2 DQM2 WE1 WE1 WE1 WE1 CAS1 CAS1 CAS1 CAS1 DQM1 WE0 WE0 WE0 WE0 CAS0 CAS0 CAS0 CAS0 DQM0 Byte 8n 1 Asserted 8n 1 1 Asserted 8n 2 1 Asserted 8n 3 1 Asserted 8n 4 1 Asserted 8n 5 1 Asserted 8n 6 1 Asserted 8n 7 1 Asserted Word 8n 1 Asserted Asserted 8n 2 1 Asserted Asserted 8n 4 1 Asserted Asserted 8n 6 1 Asserted Asserted 8n 1 Asserted Asserted Asserted A...

Page 424: ...M1 WE0 WE0 WE0 WE0 CAS0 CAS0 CAS0 CAS0 DQM0 Byte 4n 1 Data 7 0 Asserted 4n 1 1 Data 7 0 Asserted 4n 2 1 Data 7 0 Asserted 4n 3 1 Data 7 0 Asserted Word 4n 1 Data 15 8 Data 7 0 Asserted Asserted 4n 2 1 Data 15 8 Data 7 0 Asserted Asserted Long word 4n 1 Data 31 24 Data 23 16 Data 15 8 Data 7 0 Asserted Asserted Asserted Asserted Quad word 8n 1 Data 63 56 Data 55 48 Data 47 40 Data 39 32 Asserted As...

Page 425: ...E1 WE1 WE1 WE1 CAS1 CAS1 CAS1 CAS1 DQM1 WE0 WE0 WE0 WE0 CAS0 CAS0 CAS0 CAS0 DQM0 Byte 2n 1 Data 7 0 Asserted 2n 1 1 Data 7 0 Asserted Word 2n 1 Data 15 8 Data 7 0 Asserted Asserted Long word 4n 1 Data 31 24 Data 23 16 Asserted Asserted 4n 2 2 Data 15 8 Data 7 0 Asserted Asserted Quad word 8n 1 Data 63 56 Data 55 48 Asserted Asserted 8n 2 2 Data 47 40 Data 39 32 Asserted Asserted 8n 4 3 Data 31 24 ...

Page 426: ...E1 CAS1 CAS1 CAS1 CAS1 DQM1 WE0 WE0 WE0 WE0 CAS0 CAS0 CAS0 CAS0 DQM0 Byte n 1 Data 7 0 Asserted Word 2n 1 Data 15 8 Asserted 2n 1 2 Data 7 0 Asserted Long word 4n 1 Data 31 24 Asserted 4n 1 2 Data 23 16 Asserted 4n 2 3 Data 15 8 Asserted 4n 3 4 Data 7 0 Asserted Quad word 8n 1 Data 63 56 Asserted 8n 1 2 Data 55 48 Asserted 8n 2 3 Data 47 40 Asserted 8n 3 4 Data 39 32 Asserted 8n 4 5 Data 31 24 Ass...

Page 427: ...8n 1 1 Data 7 0 8n 2 1 Data 7 0 8n 3 1 Data 7 0 8n 4 1 Data 7 0 8n 5 1 Data 7 0 8n 6 1 Data 7 0 8n 7 1 Data 7 0 Word 8n 1 Data 15 8 Data 7 0 8n 2 1 Data 15 8 Data 7 0 8n 4 1 Data 15 8 Data 7 0 8n 6 1 Data 15 8 Data 7 0 Long word 8n 1 Data 31 24 Data 23 16 Data 15 8 Data 7 0 8n 4 1 Data 31 24 Data 23 16 Data 15 8 Data 7 0 Quad word 8n 1 Data 63 56 Data 55 48 Data 47 40 Data 39 32 Data 31 24 Data 23...

Page 428: ...3 CAS3 DQM3 WE2 WE2 WE2 WE2 CAS2 CAS2 CAS2 CAS2 DQM2 WE1 WE1 WE1 WE1 CAS1 CAS1 CAS1 CAS1 DQM1 WE0 WE0 WE0 WE0 CAS0 CAS0 CAS0 CAS0 DQM0 Byte 8n 1 Asserted 8n 1 1 Asserted 8n 2 1 Asserted 8n 3 1 Asserted 8n 4 1 Asserted 8n 5 1 Asserted 8n 6 1 Asserted 8n 7 1 Asserted Word 8n 1 Asserted Asserted 8n 2 1 Asserted Asserted 8n 4 1 Asserted Asserted 8n 6 1 Asserted Asserted 8n 1 Asserted Asserted Asserted...

Page 429: ...DQM1 WE0 WE0 WE0 WE0 CAS0 CAS0 CAS0 CAS0 DQM0 Byte 4n 1 Data 7 0 Asserted 4n 1 1 Data 7 0 Asserted 4n 2 1 Data 7 0 Asserted 4n 3 1 Data 7 0 Asserted Word 4n 1 Data 15 8 Data 7 0 Asserted Asserted 4n 2 1 Data 15 8 Data 7 0 Asserted Asserted Long word 4n 1 Data 31 24 Data 23 16 Data 15 8 Data 7 0 Asserted Asserted Asserted Asserted Quad word 8n 1 Data 31 24 Data 23 16 Data 15 8 Data 7 0 Asserted Ass...

Page 430: ... WE1 WE1 WE1 WE1 CAS1 CAS1 CAS1 CAS1 DQM1 WE0 WE0 WE0 WE0 CAS0 CAS0 CAS0 CAS0 DQM0 Byte 2n 1 Data 7 0 Asserted 2n 1 1 Data 7 0 Asserted Word 2n 1 Data 15 8 Data 7 0 Asserted Asserted Long word 4n 1 Data 15 8 Data 7 0 Asserted Asserted 4n 2 2 Data 31 24 Data 23 16 Asserted Asserted Quad word 8n 1 Data 15 8 Data 7 0 Asserted Asserted 8n 2 2 Data 31 24 Data 23 16 Asserted Asserted 8n 4 3 Data 47 40 D...

Page 431: ... WE1 CAS1 CAS1 CAS1 CAS1 DQM1 WE0 WE0 WE0 WE0 CAS0 CAS0 CAS0 CAS0 DQM0 Byte n 1 Data 7 0 Asserted Word 2n 1 Data 7 0 Asserted 2n 1 2 Data 15 8 Asserted Long word 4n 1 Data 7 0 Asserted 4n 1 2 Data 15 8 Asserted 4n 2 3 Data 23 16 Asserted 4n 3 4 Data 31 24 Asserted Quad word 8n 1 Data 7 0 Asserted 8n 1 2 Data 15 8 Asserted 8n 2 3 Data 23 16 Asserted 8n 3 4 Data 31 24 Asserted 8n 4 5 Data 39 32 Asse...

Page 432: ...me can be set respectively to 0 or 1 and to 0 to 3 cycles using the A0S0 A0H1 and A0H0 bits in the WCR3 register Area 1 For area 1 external address bits A28 to A26 are 001 SRAM MPX and byte control SRAM can be set to this area A bus width of 8 16 32 or 64 bits can be selected with bits A1SZ1 and A1SZ0 in the BCR2 register When MPX interface is set a bus width of 32 or 64 bits should be selected wi...

Page 433: ...hold times can be set within a range of 0 1 and 0 3 cycles respectively by means of bit A2S0 and bits A2H1 and A2H0 in the WCR3 register When synchronous DRAM interface is set the RAS and CAS signals RD WR signal and byte control signals DQM0 to DQM7 are asserted and address multiplexing is performed RAS CAS and data timing control and address multiplexing control can be set using the MCR register...

Page 434: ...nd address multiplexing control can be set using the MCR register Area 4 For area 4 external address bits A28 to A26 are 100 SRAM MPX and byte control SRAM can be set to this area A bus width of 8 16 32 or 64 bits can be selected with bits A4SZ1 and A4SZ0 in the BCR2 register When MPX interface is set a bus width of 32 or 64 bits should be selected with bits A4SZ1 and A4SZ0 in the BCR2 register Wh...

Page 435: ...RD signal which can be used as OE and the WE1 WE2 WE3 and WE7 signals which can be used as WE ICIORD ICIOWR and REG respectively are asserted As regards the number of bus cycles from 0 to 15 waits can be selected with bits A5W2 to A5W0 in the WCR2 register In addition any number of waits can be inserted in each bus cycle by means of the external wait pin RDY When the burst function is used the num...

Page 436: ...gnal which can be used as OE and the WE1 WE2 WE3 and WE7 signals which can be used as WE ICIORD ICIOWR and REG respectively are asserted As regards the number of bus cycles from 0 to 15 waits can be selected with bits A6W2 to A6W0 in the WCR2 register In addition any number of waits can be inserted in each bus cycle by means of the external wait pin RDY When the burst function is used the number o...

Page 437: ...minimum pitch There is no access size specification when reading The correct access address is output to the address pins A 25 0 but since there is no access size specification 32 bits are always read in the case of a 32 bit device and 16 bits in the case of a 16 bit device When writing only the WE signal for the byte to be written is asserted For details see section 13 3 1 Endian Access Size and ...

Page 438: ...A0 RD D63 D0 read D63 D0 write T2 DACKn SA IO memory DACKn SA IO memory DACKn DA SA Single address DMA DA Dual address DMA Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 6 Basic Timing of SRAM Interface ...

Page 439: ...bit data width SRAM A19 A3 D63 D56 SH7750 Series 128k 8 bit SRAM A16 A0 I O7 I O0 A16 A0 I O7 I O0 A16 A0 I O7 I O0 D55 D48 D47 D40 D39 D32 D31 D24 D23 D16 D15 D8 D7 D0 A16 A0 I O7 I O0 A16 A0 I O7 I O0 A16 A0 I O7 I O0 A16 A0 I O7 I O0 A16 A0 I O7 I O0 Figure 13 7 Example of 64 Bit Data Width SRAM Connection ...

Page 440: ...7 02 page 390 of 986 A16 A0 I O7 I O0 A18 A2 D31 D24 D23 D16 D15 D8 D7 D0 SH7750 Series 128k 8 bit SRAM A16 A0 I O7 I O0 A16 A0 I O7 I O0 A16 A0 I O7 I O0 Figure 13 8 Example of 32 Bit Data Width SRAM Connection ...

Page 441: ...Rev 6 0 07 02 page 391 of 986 A16 A0 I O7 I O0 A17 A1 D15 D8 D7 D0 SH7750 Series 128k 8 bit SRAM A16 A0 I O7 I O0 Figure 13 9 Example of 16 Bit Data Width SRAM Connection ...

Page 442: ...n the SRAM interface can be controlled by the WCR2 settings If the WCR2 wait specification bits corresponding to a particular area are not zero a software wait is inserted in accordance with that specification For details see section 13 2 6 Wait Control Register 2 WCR2 The specified number of Tw cycles are inserted as wait cycles using the SRAM interface wait timing shown in figure 13 11 ...

Page 443: ...T1 CKIO A25 A0 RD D63 D0 read D63 D0 write Tw T2 DACKn SA IO memory DACKn SA IO memory DACKn DA Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 11 SRAM Interface Wait Timing Software Wait Only ...

Page 444: ...ion from the Tw state to the T2 state therefore the RDY signal has no effect if asserted in the T1 cycle or the first Tw cycle The RDY signal is sampled on the rising edge of the clock T1 Tw Twe T2 CKIO A25 A0 RD read D63 D0 read write D63 D0 write DACKn SA IO memory DACKn SA IO memory DACKn DA Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 12 SRAM Interfac...

Page 445: ... 1 Tw Access wait WCR2 AnW 0 to 15 TH1 TH2 Hold wait WCR3 AnH 0 to 3 Note When AnRDH is set to 1 Figure 13 13 SRAM Interface Read Strobe Negate Timing AnS 1 AnW 4 AnH 2 13 3 4 DRAM Interface Direct Connection of DRAM When the memory type bits DRAMTP2 0 in BCR1 are set to 100 area 3 becomes DRAM space when set to 101 area 2 and area 3 become DRAM space The DRAM interface function can then be used t...

Page 446: ...nd RD WR and those for area 3 DRAM connection are RAS CAS0 to CAS3 and RD WR In addition to normal read and write access modes fast page mode is supported for burst access For DRAM connected to areas 2 and 3 EDO mode which enables the DRAM access time to be increased is supported A12 A3 RD D63 D48 SH7750 Series 1M 16 bit DRAM A9 A0 I O15 I O0 D15 D0 A9 A0 I O15 I O0 A9 A0 I O15 I O0 A9 A0 I O15 I ...

Page 447: ...Rev 6 0 07 02 page 397 of 986 A10 A2 RD D31 D16 D15 D0 SH7750 Series 256k 16 bit DRAM A8 A0 I O15 I O0 A8 A0 I O15 I O0 Figure 13 15 Example of DRAM Connection 32 Bit Data Width Area 3 ...

Page 448: ...Rev 6 0 07 02 page 398 of 986 A9 A1 RD D15 D0 SH7750 Series 256k 16 bit DRAM A8 A0 I O15 I O0 A8 A0 I O15 I O0 Area 3 Area 2 Figure 13 16 Example of DRAM Connection 16 Bit Data Width Areas 2 and 3 ...

Page 449: ...put pins subject to address multiplexing are A17 to A1 The address signals output by pins A25 to A18 are undefined Table 13 15 Relationship between AMXEXT and AMX2 0 Bits and Address Multiplexing Setting External Address Pins AMXEXT AMX2 AMX1 AMX0 Number of Column Address Bits Output Timing A1 A13 A14 A15 A16 A17 0 0 0 0 8 bits Column address A1 A13 A14 A15 A16 A17 Row address A9 A21 A22 A23 A24 A...

Page 450: ...pc is the precharge cycle Tr the RAS assert cycle Tc1 the CAS assert cycle and Tc2 the read data latch cycle Tr1 Tr2 Tc1 Tc2 Tpc Row CKIO A25 A0 RD D63 D0 read D63 D0 write DACKn SA IO memory DACKn SA IO memory Column Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 17 Basic DRAM Access Timing ...

Page 451: ...erted by means of the TPC bit in MCR giving from 1 to 7 cycles The number of cycles from RAS assertion to CAS assertion can be set to between 2 and 5 by inserting Trw cycles by means of the RCD bit in MCR Also the number of cycles from CAS assertion to the end of the access can be varied between 1 and 16 according to the setting of A2W2 to A2W0 or A3W2 to A3W0 in WCR2 Tr1 CKIO A25 A0 RD D63 D0 rea...

Page 452: ...or burst access using fast page mode is shown in figure 13 19 If the access size exceeds the set bus width burst access is performed In a 32 byte burst transfer cache fill the first access comprises a longword that includes the data requiring access The remaining accesses are performed on 32 byte boundary data that includes the relevant data In burst transfer cache write back wraparound writing is...

Page 453: ... the EDO mode bit EDOMODE in MCR enables either normal access burst access using fast page mode or EDO mode normal access burst access to be selected for DRAM When EDO mode is set BE must be set to 1 in MCR EDO mode normal access is shown in figure 13 20 and burst access in figure 13 21 CAS Negation Period The CAS negation period can be set to 1 or 2 by means of the TCAS bit in the MCR register Tr...

Page 454: ...select RAS down mode in which RAS remains asserted after the end of an access When RAS down mode is used if the refresh cycle is longer than the maximum DRAM RAS assert time the refresh cycle must be decreased to or below the maximum value of tRAS RAS down mode can only be used when DRAM is connected in area 3 In RAS down mode in the event of an access to an address with a different row address an...

Page 455: ...2 Tc2 Tc1 Tc2 CKIO A25 A0 RD D63 D0 read D63 D0 write DACKn SA IO memory DACKn SA IO memory d4 d3 d2 d1 d4 d3 d2 d1 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 22 1 DRAM Burst Bus Cycle RAS Down Mode Start Fast Page Mode RCD 0 AnW 0 ...

Page 456: ...3 D0 read D63 D0 write DACKn SA IO memory DACKn SA IO memory c0 c1 c2 c3 d0 d0 d1 d2 d3 d1 d2 d3 End of RAS down mode Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 22 2 DRAM Burst Bus Cycle RAS Down Mode Continuation Fast Page Mode RCD 0 AnW 0 ...

Page 457: ...c2 Tc2 Tr1 r c1 c2 c3 c4 Tc1 Tc1 Tce Tc2 CKIO A25 A0 RD D63 D0 read DACKn SA IO memory d4 d3 d2 d1 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 22 3 DRAM Burst Bus Cycle RAS Down Mode Start EDO Mode RCD 0 AnW 0 ...

Page 458: ...c1 c2 c3 c4 Tc1 Tce CKIO A25 A0 RD D63 D0 read DACKn SA IO memory d4 d3 d2 d1 End of RAS down mode Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 22 4 DRAM Burst Bus Cycle RAS Down Mode Continuation EDO Mode RCD 0 AnW 0 ...

Page 459: ...CKS2 CKS0 RTCNT starts counting up from the value at that time The RTCNT value is constantly compared with the RTCOR value and if the two values are the same a refresh request is generated and the BACK pin goes high If the SH7750 Series external bus can be used CAS before RAS refreshing is performed At the same time RTCNT is cleared to zero and the count up is restarted Figure 13 23 shows the oper...

Page 460: ...efresh cycle time for example the HM51W4160AL L version has a refresh cycle of 1024 cycles 128 ms compared with 1024 cycles 16 ms for the normal version With these DRAMs however the same refresh cycle as for the normal version is requested only in the case of refreshing immediately following self refreshing To ensure efficient DRAM refreshing therefore processing is needed to generate an overflow ...

Page 461: ...an be controlled by the HIZCNT bit in BCR1 This enables the DRAM to be kept in the self refreshing state As the DRAM CAS signal is multiplexed with WEn for normal memory SRAM etc access to memory that uses the WEn signals must be disabled during self refreshing Relationship between Refresh Requests and Bus Cycle Requests If a refresh request is generated during execution of a bus cycle execution o...

Page 462: ...On Sequence Regarding use of DRAM after powering on it is requested that a wait time at least 100 µs or 200 µs during which no access can be performed be provided followed by at least the prescribed number usually 8 of dummy CAS before RAS refresh cycles As the bus state controller does not perform any special operations for a power on reset the necessary power on sequence must be carried out by t...

Page 463: ...H7750R for a 32 bit bus see Notes on Changing the Burst Length SH7750R Only in section 13 3 5 Synchronous DRAM Interface The control signals for connection of synchronous DRAM are RAS CAS RD WR CS2 or CS3 DQM0 to DQM7 and CKE All the signals other than CS2 and CS3 are common to all areas and signals other than CKE are valid and latched only when CS2 or CS3 is asserted Synchronous DRAM can therefor...

Page 464: ... 2 bank synchronous DRAM A9 A0 CLK CKE I O15 I O0 DQMU DQML D47 D32 DQM5 DQM4 D31 D16 DQM3 DQM2 D15 D0 DQM1 DQM0 A9 A0 CLK CKE I O15 I O0 DQMU DQML A9 A0 CLK CKE I O15 I O0 DQMU DQML A9 A0 CLK CKE I O15 I O0 DQMU DQML Figure 13 26 Example of 64 Bit Data Width Synchronous DRAM Connection Area 3 ...

Page 465: ...ween the address multiplex specification bits and the bits output at the address pins See Appendix F Synchronous DRAM Address Multiplexing Tables Address pin output at A25 A18 A1 and A0 are undefined When A0 the LSB of the synchronous DRAM address is connected to the SH7750 Series with a 32 bit bus width it makes a longword address specification Connection should therefore be made in this order co...

Page 466: ... Tpc cycle is used to wait for completion of auto precharge based on the READA command inside the synchronous DRAM no new access command can be issued to the same bank during this cycle In the SH7750 Series the number of Tpc cycles is determined by the specification of bits TPC2 TPC0 in MCR and commands are not issued for synchronous DRAM during this interval The example in figure 13 28 shows the ...

Page 467: ...onous DRAM Burst Read In a synchronous DRAM cycle the BS signal is asserted for one cycle at the start of the data transfer cycle corresponding to the READ or READA command The order of access is as follows in a fill operation in the event of a cache miss 64 bit boundary data including the missed data is read first then 16 byte boundary data including the missed data is read in wraparound mode The...

Page 468: ...to Td4 BS is asserted and data latched only in the Td1 cycle Since such empty cycles increase the memory access time and tend to reduce program execution speed and DMA transfer speed it is important both to avoid unnecessary cache through area accesses and to use a data structure that will allow data to be placed at a 32 byte boundary and to be transferred in 32 byte units when carrying out DMA tr...

Page 469: ...efore no command can be issued for the same bank until precharging is completed Consequently in addition to the precharge wait cycle Tpc used in a read access cycle Trwl is also added as a wait interval until precharging is started following the write command Issuance of a new command for synchronous DRAM is postponed during this interval The number of Trwl cycles can be specified by bits TRWL2 TR...

Page 470: ...ous DRAM after completion of the write command and therefore no command can be issued for synchronous DRAM until precharging is completed Consequently in addition to the precharge wait cycle Tpc used in a read access cycle Trwl is also added as a wait interval until precharging is started following the write command Issuance of a new command for synchronous DRAM is postponed during this interval T...

Page 471: ...rw1 Tpc Trw H L c1 Trw1 CKIO Bank Precharge sel Address DQMn RD D63 D0 read CKE DACKn SA IO memory c1 Row Row Row Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 31 Basic Timing for Synchronous DRAM Single Write ...

Page 472: ...tate If there is no guarantee that there will not be a cache hit and another row address will be accessed within the period in which this value is maintained by program execution it is necessary to set auto refresh and set the refresh cycle to no more than the maximum value of tRAS In this way it is possible to observe the restrictions on the maximum active state time for each bank If auto refresh...

Page 473: ...a refresh cycle or before bus release due to bus arbitration c2 c3 c4 Tr Tc1 Tc2 c1 Tc3 Tc4 Td1 Td2 Td4 Trw H L c1 Td3 CKIO Bank Precharge sel Address DQMn RD D63 D0 read CKE DACKn SA IO memory Row Row Row Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 32 Burst Read Timing ...

Page 474: ...c3 Tc4 Td1 c1 Td2 Td3 Td4 Tc2 H L c1 CKIO Bank Precharge sel Address DQMn RD D63 D0 read CKE DACKn SA IO memory Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 33 Burst Read Timing RAS Down Same Row Address ...

Page 475: ...Tc3 Td2 Tpc H L c1 Tc4 Td1 Td3 Td4 CKIO Bank Precharge sel Row Row Row Address DQMn RD D63 D0 read CKE DACKn SA IO memory Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 34 Burst Read Timing RAS Down Different Row Addresses ...

Page 476: ...c2 Tc3 Tc4 Trw1 Trw H L c1 Trw1 CKIO Bank Precharge sel Address DQMn RD D63 D0 read CKE c1 c2 c3 c4 Row Row Row DACKn SA IO memory Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 35 Burst Write Timing ...

Page 477: ...gle address DMA Normal write Note In the case of SA DMA only the Tnop cycle is inserted and the DACKn signal is output as shown by the solid line In a normal write the Tnop cycle is omitted and the DACKn signal is output as shown by the dotted line DACKn shows an example where DMAC CHCRn and AL acknowledge level are 0 Figure 13 36 Burst Write Timing Same Row Address ...

Page 478: ...AC or in the case of consecutive accesses by the DMAC to provide faster access to synchronous DRAM As synchronous DRAM is internally divided into two or four banks after a READ or WRIT command is issued for one bank it is possible to issue a PRE ACTV or other command during the CAS latency cycle or data latch cycle or during the data write cycle and so shorten the access cycle When a read access i...

Page 479: ...llowing a write access the PRE ACTV READ or WRIT command is issued during the data write cycle for the preceding access however in the case of different row addresses in the same bank a PRE command cannot be issued and so in this case the PRE command is issued following the number of Trwl cycles specified by the TRWL bits in MCR after the end of the last data write cycle Figure 13 38 shows a burst...

Page 480: ...Bank Precharge sel Address DQMn RD D63 D0 read CKE a1 a2 a3 a4 b1 b2 c_A H L Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 38 Burst Read Cycle for Different Bank and Row Address Following Preceding Burst Read Cycle ...

Page 481: ...s to satisfy the refresh interval specification for the synchronous DRAM used First make the settings for RTCOR RTCNT and the RMODE and RFSH bits in MCR then make the CKS2 CKS0 setting last of all When the clock is selected by CKS2 CKS0 RTCNT starts counting up from the value at that time The RTCNT value is constantly compared with the RTCOR value and if the two values are the same a refresh reque...

Page 482: ...s Refresh request cleared by start of refresh cycle 000 000 RTCNT cleared to 0 when RTCNT RTCOR Auto refresh cycle Time Refresh request Figure 13 39 Auto Refresh Operation TRr2 TRr3 TRr4 TRr5 Trc TRr1 Trc TRrw Trc CKIO RD DQMn CKE D63 D0 Figure 13 40 Synchronous DRAM Auto Refresh Timing ...

Page 483: ...g is activated from the state in which auto refreshing is set or when exiting standby mode other than through a power on reset auto refreshing is restarted if RFSH is set to 1 and RMODE is cleared to 0 when self refresh mode is cleared If the transition from clearing of self refresh mode to the start of auto refreshing takes time this time should be taken into consideration when setting the initia...

Page 484: ...xecution of a TAS instruction and between read and write cycles when DMAC dual address transfer is executed If a refresh request occurs when the bus has been released by the bus arbiter refresh execution is deferred until the bus is acquired If a match between RTCNT and RTCOR occurs while a refresh is waiting to be executed so that a new refresh request is generated the previous refresh request is...

Page 485: ...0090 H FF940090 2 H FF900110 H FF940110 3 H FF900190 H FF940190 Note SH7750R only The value set in MCR MRSET is used to select whether a precharge all banks command or a mode register setting command is issued The timing for the precharge all banks command is shown in figure 13 42 1 and the timing for the mode register setting command in figure 13 42 2 Before mode register a 200 µs idle time depen...

Page 486: ...T to 1 and performing a write to address H FF900000 X or H FF940000 X Synchronous DRAM mode register setting should be executed once only after power on reset and before synchronous DRAM access and no subsequent changes should be made CKIO Bank Precharge sel Address RD D31 D0 CKE TRp1 TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4 High TMw5 Figure 13 42 1 Synchronous DRAM Mode Write Timing PALL ...

Page 487: ...Rev 6 0 07 02 page 437 of 986 CKIO Bank Precharge sel Address RD D31 D0 CKE TRp1 TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4 High TMw5 Figure 13 42 2 Synchronous DRAM Mode Write Timing Mode Register Set ...

Page 488: ... are accepted on the rising edges of the external command clock CKIO Tpc is the cycle used to wait for the auto precharging which is triggered by the READA command to be completed in the synchronous DRAM During this cycle a new command for accessing the same bank cannot be issued In this LSI the number of Tpc cycles is determined by the setting of the TPC2 to TPC0 bits of MCR and no command that o...

Page 489: ... burst write operation subsequent to the Tr cycle in which ACTV command output takes place a WRIT command is issued during the Tc1 cycle and a WRITA command is issued four cycles later During the write cycle write data is output together with the write command With a write command that includes an auto precharge the precharge is performed on the relevant bank of the synchronous DRAM on completion ...

Page 490: ...ytes of external memory space in area 2 or 3 Either eight 128 Mbit 4 M 8 bit 4 bank DRAMs or four 256 Mbit 4 M 8 bit 4 bank DRAMs can be connected Figure 13 45 shows an example in which four 256 Mbit DRAMs are connected Notes on Usage BCR1 DRAMTP2 DRAMTP0 011 Sets areas 2 and 3 as synchronous DRAM interface spaces MCR SZ 00 Sets the bus width of the synchronous DRAM to 64 bits MCR AMX 6 Selects th...

Page 491: ...s burst ROM to be connected to areas 0 5 and 6 The burst ROM interface provides high speed access to ROM that has a burst access function The timing for burst access to burst ROM is shown in figure 13 46 Two wait cycles are set Basically access is performed in the same way as for SRAM interface but when the first cycle ends only the address is changed before the next access is executed When 8 bit ...

Page 492: ...med on the data at the 32 byte boundary The bus is not released during this period Figure 13 48 shows the timing when a burst ROM setting is made and setup hold is specified in WCR3 T1 TB1 TB2 TB1 TB2 TB1 TB2 T2 CKIO A25 A5 A4 A0 RD D63 D0 read DACKn SA IO memory Notes 1 For a write cycle a basic bus cycle write cycle is performed 2 For DACKn an example is shown where CHCRn AL access level 0 for t...

Page 493: ...w TB1 TB2 Tw T2 TB1 CKIO A25 A5 A4 A0 RD D63 D0 read DACKn SA IO memory Notes 1 For a write cycle a basic bus cycle write cycle is performed 2 For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 47 Burst ROM Wait Access Timing ...

Page 494: ...s being supplied a 3 state buffer must be connected between the SH7750 Series bus interface and the PCMCIA cards As operation in big endian mode is not explicitly stipulated in the JEIDA PCMCIA specifications the SH7750 Series supports only a little endian mode PCMCIA interface In the SH7750 the PCMCIA interface area can only be accessed when the MMU is used The PCMCIA interface memory space can b...

Page 495: ...1 16 bit common memory 1 0 8 bit attribute memory 1 16 bit attribute memory AnPCW1 AnPCW0 specify the number of wait states to be inserted in a low speed bus cycle a value of 0 15 30 or 50 can be set and this value is added to the number of wait states for insertion specified by WCR2 AnTED2 AnTED0 can be set to a value from 0 to 15 enabling the address CS CE2A CE2B and REG setup times with respect...

Page 496: ...valid Upper read data Odd Don t care Write 8 Even Don t care 1 0 0 Invalid Write data Odd Don t care 1 0 1 Invalid Write data 16 Even Don t care First 1 0 0 Invalid Lower write data Even Don t care Second 1 0 1 Invalid Upper write data Odd Don t care 16 Read 8 Even Don t care 1 0 0 Invalid Read data Odd Don t care 0 1 1 Read data Invalid 16 Even Don t care 0 0 0 Upper read data Lower read data Odd...

Page 497: ... data Odd 0 Read 8 Even 1 1 0 0 Invalid Read data Odd 1 First 0 1 1 Ignored Invalid Odd 1 Second 1 0 1 Invalid Read data 16 Even 1 First 0 0 0 Invalid Lower read data Even 1 Second 1 0 1 Invalid Upper read data Odd 1 Write 8 Even 1 1 0 0 Invalid Write data Odd 1 First 0 1 1 Invalid Write data Odd 1 Second 1 0 1 Invalid Write data 16 Even 1 First 0 0 0 Upper write data Lower write data Even 1 Secon...

Page 498: ...D0 CD1 CD2 A25 A0 D15 D0 CD1 CD2 A25 A0 SH7750 Series D15 D0 RD DIR D7 D0 D15 D8 DIR DIR DIR D7 D0 D15 D8 Output Port PC card memory I O PC card memory I O Card detection circuit Card detection circuit Figure 13 49 Example of PCMCIA Interface ...

Page 499: ... PCMCIA IC memory card interface and figure 13 51 shows the PCMCIA memory card interface wait timing CKIO Tpcm1 Tpcm2 A25 A0 RD D15 D0 read D15 D0 write read write DACKn DA Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 50 Basic Timing for PCMCIA Memory Card Interface ...

Page 500: ...0 RD read D15 D0 read D15 D0 write write DACKn DA Notes For DACKn an example is shown where CHCRn AL access level 0 for the DMAC SH7750S SH7750R only Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm2 Tpcm2w Figure 13 51 Wait Timing for PCMCIA Memory Card Interface ...

Page 501: ...it controller Figure 13 52 PCMCIA Space Allocation I O Card Interface Timing Figures 13 53 and 13 54 show the timing for the PCMCIA I O card interface When an I O card interface access is made to a PCMCIA card in little endian mode dynamic sizing of the I O bus width is possible using the IOIS16 pin When a 16 bit bus width is set if the IOIS16 signal is high during a word size I O bus cycle the I ...

Page 502: ...e 452 of 986 CKIO Tpci1 Tpci2 A25 A0 RD read D15 D0 read write D15 D0 write DACKn DA Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 53 Basic Timing for PCMCIA I O Card Interface ...

Page 503: ...O A25 A0 RD read write DACKn DA D15 D0 read D15 D0 write Tpci0 Tpci0w Tpci1 Tpci1w Tpci1w Tpci2 Tpci2w Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 54 Wait Timing for PCMCIA I O Card Interface ...

Page 504: ...ci2 Tpci2w Tpci0 Tpci Tpci2 Tpci1w Tpci2w CKIO A25 A1 A0 RD read write D15 D0 write D15 D0 read DACKn DA Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 55 Dynamic Bus Sizing Timing for PCMCIA I O Card Interface ...

Page 505: ...nimum pitch The FRAME signal is asserted at the rise of Tm1 and negated when the cycle of the last data transfer starts in the data phase Therefore in an external device supporting the MPX interface the address information and access size output in the address phase must be saved in the external device memory and data corresponding to the data phase must be input or output For details of access si...

Page 506: ...n The MPX interface timing is shown below When the MPX interface is used for areas 1 to 6 a bus size of 32 or 64 bits should be specified in BCR2 For wait control waits specified by WCR2 and wait insertion by means of the RDY pin can be used In a read one wait cycle is automatically inserted after address output even if WCR2 is cleared to 0 ...

Page 507: ... of 986 Tm1 CKIO A RD D63 D0 Tmd1w Tmd1 DACKn DA D0 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 57 MPX Interface Timing 1 Single Read Cycle AnW 0 No External Wait Bus Width 64 Bits ...

Page 508: ...86 Tm1 CKIO A RD D63 D0 Tmd1w Tmd1w Tmd1 DACKn DA D0 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 58 MPX Interface Timing 2 Single Read AnW 0 One External Wait Inserted Bus Width 64 Bits ...

Page 509: ...age 459 of 986 Tm1 CKIO A RD D63 D0 Tmd1 DACKn DA D0 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 59 MPX Interface Timing 3 Single Write Cycle AnW 0 No Wait Bus Width 64 Bits ...

Page 510: ...6 Tm1 CKIO A RD D63 D0 Tmd1w Tmd1w Tmd1 DACKn DA D0 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 60 MPX Interface Timing 4 Single Write AnW 1 One External Wait Inserted Bus Width 64 Bits ...

Page 511: ...D0 Tmd1w Tmd1 Tmd2 Tmd3 Tmd4 DACKn DA D1 D2 D3 D0 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 61 MPX Interface Timing 5 Burst Read Cycle AnW 0 No External Wait Bus Width 64 Bits Transfer Data Size 32 Bytes ...

Page 512: ... Tmd1 Tmd2w Tmd2 Tmd3 Tmd4w Tmd4 DACKn DA D3 D1 D2 D0 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 62 MPX Interface Timing 6 Burst Read Cycle AnW 0 External Wait Control Bus Width 64 Bits Transfer Data Size 32 Bytes ...

Page 513: ...63 D0 Tmd1 Tmd2 Tmd3 Tmd4 DACKn DA D0 D1 D2 D3 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 63 MPX Interface Timing 7 Burst Write Cycle AnW 0 No External Wait Bus Width 64 Bits Transfer Data Size 32 Bytes ...

Page 514: ...Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd4w Tmd4 DACKn DA D3 D0 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 64 MPX Interface Timing 8 Burst Write Cycle AnW 1 External Wait Control Bus Width 64 Bits Transfer Data Size 32 Bytes ...

Page 515: ... RD D31 D0 Tmd1w Tmd1 Tmd2 DACKn DA D1 D0 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 65 MPX Interface Timing 1 Burst Read Cycle AnW 0 No External Wait Bus Width 32 Bits Transfer Data Size 64 Bytes ...

Page 516: ...D0 Tmd1w Tmd1w Tmd1 Tmd2 DACKn DA D1 D0 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 66 MPX Interface Timing 2 Burst Read Cycle AnW 0 One External Wait Inserted Bus Width 32 Bits Transfer Data Size 64 Bytes ...

Page 517: ...O A RD D31 D0 Tmd1 Tmd2 DACKn DA D0 D1 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 67 MPX Interface Timing 3 Burst Write Cycle AnW 0 No External Wait Bus Width 32 Bits Transfer Data Size 64 Bytes ...

Page 518: ...D0 Tmd1w Tmd1w Tmd1 Tmd2 DACKn DA D0 D1 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 68 MPX Interface Timing 4 Burst Write Cycle AnW 1 One External Wait Inserted Bus Width 32 Bits Transfer Data Size 64 Bytes ...

Page 519: ... Tmd3 Tmd4 Tmd5 Tmd6 Tmd7 Tmd8 DACKn DA D1 D2 D3 D0 D5 D6 D7 D4 A Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 69 MPX Interface Timing 5 Burst Read Cycle AnW 0 No External Wait Bus Width 32 Bits Transfer Data Size 32 Bytes ...

Page 520: ...1 Tmd2w Tmd2 Tmd3 Tmd7 Tmd8w Tmd8 DACKn DA D6 D7 D1 D2 D0 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 70 MPX Interface Timing 6 Burst Read Cycle AnW 0 External Wait Control Bus Width 32 Bits Transfer Data Size 32 Bytes ...

Page 521: ...Tmd3 Tmd4 Tmd5 Tmd6 Tmd7 Tmd8 DACKn DA D0 D1 D2 D3 D4 D5 D6 D7 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 71 MPX Interface Timing 7 Burst Write Cycle AnW 0 No External Wait Bus Width 32 Bits Transfer Data Size 32 Bytes ...

Page 522: ...w Tmd1 Tmd2w Tmd2 Tmd3 Tmd7 Tmd8w Tmd8 DACKn DA D0 D6 D7 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 72 MPX Interface Timing 8 Burst Write Cycle AnW 1 External Wait Control Bus Width 32 Bits Transfer Data Size 32 Bytes ...

Page 523: ...ions the WEn pin timing is different In a read access only the WE signal for the byte being read is asserted Assertion is synchronized with the fall of the CKIO clock as for the WE signal while negation is synchronized with the rise of the CKIO clock using the same timing as the RD signal In 32 byte transfer such as a cache fill or copy back a total of 32 bytes are transferred consecutively accord...

Page 524: ...age 474 of 986 A18 A3 RD D63 D48 SH7750 Series 64k 16 bit SRAM A15 A0 I O15 I O0 D15 D0 A15 A0 I O15 I O0 A15 A0 I O15 I O0 A15 A0 I O15 I O0 D31 D16 D47 D32 Figure 13 73 Example of 64 Bit Data Width Byte Control SRAM ...

Page 525: ...02 page 475 of 986 T1 T2 CKIO A25 A0 RD D63 D0 read DACKn SA IO memory DACKn DA Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 74 Byte Control SRAM Basic Read Cycle No Wait ...

Page 526: ...6 of 986 T1 Tw T2 CKIO A25 A0 RD D63 D0 read DACKn SA IO memory DACKn DA Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 75 Byte Control SRAM Basic Read Cycle One Internal Wait Cycle ...

Page 527: ... T1 Tw Twe T2 CKIO A25 A0 RD D63 D0 read DACKn SA IO memory DACKn DA Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 76 Byte Control SRAM Basic Read Cycle One Internal Wait One External Wait ...

Page 528: ...tion is not performed If there is originally space between accesses according to the setting of bits AnIW2 AnIW0 n 0 to 6 in WCR1 the number of idle cycles inserted is the specified number of idle cycles minus the number of empty cycles When bus arbitration is performed the bus is released after waits are inserted between cycles In single address mode DMA transfer when data transfer is performed f...

Page 529: ...f 986 T1 A25 A0 RD D31 D0 T2 Twait T1 T2 Twait T1 T2 Area m space read Area m inter access wait specification Area n inter access wait specification Area n space read Area n space write Figure 13 77 Waits between Access Cycles ...

Page 530: ...tead of a slave mode chip In the following description an external device that issues bus requests is also referred to as a slave The SH7750 Series has two internal bus masters the CPU and the DMAC When synchronous DRAM or DRAM is connected and refresh control is performed refresh requests constitute a third bus master In addition to these are bus requests from external devices in master mode If r...

Page 531: ...ased state If the synchronous DRAM interface is set to the RAS down mode the PALL command is issued before a refresh cycle occurs or before the bus is released by bus arbitration As the CPU in the SH7750 Series is connected to cache memory by a dedicated internal bus reading from cache memory can still be carried out when the bus is being used by another bus master inside or outside the SH7750 Ser...

Page 532: ...D63 D0 write A25 A0 RD D63 D0 write Master access Slave access Master access Asserted for at least 2 cycles Negated within 2 cycles HiZ HiZ HiZ HiZ HiZ HiZ Master mode device access Must be asserted for at least 2 cycles Must be negated within 2 cycles Slave mode device access Figure 13 78 Arbitration Sequence ...

Page 533: ...e is as follows First the bus use permission signal is asserted in synchronization with the rising edge of the clock The address bus and data bus go to the high impedance state in synchronization with the next rising edge of the clock after this BACK assertion At the same time the bus control signals BS CSn RAS1 RAS2 WEn RD RD WR RD2 RD WR2 CE2A and CE2B go to the high impedance state These bus co...

Page 534: ...the clock When BSACK assertion is detected the bus control signals and address bus are immediately driven at the negated level The bus cycle is started at the next rising edge of the clock The last signal negated at the end of the access cycle is synchronized with the rising edge of the clock When the bus cycle ends the BSREQ signal is negated and the release of the bus is reported to the master O...

Page 535: ...by the partial sharing master is carried out by referencing the CS2 signal or BSREQ and BSACK signals on the partial sharing master side Permission to use the bus is reported by the BSACK line connected to the partial sharing master but the master may also negate the BSACK signal even while the bus is being used if it needs the bus urgently in order to service a refresh for example Consequently th...

Page 536: ...mode device In a dual processor configuration using direct master slave connection all processing except direct access to memory is handled by the master In a combination of master mode and partial sharing master mode the partial sharing master mode processor performs initialization refreshing and standby control for the areas connected to it with the exception of area 2 while the master performs ...

Page 537: ...s set to 1 operation cannot be guaranteed when the transition is made to standby mode or deep sleep mode Synchronous DRAM Mode Register Setting SH7750 SH7750S Only The following conditions must be satisfied when setting the synchronous DRAM mode register The DMAC must not be activated until synchronous DRAM mode register setting is completed 1 Register setting for the on chip peripheral modules 2 ...

Page 538: ...Rev 6 0 07 02 page 488 of 986 ...

Page 539: ... eight channels SH7750R Physical address space Choice of 8 bit 16 bit 32 bit 64 bit or 32 byte transfer data length Maximum of 16 M 16 777 216 transfers Choice of single or dual address mode Single address mode Either the transfer source or the transfer destination external device is accessed by a DACK signal while the other is accessed by address One data transfer is completed in one bus cycle Du...

Page 540: ...annels i e channels 1 to 3 in the SH7750 or SH7750S and channels 1 to 7 in the SH7750R In the SH7750R request queues can be cleared on a channel by channel basis in DDT mode in either of the following two ways Clearing a request queue by DTR format The request queues of the relevant channel are cleared when it receives DTR SZ 110 DTR ID 00 DTR MD 11 and DTR COUNT 7 4 1 8 Using software to clear th...

Page 541: ...l requests are accepted Channel 2 Single or dual address mode External requests are accepted Channel 3 Single or dual address mode External requests are accepted Channel 4 SH7750R only Single or dual address mode External requests are accepted Channel 5 SH7750R only Single or dual address mode External requests are accepted Channel 6 SH7750R only Single or dual address mode External requests are a...

Page 542: ...nt register CHCRn DMAC channel control register n 0 to 3 On chip peripheral module Peripheral bus Internal bus DMAC module Count control Register control Activation control Request priority control Bus interface 32B data buffer Bus state controller CH0 CH1 CH2 CH3 Request controller DTR command buffer DDT module SAR0 DAR0 DMATCR0 CHCR0 only External bus ID 1 0 D 63 0 DDTMODE DBREQ BAVL Request 4 4...

Page 543: ...Notification to external device of start of execution DMA transfer end notification DACK0 Output Strobe output to external device of DMA transfer request from channel 0 to external device 1 DMA transfer request DREQ1 Input DMA transfer request input from external device to channel 1 DREQ acceptance confirmation DRAK1 Output Acceptance of request for DMA transfer from channel 1 to external device N...

Page 544: ... notification ID 1 0 DRAK1 DACK1 Output Notification of channel number to external device at same time as TDACK output ID 1 DRAK1 ID 0 DACK1 14 1 4 Register Configuration SH7750 SH7750S Table 14 3 summarizes the DMAC registers The DMAC has a total of 17 registers four registers are allocated to each channel and an additional control register is shared by all four channels Table 14 3 DMAC Registers...

Page 545: ...000000 H FFA0002C H 1FA0002C 32 3 DMA source address register 3 SAR3 R W Undefined H FFA00030 H 1FA00030 32 DMA destination address register 3 DAR3 R W Undefined H FFA00034 H 1FA00034 32 DMA transfer count register 3 DMATCR3 R W Undefined H FFA00038 H 1FA00038 32 DMA channel control register 3 CHCR3 R W 1 H 00000000 H FFA0003C H 1FA0003C 32 Com mon DMA operation register DMAOR R W 1 H 00000000 H F...

Page 546: ...e Specify a 16 bit 32 bit 64 bit or 32 byte boundary address when performing a 16 bit 32 bit 64 bit or 32 byte data transfer respectively If a different address is specified an address error will be detected and the DMAC will halt The initial value of these registers after a power on or manual reset is undefined They retain their values in standby mode and deep sleep mode When transfer is performe...

Page 547: ...e initial value of these registers after a power on or manual reset is undefined They retain their values in standby mode and deep sleep mode When transfer is performed from an external device with DACK to memory in DDT mode DTR format 31 0 is set in DAR0 31 0 For details see Data Transfer Request Format in section 14 5 2 Notes 1 When a 16 bit 32 bit 64 bit or 32 byte boundary address is specified...

Page 548: ...fy the transfer count for the corresponding channel byte count word count longword count quadword count or 32 byte count Specifying H 000001 gives a transfer count of 1 while H 000000 gives the maximum setting 16 777 216 16M transfers During DMAC operation the remaining number of transfers is shown Bits 31 24 of these registers are reserved they are always read as 0 and should only be written with...

Page 549: ...re 32 bit readable writable registers that specify the operating mode transfer method etc for each channel Bits 31 28 and 27 24 indicate the source address and destination address respectively these settings are only valid when the transfer involves the CS5 or CS6 space and the relevant space has been specified as a PCMCIA interface space In other cases these bits should be cleared to 0 For detail...

Page 550: ...s Wait Control Select STC Specifies CS5 or CS6 space wait cycle control for access to a PCMCIA interface area This bit selects the wait control register in the BSC that performs area 5 and 6 wait cycle control Bit 28 STC Description 0 C5 space wait cycle selection Initial value Settings of bits A5W2 A5W0 in wait control register 2 WCR2 and bits A5PCW1 A5PCW0 A5TED2 A5TED0 and A5TEH2 A5TEH0 in the ...

Page 551: ... or CS6 space wait cycle control for access to a PCMCIA interface area This bit selects the wait control register in the BSC that performs area 5 and 6 wait cycle control Bit 24 DTC Description 0 C5 space wait cycle selection Initial value Settings of bits A5W2 A5W0 in wait control register 2 WCR2 and bits A5PCW1 A5PCW0 A5TED2 A5TED0 and A5TEH2 A5TEH0 in the PCMCIA control register PCR are selecte...

Page 552: ...xternal device of the acceptance of DREQ is an active high or active low output In normal DMA mode this bit is valid only in CHCR0 and CHCR1 In DDT mode this bit is invalid Bit 18 RL Description 0 DRAK is an active high output Initial value 1 DRAK is an active low output Bit 17 Acknowledge Mode AM In dual address mode selects whether DACK is output in the data read cycle or write cycle In single a...

Page 553: ...2 in 16 bit transfer 4 in 32 bit transfer 8 in 64 bit transfer 32 in 32 byte burst transfer 1 0 Destination address decremented 1 in 8 bit transfer 2 in 16 bit transfer 4 in 32 bit transfer 8 in 64 bit transfer 32 in 32 byte burst transfer 1 Setting prohibited Bits 13 and 12 Source Address Mode 1 and 0 SM1 SM0 These bits specify incrementing decrementing of the DMA transfer source address The spec...

Page 554: ...r request SCRDR1 external address space 2 1 0 SCIF transmit data empty interrupt transfer request external address space SCFTDR2 2 1 SCIF receive data full interrupt transfer request SCFRDR2 external address space 2 1 0 0 TMU channel 2 input capture interrupt external address space external address space 2 1 TMU channel 2 input capture interrupt external address space on chip peripheral module 2 1...

Page 555: ... TS1 Bit 4 TS0 Description 0 0 0 Quadword size 64 bit specification Initial value 1 Byte size 8 bit specification 1 0 Word size 16 bit specification 1 Longword size 32 bit specification 1 0 0 32 byte block transfer specification Bit 3 Reserved This bit is always read as 0 and should only be written with 0 Bit 2 Interrupt Enable IE When this bit is set to 1 an interrupt request DMTE is generated af...

Page 556: ... specified in DMATCR completed Bit 0 DMAC Enable DE Enables operation of the corresponding channel Bit 0 DE Description 0 Operation of corresponding channel is disabled Initial value 1 Operation of corresponding channel is enabled When auto request is specified with RS3 RS0 transfer is begun when this bit is set to 1 In the case of an external request or on chip peripheral module request transfer ...

Page 557: ... clear the flags The COD bit can be written to in the SH7750S only DMAOR is a 32 bit readable writable register that specifies the DMAC transfer mode DMAOR is initialized to H 00000000 by a power on or manual reset They retain their values in standby mode and deep sleep mode Bits 31 to 16 Reserved These bits are always read as 0 and should only be written with 0 Bit 15 On Demand Data Transfer DDT ...

Page 558: ...h level For details see External Request Mode in section 14 3 2 Bit 4 COD Description 0 DREQ acceptance flag cancellation disabled Initial value 1 DREQ acceptance flag cancellation enabled Note When external request mode is used in the SH7750S recommend setting COD to 1 permanently Bit 4 SH7750 Reserved These bits are always read as 0 and should only be written with 0 Bit 3 Reserved This bit is al...

Page 559: ...NMIF after reading NMIF 1 1 NMI input DMA transfer disabled Setting condition When an NMI interrupt is generated Bit 0 DMAC Master Enable DME Enables activation of the entire DMAC When the DME bit and the DE bit of the CHCR register for the corresponding channel are set to 1 that channel is enabled for transfer If this bit is cleared during data transfer transfers on all channels are suspended Eve...

Page 560: ... 2 When a transfer request is issued and transfer has been enabled the DMAC transfers one transfer unit of data determined by the setting of TS2 TS0 In auto request mode the transfer begins automatically when the DE bit and DME bit are set to 1 The DMATCR value is decremented by 1 for each transfer The actual transfer flow depends on the address mode and bus mode 3 When the specified number of tra...

Page 561: ... AE 1 or DE 0 or DME 0 Bus mode transfer request mode detection method Transfer suspended 4 2 3 No No Yes Yes Yes No No No Yes Yes No Yes Notes 1 In auto request mode transfer begins when the NMIF AE and TE bits are all 0 and the DE and DME bits are set to 1 2 level detection external request in burst mode or cycle steal mode 3 edge detection external request in burst mode or auto request mode in ...

Page 562: ...gnal internally When the DE bit in CHCR0 CHCR3 and the DME bit in the DMA operation register DMAOR are set to 1 the transfer begins so long as the TE bit in CHCR0 CHCR3 and the NMIF and AE bits in DMAOR are all 0 External Request Mode In this mode a transfer is performed in response to a transfer request signal DREQ from an external device One of the modes shown in table 14 4 should be chosen acco...

Page 563: ...REQ is input DMA transfer is started 3 An external request DREQ will be ignored if input when CHCR TE 1 DMAOR NMIF 1 or DMAOR AE 1 or during a power on reset or manual reset in deep sleep mode or standby mode or while the DMAC is in the module standby state 4 A previously input external request will be canceled by the occurrence of an NMI interrupt DMAOR NMIF 1 or address error DMAOR AE 1 or by a ...

Page 564: ... transfer request by SCI SCIF transmit data empty interrupt the transfer destination must be the SCI SCIF s transmit data register SCTDR1 SCFTDR2 Table 14 5 Selecting On Chip Peripheral Module Request Mode with RS Bits RS3 RS2 RS1 RS0 DMAC Transfer Request Source DMAC Transfer Request Signal Transfer Source Transfer Destination Bus Mode 1 0 0 0 SCI transmitter SCTDR1 SCI transmit data empty transf...

Page 565: ...is occurs every transfer in cycle steal mode and in the last transfer in burst mode 14 3 3 Channel Priorities If the DMAC receives simultaneous transfer requests on two or more channels it selects a channel according to a predetermined priority system either in a fixed mode or round robin mode The mode is selected with priority bits PR1 and PR0 in the DMA operation register DMAOR Fixed Mode In thi...

Page 566: ...is a transfer request for channel 1 only immediately afterward channel 1 is given the lowest priority and the priorities of channels 3 and 0 are simultaneously shifted down Transfer on channel 3 Initial priority order Priority order after transfer No change in priority order CH0 CH1 CH2 CH3 CH3 CH0 CH1 CH2 CH2 CH3 CH0 CH1 CH0 CH1 CH2 CH3 CH0 CH1 CH2 CH3 CH2 CH3 CH0 CH1 When channel 1 is given the ...

Page 567: ...transfer standby 6 At the end of the channel 1 transfer channel 1 shifts to the lowest priority level 7 The channel 3 transfer is started 8 At the end of the channel 3 transfer the channel 3 and channel 2 priority levels are lowered giving channel 3 the lowest priority 3 1 3 3 Transfer request Channel waiting DMAC operation Channel priority order 1 Issued for channels 0 and 3 3 Issued for channel ...

Page 568: ...e bus mode which can be either burst mode or cycle steal mode Table 14 6 Supported DMA Transfers Transfer Destination Transfer Source External Device with DACK External Memory Memory Mapped External Device On Chip Peripheral Module External device with DACK Not available Single address mode Single address mode Not available External memory Single address mode Dual address mode Dual address mode Du...

Page 569: ... DACK in which the external device outputs data to the data bus and that data is written to external memory in the same bus cycle DMAC DACK External memory External device with DACK SH7750 Series External address bus Data flow External data bus Figure 14 5 Data Flow in Single Address Mode Two types of transfer are possible in single address mode 1 transfer between an external device with DACK and ...

Page 570: ...n D63 D0 RD DACK Figure 14 6 DMA Transfer Timing in Single Address Mode Dual Address Mode Dual address mode is used to access both the transfer source and the transfer destination by address The transfer source and destination can be accessed by either on chip peripheral module or external address Even if the operand cache is used in RAM mode the RAM cannot be set as the transfer source or transfe...

Page 571: ...same as that of CSn in a read or write cycle specified by the CHCRn AM bit Data buffer Address bus Data bus Address bus Data bus Memory Transfer source module Transfer destination module Memory Transfer source module Transfer destination module SAR DAR Data buffer SAR DAR Taking the SAR value as the address data is read from the transfer source module and stored temporarily in the data buffer in t...

Page 572: ...eleases the bus to the CPU at the end of each transfer unit 8 bit 16 bit 32 bit 64 bit or 32 byte transfer When the next transfer request is issued the DMAC reacquires the bus from the CPU and carries out another transfer unit transfer At the end of this transfer the bus is again given to the CPU This is repeated until the transfer end condition is satisfied Cycle steal mode can be used with all c...

Page 573: ...e DMAC transfer request that has already been accepted even if the transfer end condition has not been satisfied Figure 14 10 shows an example of DMA transfer timing in burst mode The transfer conditions in this example are single address mode and DREQ level detection CHCRn DS 0 CHCRn TM 1 CPU DMAC DMAC DMAC DMAC DMAC DMAC CPU CPU CPU Bus cycle Figure 14 10 Example of DMA Transfer in Burst Mode No...

Page 574: ... steal External External request Internal Auto request or on chip peripheral module request Notes 1 External request auto request or on chip peripheral module request TMU input capture interrupt request possible In the case of an on chip peripheral module request it is not possible to specify external memory data transfer with the SCI SCIF as the transfer request source 2 External request auto req...

Page 575: ... DRAM Single 0 1 5 Synchronous DRAM SRAM type MPX PCMCIA Dual 0 1 6 SRAM type MPX PCMCIA Synchronous DRAM Dual 0 1 7 SRAM type DRAM PCMCIA MPX SRAM type MPX PCMCIA Dual 0 1 8 SRAM type MPX PCMCIA SRAM type DRAM PCMCIA MPX Dual 0 1 DACK output setting in dual address mode transfer SRAM type in the table indicates an SRAM byte control SRAM or burst ROM setting Notes 1 Memory interfaces on which tran...

Page 576: ...r MPX interface 1 In SH7750 the bus width must be 64 bits 2 DACK output setting in dual address mode transfer Bus Mode and Channel Priority Order When for example channel 1 is transferring data in burst mode and a transfer request is issued to channel 0 which has a higher priority the channel 0 transfer is started immediately If fixed mode has been set for the priority levels CH0 CH1 transfer on c...

Page 577: ... of CKIO clock pulses When DREQ input is detected a DMAC bus cycle is generated and DMA transfer executed after four CKIO cycles at the earliest The second and subsequent DREQ sampling operations are performed one cycle after the start of the first DMAC transfer bus cycle in the case of single address mode DRAK is output for one cycle only once each time DREQ is detected regardless of the transfer...

Page 578: ...address mode and level detection is virtually the same as for cycle steal mode For example in figure 14 14 DMAC transfer begins at the earliest four CKIO cycles after the first sampling operation The second sampling operation is performed one cycle after the start of the first DMAC transfer write cycle In the case of dual address mode transfer initiated by an external request the DACK signal can b...

Page 579: ...e and edge detection DREQ sampling is performed only in the first cycle For example in the case shown in figure 14 21 DMAC transfer begins at the earliest five cycles after the first sampling operation DMAC transfer then continues until the end of the number of data transfers set in DMATCR DREQ is not sampled during this time and therefore DRAK is output in the first cycle only In single address m...

Page 580: ...ce address Destination address Bus locked Destination address CPU CPU DMAC CPU DMAC DRAK0 level detection DACK0 Bus cycle A 25 0 CKIO D 63 0 sampling and determination of channel priority Figure 14 12 Dual Address Mode Cycle Steal Mode External Bus External Bus DREQ DREQ DREQ DREQ Level Detection DACK Read Cycle ...

Page 581: ...cked Source address Source address Destination address Bus locked Destination address CPU DMAC CPU DMAC CPU DMAC DRAK0 edge detection DACK0 Bus cycle A 25 0 CKIO D 63 0 sampling and determination of channel priority Figure 14 13 Dual Address Mode Cycle Steal Mode External Bus External Bus DREQ DREQ DREQ DREQ Edge Detection DACK Read Cycle ...

Page 582: ...ource address Destination address Bus locked Destination address CPU DMAC 2 CPU DMAC 1 DRAK0 level detection DACK0 Bus cycle A 25 0 CKIO D 63 0 sampling and determination of channel priority Figure 14 14 Dual Address Mode Burst Mode External Bus External Bus DREQ DREQ DREQ DREQ Level Detection DACK Read Cycle ...

Page 583: ...stination address Bus locked Destination address CPU DMAC 2 CPU DMAC 1 TE bit transfer end DRAK0 edge detection DACK0 Bus cycle A 25 0 CKIO D 63 0 sampling and determination of channel priority Figure 14 15 Dual Address Mode Burst Mode External Bus External Bus DREQ DREQ DREQ DREQ Edge Detection DACK Read Cycle ...

Page 584: ...rce address On chip peripheral data bus Read Read Read D 63 0 Write Write Write Source address Source address A 25 0 Destination address Destination address Destination address CPU CPU DMAC CPU DMAC CPU DMAC Figure 14 16 Dual Address Mode Cycle Steal Mode On Chip SCI Level Detection External Bus ...

Page 585: ...urce address Source address A 25 0 Destination address Destination address Destination address CPU DMAC CPU DMAC CPU DMAC T1 T2 T1 T2 T1 T2 On chip peripheral address bus On chip peripheral data bus B cyc P cyc 1 1 Figure 14 17 Dual Address Mode Cycle Steal Mode External Bus On Chip SCI Level Detection ...

Page 586: ...address 2nd acceptance Source address 3rd acceptance Source address 4th acceptance Source address DRAK0 level detection DACK0 Bus cycle A 25 0 CKIO D 63 0 sampling and determination of channel priority Figure 14 18 Single Address Mode Cycle Steal Mode External Bus External Bus DREQ DREQ DREQ DREQ Level Detection ...

Page 587: ... 2nd acceptance Source address Source address CPU CPU DMAC CPU DMAC CPU DMAC DRAK0 edge detection DACK0 Bus cycle A 25 0 CKIO D 63 0 sampling and determination of channel priority Figure 14 19 Single Address Mode Cycle Steal Mode External Bus External Bus DREQ DREQ DREQ DREQ Edge Detection ...

Page 588: ...ce 2nd acceptance Source address Source address Source address CPU DMAC 4 DMAC 2 DMAC 3 CPU DMAC 1 sampling and determination of channel priority DRAK0 level detection DACK0 Bus cycle A 25 0 CKIO D 63 0 Figure 14 20 Single Address Mode Burst Mode External Bus External Bus DREQ DREQ DREQ DREQ Level Detection ...

Page 589: ...ptance Source address Source address Source address CPU DMAC 2 DMAC 4 DMAC 3 CPU DMAC 1 DRAK0 edge detection DACK0 Bus cycle A 25 0 CKIO D 63 0 sampling and determination of channel priority Figure 14 21 Single Address Mode Burst Mode External Bus External Bus DREQ DREQ DREQ DREQ Edge Detection ...

Page 590: ...bus cycle Asserted 2 cycles before start of bus cycle Asserted 2 cycles before start of bus cycle 2nd acceptance 3rd acceptance DMAC 1 DMAC 2 DMAC 3 Destination address Destination address Destination address D1 D2 D4 D1 D2 D3 D4 D3 D3 Figure 14 22 Single Address Mode Burst Mode External Bus External Bus DREQ DREQ DREQ DREQ Level Detection 32 Byte Block Transfer Bus Width 64 Bits SDRAM Row Hit Wri...

Page 591: ...tivates the DMAC but the timing of stop request DE 0 in CHCR DME 0 in DMAOR sampling is the same as the transfer request sampling timing shown in 4 and 5 under Operation in section 14 3 5 Therefore a transfer request is regarded as having been issued until a stop request is detected and the corresponding processing is executed before the DMAC stops 3 Burst Mode Level Detection External Request The...

Page 592: ...ly when either of the following conditions is satisfied The address error bit AE or NMI flag NMIF in the DMA operation register DMAOR is set to 1 The DMA master enable bit DME in DMAOR is cleared to 0 1 End of transfer when AE 1 in DMAOR If the AE bit in DMAOR is set to 1 due to an address error DMA transfer is suspended on all channels in accordance with the conditions in 1 2 3 and 4 in section 1...

Page 593: ...tance of external requests is suspended while NMIF is set to 1 so a DMA transfer request must be reissued when resuming transfer Acceptance of internal requests is also suspended so when resuming transfer the DMA transfer request enable bit for the relevant on chip peripheral module must be cleared to 0 before the new setting is made 3 End of transfer when DME 0 in DMAOR If the DME bit in DMAOR is...

Page 594: ...ansfer between External Memory and an External Device with DACK and Corresponding Register Settings Transfer Conditions Register Set Value Transfer source external memory SAR1 H 0C000000 Transfer source external device with DACK DAR1 Accessed by DACK Number of transfers 32 DMATCR1 H 00000020 Transfer source address decremented CHCR1 H 000022A5 Transfer destination address setting invalid Transfer ...

Page 595: ... 1 0 ddtmode Data buffer Address bus ddtmode tdack id 1 0 Data bus Request controller FIFO or memory Figure 14 23 On Demand Transfer Mode Block Diagram For channels 0 to 3 after making the settings for normal DMA transfer using the CPU a transfer request can be issued from an external device using the DBREQ BAVL TR TDACK ID 1 0 and D 63 0 DTR signals handshake protocol using the data bus A transfe...

Page 596: ...tial settings have been made in the DMAC channel 0 control register by means of normal data transfer mode channel 0 in the SH7750 or after the initial settings have been made in the DMAC channel 0 control register from the CPU or by means of normal data transfer mode channel 0 in the SH7750S the DDT module asserts a data transfer request for the DMAC by setting DTR format ID 00 MD 00 and SZ 101 or...

Page 597: ...ertion of BAVL means that the data bus will be released two cycles later The SH 4 does not switch the data pins to output status for a total of three cycles the cycle in which the data bus is released and the cycles preceding and following it TR TR TR TR Transfer request signal Assertion of TR has the following different meanings In normal data transfer mode channel 0 TR is asserted and at the sam...

Page 598: ...r destination address are specified A specification in bits 47 32 is invalid In the SH7750 only single address mode can be set in normal data transfer mode channel 0 With the DTR format DS 0 MD 10 11 1 MD 01 RL 0 AL 0 DM 1 0 01 SM 1 0 01 RS 3 0 0010 R W 0 0011 R W 1 TM 0 MD 11 1 MD 01 10 TS 2 0 SZ and IE 0 settings are made in DMA channel control register 0 COUNT is set in transfer count register ...

Page 599: ...nsfer count 1 to 255 00000000 Maximum number of transfers 16M Bits 47 to 32 Reserved Bits 31 to 0 Address ADDRESS31 ADDRESS0 R W 0 Transfer source address specification R W 1 Transfer destination address specification Notes 1 Only the ID field is valid for channels 1 to 3 2 To start DMA transfer by means of demand data transfer on channel 0 the initial value of MD in the DTR format must be 01 10 o...

Page 600: ...requests are accepted between DTR format acceptance and the end of the data transfer On channels 1 to 3 output a transfer request from an external device by means of the DTR format ID 01 10 or 11 after making DMAC control register settings in the same way as in normal DMA mode Each of channels 1 to 3 has a request queue that can accept up to four transfer requests When a request queue is full the ...

Page 601: ...CASD2 tRWD DMAC Channel tIDD tIDD tBSD DTR1CKIO cycle 10nsF100MHz tDBQS 2CKIO cycle tDTRS 18nsF100MHz tTRH tTRS tBAVD CKIO BANK Precharge sel Address DQMn ID1 ID0 D63 D0 READ n RD tTDAD tTDAD c1 c2 c3 c4 tDBQH tBAVD tRASD tBSD Figure 14 26 Single Address Mode Synchronous DRAM External Device Longword Transfer SDRAM auto precharge Read bus cycle burst RCD 1 0 01 CAS latency 3 TPC 2 0 001 ...

Page 602: ...annel tIDD tBSD DTR 1CKIO cycle 10ns 100MHz tDBQS 2CKIO cycle tDTRS 18ns F100MHz tTRH tTRS tBAVD tRASD tRASD tTDAD tTDAD tRWD tRWD tDBQH tBAVD tBSD tIDD tWDD c1 c2 c3 c4 CKIO BANK Precharge sel Address DQMn ID1 ID0 D63 D0 READ RD Figure 14 27 Single Address Mode External Device Synchronous DRAM Longword Transfer SDRAM auto precharge Write bus cycle burst RCD 1 0 01 TRWL 2 0 101 TPC 2 0 001 ...

Page 603: ...1 ID0 D63 D0 READ RD tAD tCSD tAD tCSD Row Row Row tAD c1 H L tRASD tDQMD tCASD2 tCASD2 tRDS tBSD tBSD c1 c2 c4 c3 tDQMD tRDH DMAC Channel tTDAD tTRS tTRH tBAVD 2CKIO cycles tDTRS 18ns 100MHz DTR 1CKIO cycle 10ns 100MHz tDTRS tDTRH tDBQH tBAVD tRASD tTDAD DMAC Channel Figure 14 28 Dual Address Mode Synchronous DRAM SRAM Longword Transfer ...

Page 604: ...ngle Address Mode Burst Mode External Bus External Device 32 Byte Block Transfer Channel 0 On Demand Data Transfer RA CA WT BA D0 D1 D2 D3 D5 D4 DTR CLK ID1 ID0 RAS CAS WE D63 D0 A25 A0 Figure 14 30 Single Address Mode Burst Mode External Device External Bus 32 Byte Block Transfer Channel 0 On Demand Data Transfer ...

Page 605: ...ge 555 of 986 RA CA CA CA D1 D0 DTR BA RD RD RD 00 00 CLK ID1 ID0 RAS CAS WE D63 D0 A25 A0 DQMn Figure 14 31 Single Address Mode Burst Mode External Bus External Device 32 Bit Transfer Channel 0 On Demand Data Transfer ...

Page 606: ... 02 page 556 of 986 RA CA CA D1 D0 DTR BA WT WT CLK ID1 ID0 RAS CAS WE D63 D0 A25 A0 DQMn Figure 14 32 Single Address Mode Burst Mode External Device External Bus 32 Bit Transfer Channel 0 On Demand Data Transfer ...

Page 607: ...57 of 986 CA CA D0 D1 DTR MD 00 D0 D1 D2 D3 WT WT DTR MD 10 or 11 Start of data transfer Next transfer request CLK ID1 ID0 D63 D0 A25 A0 CMD Figure 14 33 Handshake Protocol Using Data Bus Channel 0 On Demand Data Transfer ...

Page 608: ... of 986 CA CA D0 D1 D2 D3 D0 D1 D2 D3 WT WT MD 10 or 11 Start of data transfer Next transfer request CLK ID1 ID0 DTR D63 D0 A25 A0 CMD Figure 14 34 Handshake Protocol without Use of Data Bus Channel 0 On Demand Data Transfer ...

Page 609: ... RAS CAS WE D0 RA CA D1 D2 D3 BA RD Figure 14 35 Read from Synchronous DRAM Precharge Bank CLK A25 A0 D63 D0 RAS CAS WE RA CA D0 D1 D2 D3 PCH BA RD Transfer requests can be accepted Figure 14 36 Read from Synchronous DRAM Non Precharge Bank Row Miss ...

Page 610: ...age 560 of 986 CLK A25 A0 D63 D0 RAS CAS WE CA RD D0 D1 D2 D3 Figure 14 37 Read from Synchronous DRAM Row Hit CLK A25 A0 D63 D0 RAS CAS WE RA CA BA WT D0 D1 D2 D3 Figure 14 38 Write to Synchronous DRAM Precharge Bank ...

Page 611: ... D63 D0 RAS CAS WE RA CA D0 D1 D2 D3 PCH BA WT Transfer requests can be accepted Figure 14 39 Write to Synchronous DRAM Non Precharge Bank Row Miss CLK A25 A0 D63 D0 RAS CAS WE D0 CA D1 D2 D3 WT Figure 14 40 Write to Synchronous DRAM Row Hit ...

Page 612: ...02 page 562 of 986 00 D0 D1 D2 RA CA RD BA DTR CLK ID1 ID0 RAS CAS WE D63 D0 A25 A0 Figure 14 41 Single Address Mode Burst Mode External Bus External Device 32 Byte Block Transfer Channel 0 On Demand Data Transfer ...

Page 613: ...DT 0 Normal DMA mode 1 On demand data transfer mode Figure 14 42 DDT Mode Setting DTR MD 01 CA CA D0 D1 D2 D3 D0 D1 D2 D3 D1 D2 D3 WT WT CLK ID1 ID0 CMD D63 D0 A25 A0 Start of data transfer No DMA request sampling Figure 14 43 Single Address Mode Burst Mode Edge Detection External Device External Bus Data Transfer ...

Page 614: ...D0 A25 A0 Figure 14 44 Single Address Mode Burst Mode Level Detection External Bus External Device Data Transfer CA CA CA RD RD RD DTR D0 D3 D2 CLK ID1 ID0 DQMn D63 D0 A25 A0 CMD Idle cycle Idle cycle Idle cycle MD 01 Figure 14 45 Single Address Mode Burst Mode Edge Detection Byte Word Longword Quadword External Bus External Device Data Transfer ...

Page 615: ...A CA CA WT DTR D0 D3 D1 CLK ID1 ID0 DQMn D63 D0 A25 A0 CMD Idle cycle MD 01 Idle cycle Idle cycle WT WT Figure 14 46 Single Address Mode Burst Mode Edge Detection Byte Word Longword Quadword External Device External Bus Data Transfer ...

Page 616: ...566 of 986 DTR ID 1 2 or 3 RA CA BA RD D0 D1 D2 D3 CLK ID1 ID0 RAS CAS WE D63 D0 A25 A0 01 or 10 or 11 Figure 14 47 Single Address Mode Burst Mode 32 Byte Block Transfer DMA Transfer Request to Channels 1 3 Using Data Bus ...

Page 617: ...6 D7 CLK ID1 ID0 RAS CAS WE D63 D0 A25 A0 No DTR cycle so requests can be made at any time Figure 14 48 Single Address Mode Burst Mode 32 Byte Block Transfer External Bus External Device Data Transfer Direct Data Transfer Request to Channel 2 without Using Data Bus ...

Page 618: ... Handshaking is necessary to send additional requests Must be ignored no request transmitted CA CA RA BA RD NOP RD CA D1 D2 D3 D0 D1 D2 D3 D1 D2 RD D0 D0 No more requests 2nd 1st Figure 14 49 Single Address Mode Burst Mode External Bus External Device Data Transfer Direct Data Transfer Request to Channel 2 ...

Page 619: ...queued Handshaking is necessary to send additional requests CA CA RA CA CA D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 BA WT WT WT WT Must be ignored no request transmitted 2nd 1st Figure 14 50 Single Address Mode Burst Mode External Device External Bus Data Transfer Direct Data Transfer Request to Channel 2 ...

Page 620: ... D1 D2 D3 D0 D1 D2 RD RD RD RD Four requests can be queued Handshaking is necessary to send additional requests Must be ignored no request transmitted 2nd 1st Figure 14 51 Single Address Mode Burst Mode External Bus External Device Data Transfer Active Bank Address Direct Data Transfer Request to Channel 2 ...

Page 621: ...1 In this case only single address mode can be set for channel 0 2 Normal data transfer mode channels 1 to 3 If a setting of DTR ID 01 10 or 11 is made DTR MD will be ignored 3 Handshake protocol using the data bus valid on channel 0 only a The handshake protocol using the data bus can be executed only on channel 0 Set DTR ID 00 DTR MD 00 DTR SZ 101 or 110 Operation is not guaranteed if settings o...

Page 622: ...s ended and CHCR0 TE 1 the DMAC will freeze Before issuing a DMA transfer request the TE flag must be cleared by writing CHCR0 TE 0 after reading CHCR0 TE 1 5 Direct data transfer mode valid on channel 2 only a If a DMA transfer request for channel 2 is input by simultaneous assertion of DBREQ and TR during DMA transfer execution with the handshake protocol without use of the data bus it will be a...

Page 623: ...between the number of DBREQ and BAVL assertions b The BAVL assertion period due to DBREQ assertion is one cycle If a row address miss occurs in a read or write in the non precharged bank during synchronous DRAM access BAVL is asserted for a number of cycles in accordance with the RAS precharge interval set in BSC MCR TCP c It takes one cycle for DBREQ to be accepted by the DMAC after being asserte...

Page 624: ...0 ID 1 0 D 63 0 DBREQ SARn DARn DMATCRn CHCRn DMAOR Bus interface Peripheral bus Internal bus DMAC module Count control Registr control Activation control Request priority control 32B data buffer Bus state controller On chip peripheral module External address on chip peripheral module address TMU SCI SCIF DACK0 DACK1 DRAK0 DRAK1 DMAORn SARn DARn DMATCRn CHCRn n 0 to 7 DMAC operation register DMAC ...

Page 625: ... device Notification to external device of start of execution DMA transfer end notification DACK0 Output Strobe output to external device of DMA transfer request from channel 0 to external device 1 DMA transfer request DREQ1 Input DMA transfer request input from external device to channel 1 DREQ acceptance confirmation DRAK1 Output Acceptance of request for DMA transfer from channel 1 to external ...

Page 626: ...ltaneously Direct request to channel 2 DMAC strobe TDACK DACK0 Output Reply strobe signal for external device from DMAC Channel number notification ID 1 0 DRAK1 DACK1 Output Notification of channel number to external device at same time as TDACK output ID 1 DRAK1 ID 0 DACK1 Requests for DMA transfer from external devices are normally accepted only on channel 0 DREQ0 and channel 1 DREQ1 In DDT mode...

Page 627: ...ount register 1 DMATCR1 R W Undefined H FFA00018 H 1FA00018 32 1 DMA channel control register 1 CHCR1 R W 1 H 00000000 H FFA0001C H 1FA0001C 32 DMA source address register 2 SAR2 R W Undefined H FFA00020 H 1FA00020 32 DMA destination address register 2 DAR2 R W Undefined H FFA00024 H 1FA00024 32 DMA transfer count register 2 DMATCR2 R W Undefined H FFA00028 H 1FA00028 32 2 DMA channel control regi...

Page 628: ...ess register 6 SAR6 R W Undefined H FFA00070 H 1FA00070 32 DMA destination address register 6 DAR6 R W Undefined H FFA00074 H 1FA00074 32 DMA transfer count register 6 DMATCR6 R W Undefined H FFA00078 H 1FA00078 32 6 DMA channel control register 6 CHCR6 R W 1 H 00000000 H FFA0007C H 1FA0007C 32 DMA source address register 7 SAR7 R W Undefined H FFA00080 H 1FA00080 32 DMA destination address regist...

Page 629: ...re the same as on the SH7750 or SH7750S For more information see section 14 2 1 DMA Source Address Registers 0 3 SAR0 SAR3 14 7 2 DMA Destination Address Registers 0 7 DAR0 DAR7 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value R W R W R W R W R W R W R W R W ...

Page 630: ...Registers 0 7 CHCR0 CHCR7 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SSA2 SSA1 SSA0 STC DSA2DSA1DSA0 DTC DS RL AM AL Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R R R R R W R W R W R W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 TM TS2 TS1 TS0 QCL IE TE DE Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W ...

Page 631: ...se bits are only valid in the case of page mapping to PCMCIA connected to areas 5 and 6 For details of the settings see the description of the DSA2 DSA0 bits in section 14 2 4 DMA Channel Control Registers 0 3 CHCR0 CHCR3 Bit 24 Destination Address Wait Control Select DTC Specifies CS5 or CS6 space wait cycle control for PCMCIA access This bit selects the wait control register in the BSC that perf...

Page 632: ...ction 14 2 4 DMA Channel Control Registers 0 3 CHCR0 CHCR3 Bits 13 and 12 Source Address Mode 1 and 0 SM1 SM0 These bits specify incrementing decrementing of the DMA transfer source address The specification of these bits is ignored when data is transferred from an external device to external memory in single address mode For details of the settings see the description of the SM1 and SM0 bits in s...

Page 633: ...efore TE is set to 1 for example due to an NMI interrupt address error or clearing of the DE bit or the DME bit in DMAOR the TE bit is not set to 1 When this bit is 1 the transfer enabled state is not entered even if the DE bit is set to 1 For details of the settings see the description of the TE bit in section 14 2 4 DMA Channel Control Registers 0 3 CHCR0 CHCR3 Bit 0 DMAC Enable DE Enables opera...

Page 634: ... channels Note When DMAOR DBL 0 channels 4 to 7 cannot accept external requests When DMAOR DBL 1 one channel can be selected from among channels 0 7 by the combination of DTR SZ and DTR ID in the DTR format see figure 14 54 Table 14 14 shows the channel selection by DTR format in the DDT mode Table 14 14 Channel Selection by DTR Format DMAOR DBL 1 DTR ID 1 0 DTR SZ 2 0 101 DTR SZ 2 0 101 00 CH0 CH...

Page 635: ... 1 NMI Flag NMIF Indicates that NMI has been input This bit is set regardless of whether or not the DMAC is operating If this bit is set during data transfer transfers on all channels are suspended The CPU cannot write 1 to NMIF This bit can only be cleared by writing 0 after reading 1 For details of the settings see the description of the NMIF bit in section 14 2 5 DMA Operation Register DMAOR Bi...

Page 636: ...DMA Transfer For DMA transfer in DDT mode the DMAOR DBL setting selects either four or eight channels External requests are accepted on channels 0 3 when DMAOR DBL 0 and on channels 0 7 when DMAOR DBL 1 For further information on these settings see the entry on the DBL bit in section 14 7 5 DMA Operation Register DMAOR 14 8 3 Transfer Channel Notification in DDT Mode When the DMAC is set up for fo...

Page 637: ...nction of BAVL BAVL BAVL BAVL Function of BAVL BAVL BAVL BAVL TDACK High Bus available data bus enabled TDACK Low Notification of channel number ID2 14 8 4 Clearing Request Queues by DTR Format In DDT mode the request queues of any channel can be cleared by using DTR ID DTR MD DTR SZ and DTR COUNT 7 4 in a DTR format This function is only available when DMAOR DBL 1 Table 14 17 shows the DTR format...

Page 638: ...Clear the CH2 request queues 0100 Clear the CH3 request queues 0101 Clear the CH4 request queues 0110 Clear the CH5 request queues 0111 Clear the CH6 request queues 1 00 11 110 1000 Clear the CH7 request queues Note SH7750R DTR SZ DTR 63 61 DTR ID DTR 59 58 DTR MD DTR 57 56 DTR COUNT 7 4 DTR 55 52 14 8 5 Interrupt Request Codes When the number of transfers specified in DMATCR has been finished and...

Page 639: ...nd interrupt H 6A0 DMTE4 CH4 transfer end interrupt H 780 DMTE5 CH5 transfer end interrupt H 7A0 DMTE6 CH6 transfer end interrupt H 7C0 DMTE7 CH7 transfer end interrupt H 7E0 DMAE Address error interrupt H 6C0 Low DMTE4 DMTE7 These codes are not used in the SH7750 or SH7750S CKIO RA DTR CA D1 D2 RD BA 00 ID1 ID0 RAS CAS WE D63 D0 A25 A0 D0 Figure 14 55 Single Address Mode Burst Mode External Bus E...

Page 640: ... page 590 of 986 CKIO RA DTR CA D1 D2 RD BA 00 ID1 ID0 RAS CAS WE D63 D0 A25 A0 D0 Figure 14 56 Single Address Mode Burst Mode External Bus External Device 32 Byte Block Transfer On Demand Data Transfer on Channel 4 ...

Page 641: ...before making a transition to the module standby state standby mode or deep sleep mode Either check that TE 1 in the SH7750 or SH7750S s CHCR0 CHCR3 or in the SH7750R s CHCR0 CHCR7 or clear DME to 0 in DMAOR to terminate DMA transfer When DME is cleared to 0 in DMAOR transfer halts at the end of the currently executing DMA bus cycle Note therefore that transfer may not end immediately depending on...

Page 642: ...detection in the SH7750R an external request that has been accepted can be cancelled in the following way Firstly negate DREQ and change the value of CHCR DS from 1 to 0 After that set the CHCR DS bit back to 1 then assert DREQ Though the SH7750R does not have a DMAOR COD bit similar to when the DMAOR COD bit is 1 in the SH7750S external requests that have once been accepted can be cancelled when ...

Page 643: ...face with FIFO SCIF 15 1 1 Features SCI features are listed below Choice of synchronous or asynchronous serial communication mode Asynchronous mode Serial data communication is executed using an asynchronous system in which synchronization is achieved character by character Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous ...

Page 644: ...uffering is used in both the transmitter and the receiver enabling continuous transmission and continuous reception of serial data On chip baud rate generator allows any bit rate to be selected Choice of serial clock source internal clock from baud rate generator or external clock from SCK pin Four interrupt sources There are four interrupt sources transmit data empty transmit end receive data ful...

Page 645: ...ption control Baud rate generator Clock External clock Pφ Pφ 4 Pφ 16 Pφ 64 TEI TXI RXI ERI SCI Bus interface Internal data bus SCSPTR1 SCRSR1 Receive shift register SCRDR1 Receive data register SCTSR1 Transmit shift register SCTDR1 Transmit data register SCSMR1 Serial mode register SCSCR1 Serial control register SCSSR1 Serial status register SCBRR1 Bit rate register SCSPTR1 Serial port register Fi...

Page 646: ...ynchronous mode the data format and the bit rate and to perform transmitter receiver control With the exception of the serial port register the SCI registers are initialized in standby mode and in the module standby state as well as after a power on reset or manual reset When recovering from standby mode or the module standby state the registers must be set again Table 15 2 SCI Registers Name Abbr...

Page 647: ...U 15 2 2 Receive Data Register SCRDR1 Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R SCRDR1 is the register that stores received serial data When the SCI has received one byte of serial data it transfers the received data from SCRSR1 to SCRDR1 where it is stored and completes the receive operation SCRSR1 is then enabled for reception Since SCRSR1 and SCRDR1 function as a dou...

Page 648: ...rial status register SCSSR1 is set to 1 SCTSR1 cannot be directly read or written to by the CPU 15 2 4 Transmit Data Register SCTDR1 Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W SCTDR1 is an 8 bit register that stores data for serial transmission When the SCI detects that SCTSR1 is empty it transfers the transmit data written in SCTDR1 to SCTSR1 and starts ...

Page 649: ...h CHR Selects 7 or 8 bits as the data length in asynchronous mode In synchronous mode a fixed data length of 8 bits is used regardless of the CHR setting Bit 6 CHR Description 0 8 bit data Initial value 1 7 bit data Note When 7 bit data is selected the MSB bit 7 of SCTDR1 is not transmitted Bit 5 Parity Enable PE In asynchronous mode selects whether or not parity bit addition is performed in trans...

Page 650: ...bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd In reception a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd Bit 3 Stop Bit Length STOP Selects 1 or 2 bits as the stop bit length in asynchronous mode The STOP bit setting is only valid in asynchronous mode ...

Page 651: ...cted from Pφ Pφ 4 Pφ 16 and Pφ 64 according to the setting of bits CKS1 and CKS0 For the relation between the clock source the bit rate register setting and the baud rate see section 15 2 9 Bit Rate Register SCBRR1 Bit 1 CKS1 Bit 0 CKS0 Description 0 0 Pφ clock Initial value 1 Pφ 4 clock 1 0 Pφ 16 clock 1 Pφ 64 clock Note Pφ Peripheral clock 15 2 6 Serial Control Register SCSCR1 Bit 7 6 5 4 3 2 1 ...

Page 652: ...d from SCRSR1 to SCRDR1 and the RDRF flag in SCSSR1 is set to 1 Bit 6 RIE Description 0 Receive data full interrupt RXI request and receive error interrupt ERI request disabled Initial value 1 Receive data full interrupt RXI request and receive error interrupt ERI request enabled Note RXI and ERI interrupt requests can be cleared by reading 1 from the RDRF flag or the FER PER or ORER flag then cle...

Page 653: ...e or when the MP bit is cleared to 0 Bit 3 MPIE Description 0 Multiprocessor interrupts disabled normal reception performed Initial value Clearing conditions When the MPIE bit is cleared to 0 When data with MPB 1 is received 1 Multiprocessor interrupts enabled Note When receive data including MPB 1 is received the MPIE bit is cleared to 0 automatically and generation of RXI and ERI interrupts when...

Page 654: ...ls of clock source selection see table 15 9 in section 15 3 Operation Bit 1 CKE1 Bit 0 CKE0 Description 0 0 Asynchronous mode Internal clock SCK pin functions as input pin input signal ignored 1 Synchronous mode Internal clock SCK pin functions as serial clock output 1 1 Asynchronous mode Internal clock SCK pin functions as clock output 2 Synchronous mode Internal clock SCK pin functions as serial...

Page 655: ...ag and MPB flag are read only flags and cannot be modified SCSSR1 is initialized to H 84 by a power on reset or manual reset in standby mode and in the module standby state Bit 7 Transmit Data Register Empty TDRE Indicates that data has been transferred from SCTDR1 to SCTSR1 and the next serial transmit data can be written to SCTDR1 Bit 7 TDRE Description 0 Valid transmit data has been written to ...

Page 656: ... completed while the RDRF flag is still set to 1 an overrun error will occur and the receive data will be lost Bit 5 Overrun Error ORER Indicates that an overrun error occurred during reception causing abnormal termination Bit 5 ORER Description 0 Reception in progress or reception has ended normally 1 Initial value Clearing conditions Power on reset manual reset standby mode or module standby Whe...

Page 657: ... the receive data is transferred to SCRDR1 but the RDRF flag is not set Serial reception cannot be continued while the FER flag is set to 1 Bit 3 Parity Error PER Indicates that a parity error occurred during reception with parity addition in asynchronous mode causing abnormal termination Bit 3 PER Description 0 Reception in progress or reception has ended normally 1 Initial value Clearing conditi...

Page 658: ...n to The read value is undefined Note This bit is prepared for storing a multi processor bit in the received data when the receipt is carried out with a multi processor format in asynchronous mode This bit does not function correctly in this LSI However do not use the read value from this bit Bit 0 Multiprocessor Bit Transfer MPBT When transmission is performed using a multiprocessor format in asy...

Page 659: ...ialized in the module standby state or standby mode Bit 7 Error Interrupt Only EIO When the EIO bit is 1 an RXI interrupt request is not sent to the CPU even if the RIE bit is set to 1 When the DMAC is used this setting means that only ERI interrupts are handled by the CPU The DMAC transfers read data to memory or another peripheral module This bit specifies enabling or disabling of the RXI interr...

Page 660: ...et as a port output pin and outputs the value set by the SPB0DT bit the TE bit in SCSCR1 should be cleared to 0 Bit 1 SPB0IO Description 0 SPB0DT bit value is not output to the TxD pin Initial value 1 SPB0DT bit value is output to the TxD pin Bit 0 Serial Port Break Data SPB0DT Specifies the serial port RxD pin input data and TxD pin output data The TxD pin output condition is specified by the SPB...

Page 661: ...gnal Serial clock output signal Serial clock input signal Clock input enable signal MD0 SCK Mode setting register SPTRW Write to SPTR SPTRR Read SPTR Note Signals that set the SCK pin function as internal clock output or external clock input according to the CKE0 and CKE1 bits in SCSCR1 and the C bit in SCSMR1 Figure 15 2 MD0 SCK Pin ...

Page 662: ...PTRW SCI R Q D SPB0IO C Reset SPTRW R Q D SPB0DT C MD7 TxD Mode setting register Transmit enable signal Serial transmit data SPTRW Write to SPTR Figure 15 3 MD7 TxD Pin Internal data bus SCI RxD SPTRR Serial receive data SPTRR Read SPTR Figure 15 4 RxD Pin ...

Page 663: ...t all times SCBRR1 is initialized to H FF by a power on reset or manual reset in standby mode and in the module standby state The SCBRR1 setting is found from the following equations Asynchronous mode N 106 1 64 22n 1 B φ P Synchronous mode N 106 1 8 22n 1 B φ P Where B Bit rate bits s N SCBRR1 setting for baud rate generator 0 N 255 Pφ Peripheral module operating frequency MHz n Baud rate generat...

Page 664: ...e bit rate error in asynchronous mode is found from the following equation Error 100 P 106 N 1 B 64 22n 1 φ 1 Table 15 3 shows sample SCBRR1 settings in asynchronous mode and table 15 4 shows sample SCBRR1 settings in synchronous mode ...

Page 665: ...0 0 2 8 51 0 2 13 78 0 3 0 00 0 4 2 34 31250 0 1 0 00 0 1 4 86 0 1 22 88 0 2 0 00 38400 0 1 18 62 0 1 14 67 0 1 0 00 Pφ φ φ φ MHz 3 6864 4 4 9152 5 Bit Rate bits s n N Error n N Error n N Error n N Error 110 2 64 0 70 2 70 0 03 2 86 0 31 2 88 0 25 150 1 191 0 00 1 207 0 16 1 255 0 00 2 64 0 16 300 1 95 0 00 1 103 0 16 1 127 0 00 1 129 0 16 600 0 191 0 00 0 207 0 16 0 255 0 00 1 64 0 16 1200 0 95 0...

Page 666: ...00 0 23 0 00 0 25 0 16 19200 0 9 2 34 0 9 0 00 0 11 0 00 0 12 0 16 31250 0 5 0 00 0 5 2 40 0 6 5 33 0 7 0 00 38400 0 4 2 34 0 4 0 00 0 5 0 00 0 6 6 99 Pφ φ φ φ MHz 9 8304 10 12 12 288 Bit Rate bits s n N Error n N Error n N Error n N Error 110 2 174 0 26 2 177 0 25 2 212 0 03 2 217 0 08 150 2 127 0 00 2 129 0 16 2 155 0 16 2 159 0 00 300 1 255 0 00 2 64 0 16 2 77 0 16 2 79 0 00 600 1 127 0 00 1 12...

Page 667: ... 0 63 0 00 0 64 0 16 19200 0 23 0 00 0 25 0 16 0 31 0 00 0 32 1 36 31250 0 14 1 70 0 15 0 00 0 19 1 70 0 19 0 00 38400 0 11 0 00 0 12 0 16 0 15 0 00 0 15 1 73 Pφ φ φ φ MHz 24 24 576 28 7 30 Bit Rate bits s n N Error n N Error n N Error n N Error 110 3 106 0 44 3 108 0 08 3 126 0 31 3 132 0 13 150 3 77 0 16 3 79 0 00 3 92 0 46 3 97 0 35 300 2 155 0 16 2 159 0 00 2 186 0 08 2 194 0 16 600 2 77 0 16 ...

Page 668: ... 5k 1 99 1 199 2 99 2 178 2 187 5k 0 199 1 99 1 199 2 89 2 93 10k 0 99 0 199 1 99 1 178 1 187 25k 0 39 0 79 0 159 1 71 1 74 50k 0 19 0 39 0 79 0 143 0 149 100k 0 9 0 19 0 39 0 71 0 74 250k 0 3 0 7 0 15 0 29 500k 0 1 0 3 0 7 0 14 1M 0 0 0 1 0 3 2M 0 0 0 1 Note As far as possible the setting should be made so that the error is within 1 Legend Blank No setting is available A setting is available but ...

Page 669: ...Bit Rate for Various Frequencies with Baud Rate Generator Asynchronous Mode Settings Pφ φ φ φ MHz Maximum Bit Rate bits s n N 2 62500 0 0 2 097152 65536 0 0 2 4576 76800 0 0 3 93750 0 0 3 6864 115200 0 0 4 125000 0 0 4 9152 153600 0 0 8 250000 0 0 9 8304 307200 0 0 12 375000 0 0 14 7456 460800 0 0 16 500000 0 0 19 6608 614400 0 0 20 625000 0 0 24 750000 0 0 24 576 768000 0 0 28 7 896875 0 0 30 937...

Page 670: ... 62500 4 9152 1 2288 76800 8 2 0000 125000 9 8304 2 4576 153600 12 3 0000 187500 14 7456 3 6864 230400 16 4 0000 250000 19 6608 4 9152 307200 20 5 0000 312500 24 6 0000 375000 24 576 6 1440 384000 28 7 7 1750 448436 30 7 5000 468750 Table 15 7 Maximum Bit Rate with External Clock Input Synchronous Mode Pφ φ φ φ MHz External Input Clock MHz Maximum Bit Rate bits s 8 1 3333 1333333 3 16 2 6667 26666...

Page 671: ... these parameters determines the transfer format and character length Detection of framing parity and overrun errors and breaks during reception Choice of internal or external clock as SCI clock source When internal clock is selected The SCI operates on the baud rate generator clock and a clock with the same frequency as the bit rate can be output When external clock is selected A clock with a fre...

Page 672: ...t 1 2 bits 1 0 7 bit data 1 bit 1 Asynchronous mode multiprocessor format 2 bits 1 Synchronous mode 8 bit data No None Note An asterisk in the table means Don t care Table 15 9 SCSMR1 and SCSCR1 Settings for SCI Clock Source Selection SCSMR1 SCSCR1 Setting SCI Transmit Receive Clock Bit 7 C A A A A Bit 1 CKE1 Bit 0 CKE0 Mode Clock Source SCK Pin Function 0 0 0 Internal SCI does not use SCK pin 1 O...

Page 673: ...n line and when it goes to the space state low level recognizes a start bit and starts serial communication One serial communication character consists of a start bit low level followed by data in LSB first order a parity bit high or low level and finally one or two stop bits high level In asynchronous mode the SCI performs synchronization at the falling edge of the start bit in reception The SCI ...

Page 674: ... data STOP STOP 0 1 0 0 S 8 bit data P STOP 0 1 0 1 S 8 bit data P STOP STOP 1 0 0 0 S 7 bit data STOP 1 0 0 1 S 7 bit data STOP STOP 1 1 0 0 S 7 bit data P STOP 1 1 0 1 S 7 bit data P STOP STOP 0 1 0 S 8 bit data MPB STOP 0 1 1 S 8 bit data MPB STOP STOP 1 1 0 S 7 bit data MPB STOP 1 1 1 S 7 bit data MPB STOP STOP S Start bit STOP Stop bit P Parity bit MPB Multiprocessor bit Note An asterisk in t...

Page 675: ...figure 15 6 D0 D1 D2 D3 D4 D5 D6 D7 0 1 1 1 One frame 0 Figure 15 6 Relation between Output Clock and Transfer Data Phase Asynchronous Mode Data Transfer Operations SCI Initialization Asynchronous Mode Before transmitting and receiving data it is necessary to clear the TE and RE bits in SCSCR1 to 0 then initialize the SCI as described below When the operating mode transfer format etc is changed th...

Page 676: ...tings are made 2 Set the transmit receive format in SCSMR1 3 Write a value corresponding to the bit rate into SCBRR1 Not necessary if an external clock is used 4 Wait at least one bit interval then set the TE bit or RE bit in SCSCR1 to 1 Also set the RIE TIE TEIE and MPIE bits Setting the TE and RE bits enables the TxD and RxD pins to be used When transmitting the SCI will go to the mark state whe...

Page 677: ...R1 and clear the TDRE flag to 0 2 Serial transmission continuation procedure To continue serial transmission read 1 from the TDRE flag to confirm that writing is possible then write data to SCTDR1 and then clear the TDRE flag to 0 Checking and clearing of the TDRE flag is automatic when the direct memory access controller DMAC is activated by a transmit data empty interrupt TXI request and data is...

Page 678: ...ity bit even or odd parity or one multiprocessor bit is output A format in which neither a parity bit nor a multiprocessor bit is output can also be selected d Stop bit s One or two 1 bits stop bits are output e Mark state 1 is output continuously until the start bit that starts the next transmission is sent 3 The SCI checks the TDRE flag at the timing for sending the stop bit If the TDRE flag is ...

Page 679: ...en to SCTDR1 and TDRE flag cleared to 0 by TXI interrupt handler One frame TEI interrupt request TXI interrupt request Figure 15 9 Example of Transmit Operation in Asynchronous Mode Example with 8 Bit Data Parity One Stop Bit Serial Data Reception Asynchronous Mode Figure 15 10 shows a sample flowchart for serial reception Use the following procedure for serial data reception after enabling the SC...

Page 680: ...e ORER PER and FER flags are all cleared to 0 Reception cannot be resumed if any of these flags are set to 1 In the case of a framing error a break can be detected by reading the value of the RxD pin 2 SCI status check and receive data read Read SCSSR1 and check that RDRF 1 then read the receive data in SCRDR1 and clear the RDRF flag to 0 3 Serial reception continuation procedure To continue seria...

Page 681: ... ORER 1 FER 1 Break PER 1 End Yes Yes No Yes No No No Yes Clear ORER PER and FER flags in SCSSR1 to 0 Parity error handling Framing error handling Clear RE bit in SCSCR1 to 0 Overrun error handling Figure 15 10 Sample Serial Reception Flowchart 2 ...

Page 682: ...n is as shown in table 15 11 Note No further receive operations can be performed when a receive error has occurred Also note that the RDRF flag is not set to 1 in reception and so the error flags must be cleared to 0 4 If the EIO bit in SCSPTR1 is cleared to 0 and the RIE bit in SCSCR1 is set to 1 when the RDRF flag changes to 1 a receive data full interrupt RXI request is generated If the RIE bit...

Page 683: ...t Data Parity bit Stop bit Start bit Data Parity bit Stop bit RXI interrupt request One frame SCRDR1 data read and RDRF flag cleared to 0 by RXI interrupt handler ERI interrupt request generated by framing error Figure 15 11 Example of SCI Receive Operation Example with 8 Bit Data Parity One Stop Bit ...

Page 684: ...communication as data with a 1 multiprocessor bit added It then sends transmit data as data with a 0 multiprocessor bit added The receiving station skips the data until data with a 1 multiprocessor bit is sent When data with a 1 multiprocessor bit is received the receiving station compares that data with its own ID The station whose ID matches then receives the data sent next Stations whose ID doe...

Page 685: ...f Inter Processor Communication Using Multiprocessor Format Transmission of Data H AA to Receiving Station A Data Transfer Formats There are four data transfer formats When the multiprocessor format is specified the parity bit specification is invalid For details see table 15 10 Clock See the description under Clock in section 15 3 2 Data Transfer Operations Multiprocessor Serial Data Transmission...

Page 686: ...and write ID data to SCTDR1 Finally clear the TDRE flag to 0 2 Preparation for data transfer Read SCSSR1 and check that the TEND flag is set to 1 then set the MPBT bit in SCSSR1 to 1 3 Serial data transmission Write the first transmit data to SCTDR1 then clear the TDRE flag to 0 To continue data transmission be sure to read 1 from the TDRE flag to confirm that writing is possible then write data t...

Page 687: ... starts the next transmission is sent 3 The SCI checks the TDRE flag at the timing for sending the stop bit If the TDRE flag is set to 1 the TEND flag in SCSSR1 is set to 1 the stop bit is sent and then the line goes to the mark state in which 1 is output If the TEIE bit in SCSCR1 is set to 1 at this time a transmit end interrupt TEI request is generated 4 The SCI monitors the TDRE flag When TDRE ...

Page 688: ... 1 1 Multi proces sor bit Multi proces sor bit Multi proces sor bit Stop bit Start bit Stop bit Stop bit Start bit Data Data Data Start bit TDRE TEND One frame Idle state mark state Figure 15 14 Example of SCI Transmit Operation Example with 8 Bit Data Multiprocessor Bit One Stop Bit Multiprocessor Serial Data Reception Figure 15 15 shows a sample flowchart for multiprocessor serial reception Use ...

Page 689: ...IE bit is set to 0 then read the receive data in SCRDR1 and compare it with this station s ID If the data is not this station s ID set the MPIE bit to 1 again and clear the RDRF flag to 0 If the data is this station s ID clear the RDRF flag to 0 3 SCI status check and data reception Read SCSSR1 and check that the RDRF flag is set to 1 then read the data in SCRDR1 4 Receive error handling and break...

Page 690: ...ER 1 FER 1 Error handling Overrun error handling Break Framing error handling Clear RE bit in SCSCR1 to 0 Clear ORER and FER flags in SCSSR1 to 0 End Yes No No Yes Yes No Figure 15 15 Sample Multiprocessor Serial Reception Flowchart 2 ...

Page 691: ... 0 by RXI interrupt handler As data is not this station s ID MPIE bit is set to 1 again RXI interrupt request The RDRF flag is cleared to 0 by the RXI interrupt handler MPB Serial data Start bit Data ID2 Stop bit Start bit Data Data2 Stop bit Idle state mark state a Data does not match station s ID SCRDR1 value RXI interrupt request multiprocessor interrupt MPIE 0 SCRDR1 data read and RDRF flag cl...

Page 692: ... In synchronous mode data is transmitted or received in synchronization with clock pulses making it suitable for high speed serial communication Inside the SCI the transmitter and receiver are independent units enabling full duplex communication Both the transmitter and the receiver also have a double buffered structure so that data can be read or written during transmission or reception enabling ...

Page 693: ...lock is output from the SCK pin Eight serial clock pulses are output in the transfer of one character and when no transfer is performed the clock is fixed high In reception only if an on chip clock source is selected clock pulses are output while RE 1 When the last data is received RE should be cleared to 0 before the end of bit 7 Data Transfer Operations SCI Initialization Synchronous Mode Before...

Page 694: ...ts in SCSCR1 to 0 Initialization 1 Set the clock selection in SCSCR1 Be sure to clear bits RIE TIE TEIE and MPIE TE and RE to 0 2 Set transmit receive format in SCSMR1 3 Write a value corresponding to the bit rate into SCBRR1 Not necessary if an external clock is used 4 Wait at least one bit interval then set the TE bit or RE bit in SCSCR1 to 1 Also set the RIE TIE TEIE and MPIE bits Setting the T...

Page 695: ...a to SCTDR1 and clear TDRE flag in SCSSR1 to 0 1 SCI status check and transmit data write Read SCSSR1 and check that the TDRE flag is set to 1 then write transmit data to SCTDR1 and clear the TDRE flag to 0 2 To continue serial transmission be sure to read 1 from the TDRE flag to confirm that writing is possible then write data to SCTDR1 and then clear the TDRE flag to 0 Checking and clearing of t...

Page 696: ...he LSB bit 0 and ending with the MSB bit 7 3 The SCI checks the TDRE flag at the timing for sending the MSB bit 7 If the TDRE flag is cleared to 0 data is transferred from SCTDR1 to SCTSR1 and serial transmission of the next frame is started If the TDRE flag is set to 1 the TEND flag in SCSSR1 is set to 1 the MSB bit 7 is sent and the TxD pin maintains its state If the TEIE bit in SCSCR1 is set to...

Page 697: ...Yes No No Error handling 1 Receive error handling If a receive error occurs read the ORER flag in SCSSR1 and after performing the appropriate error handling clear the ORER flag to 0 Transfer cannot be resumed if the ORER flag is set to 1 2 SCI status check and receive data read Read SCSSR1 and check that the RDRF flag is set to 1 then read the receive data in SCRDR1 and clear the RDRF flag to 0 Tr...

Page 698: ... SCRDR1 If this check is passed the RDRF flag is set to 1 and the receive data is stored in SCRDR1 If a receive error is detected in the error check the operation is as shown in table 15 11 Neither transmit nor receive operations can be performed subsequently when a receive error has been found in the error check Also as the RDRF flag is not set to 1 when receiving the flag must be cleared to 0 3 ...

Page 699: ...ne frame RXI interrupt request ERI interrupt request due to overrun error Figure 15 22 Example of SCI Receive Operation Simultaneous Serial Data Transmission and Reception Synchronous Mode Figure 15 23 shows a sample flowchart for simultaneous serial transmit and receive operations Use the following procedure for simultaneous serial data transmit and receive operations after enabling the SCI for t...

Page 700: ... check that the RDRF flag is set to 1 then read the receive data in SCRDR1 and clear the RDRF flag to 0 Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt 4 Serial transmission reception continuation procedure To continue serial transmission reception finish reading the RDRF flag reading SCRDR1 and clearing the RDRF flag to 0 before the MSB bit 7 of the current fram...

Page 701: ...ransfer The RDRF flag is cleared to 0 automatically when a receive data register SCRDR1 read is performed by the DMAC When the ORER FER or PER flag in SCSSR1 is set to 1 an ERI interrupt request is generated The DMAC cannot be activated by an ERI interrupt request When receive data processing is to be carried out by the DMAC and receive error handling is to be performed by means of an interrupt to...

Page 702: ...hown in table 15 13 If there is an overrun error data is not transferred from SCRSR1 to SCRDR1 and the receive data is lost Table 15 13 SCSSR1 Status Flags and Transfer of Receive Data SCSSR1 Status Flags Receive Errors RDRF ORER FER PER Receive Data Transfer SCRSR1 SCRDR1 Overrun error 1 1 0 0 X Framing error 0 0 1 0 O Parity error 0 0 0 1 O Overrun error framing error 1 1 1 0 X Overrun error par...

Page 703: ...sion When the TE bit is cleared to 0 the transmitter is initialized regardless of its current state and the TxD pin becomes an output port outputting the value 0 Receive Error Flags and Transmit Operations Synchronous Mode Only Transmission cannot be started when a receive error flag ORER PER or FER is set to 1 even if the TDRE flag is set to 1 Be sure to clear the receive error flags to 0 before ...

Page 704: ...onous Mode The receive margin in asynchronous mode can therefore be expressed as shown in equation 1 M 0 5 L 0 5 F 1 F 100 1 2N D 0 5 N 1 M Receive margin N Ratio of clock frequency to bit rate N 16 D Clock duty cycle D 0 to 1 0 L Frame length L 9 to 12 F Absolute deviation of clock frequency From equation 1 if F 0 and D 0 5 the receive margin is 46 875 as given by equation 2 When D 0 5 and F 0 M ...

Page 705: ...ed by the DMAC independently of the interrupt handling program When Using Synchronous External Clock Mode Do not set TE or RE to 1 until at least 4 peripheral operating clock cycles after external clock SCK has changed from 0 to 1 Only set both TE and RE to 1 when external clock SCK is 1 In reception note that if RE is cleared to 0 from 2 5 to 3 5 peripheral operating clock cycles after the rising...

Page 706: ...Rev 6 0 07 02 page 656 of 986 ...

Page 707: ...r UART or Asynchronous Communication Interface Adapter ACIA There is a choice of 8 serial data transfer formats Data length 7 or 8 bits Stop bit length 1 or 2 bits Parity Even odd none Receive error detection Parity framing and overrun errors Break detection If the receive data following that in which a framing error occurred is also at the space 0 level and there is a frame error a break is detec...

Page 708: ... issuing a DMA transfer request in the event of a transmit FIFO data empty or receive FIFO data full interrupt When not in use the SCIF can be stopped by halting its clock supply to reduce power consumption Modem control functions RTS2 and CTS2 are provided The amount of data in the transmit receive FIFO registers and the number of receive errors in the receive data in the receive FIFO register ca...

Page 709: ...ock External clock Pφ Pφ 4 Pφ 16 Pφ 64 TXI RXI ERI BRI SCIF Bus interface Internal data bus SCSCR2 SCSPTR2 SCRSR2 Receive shift register SCFRDR2 Receive FIFO data register SCTSR2 Transmit shift register SCFTDR2 Transmit FIFO data register SCSMR2 Serial mode register SCSCR2 Serial control register SCFSR2 Serial status register SCBRR2 Bit rate register SCSPTR2 Serial port register SCFCR2 FIFO contro...

Page 710: ...I O Transmission enabled Modem control pin MD8 RTS2 I O Transmission request Note After a power on reset these pins function as mode input pins MD0 MD1 MD2 MD7 and MD8 These pins can function as serial pins by setting the SCIF operation with the TE RE and CKE1 bits in SCSCR2 and the MCE bit in SCFCR2 These pins are made to function as serial pins by performing SCIF operation settings with the TE R...

Page 711: ...rol register SCFCR2 R W H 0000 H FFE80018 H IFE80018 16 FIFO data count register SCFDR2 R H 0000 H FFE8001C H IFE8001C 16 Serial port register SCSPTR2 R W H 0000 2 H FFE80020 H IFE80020 16 Line status register SCLSR2 R W 3 H 0000 H FFE80024 H IFE80024 16 Notes 1 Only 0 can be written to clear flags Bits 15 to 8 3 and 2 are read only and cannot be modified 2 The value of bits 6 4 and 0 is undefined...

Page 712: ...f a read is performed when there is no receive data in the receive FIFO register an undefined value will be returned When the receive FIFO register is full of receive data subsequent serial data is lost The contents of SCFRDR2 are undefined after a power on reset or manual reset 16 2 3 Transmit Shift Register SCTSR2 Bit 7 6 5 4 3 2 1 0 R W SCTSR2 is the register used to transmit serial data To per...

Page 713: ...in this case is ignored The contents of SCFTDR2 are undefined after a power on reset or manual reset 16 2 5 Serial Mode Register SCSMR2 Bit 15 14 13 12 11 10 9 8 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Bit 7 6 5 4 3 2 1 0 CHR PE O E STOP CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 R W R R W R W R W R W R R W R W SCSMR2 is a 16 bit register used to set the SCIF s serial transfer format and se...

Page 714: ... bit addition and checking The O E bit setting is invalid when parity addition and checking is disabled Bit 4 O E E E E Description 0 Even parity 1 Initial value 1 Odd parity 2 Notes 1 When even parity is set parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even In reception a check is performed to see if the total...

Page 715: ...urce the bit rate register setting and the baud rate see section 16 2 8 Bit Rate Register SCBRR2 Bit 1 CKS1 Bit 0 CKS0 Description 0 0 Pφ clock Initial value 1 Pφ 4 clock 1 0 Pφ 16 clock 1 Pφ 64 clock Note Pφ Peripheral clock 16 2 6 Serial Control Register SCSCR2 Bit 15 14 13 12 11 10 9 8 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Bit 7 6 5 4 3 2 1 0 TIE RIE TE RE REIE CKE1 Initial value 0 ...

Page 716: ...t to 1 a receive error interrupt ERI request when the ER flag in SCFSR2 is set to 1 and a break interrupt BRI request when the BRK flag in SCFSR2 or the ORER flag in SCLSR2 is set to 1 Bit 6 RIE Description 0 Receive data full interrupt RXI request receive error interrupt ERI request and break interrupt BRI request disabled Initial value 1 Receive data full interrupt RXI request receive error inte...

Page 717: ...the RIE bit is 0 Bit 3 REIE Description 0 Receive error interrupt ERI and break interrupt BRI requests disabled Initial value 1 Receive error interrupt ERI and break interrupt BRI requests enabled Note Receive error interrupt ERI and break interrupt BRI requests can be cleared by reading 1 from the ER BRK or ORER flag then clearing the flag to 0 or by clearing the RIE and REIE bits to 0 When REIE ...

Page 718: ...ad only flags and cannot be modified SCFSR2 is initialized to H 0060 by a power on reset or manual reset It is not initialized in standby mode or in the module standby state Bits 15 to 12 Number of Parity Errors PER3 PER0 These bits indicate the number of data bytes in which a parity error occurred in the receive data stored in SCFRDR2 After the ER bit in SCFSR2 is set the value indicated by bits ...

Page 719: ...7 ER Description 0 No framing error or parity error occurred during reception Initial value Clearing conditions Power on reset or manual reset When 0 is written to ER after reading ER 1 1 A framing error or parity error occurred during reception Setting conditions When the SCIF checks whether the stop bit at the end of the receive data is 1 when reception ends and the stop bit is 0 When in recepti...

Page 720: ...ransmission is in progress Clearing conditions When transmit data is written to SCFTDR2 and 0 is written to TEND after reading TEND 1 When data is written to SCFTDR2 by the DMAC 1 Transmission has been ended Initial value Setting conditions Power on reset or manual reset When the TE bit in SCSCR2 is 0 When there is no transmit data in SCFTDR2 on transmission of the last bit of a 1 byte serial tran...

Page 721: ...r on reset or manual reset When the number of SCFTDR2 transmit data bytes falls to or below the transmit trigger set number as the result of a transmit operation Note As SCFTDR2 is a 16 byte FIFO register the maximum number of bytes that can be written when TDFE 1 is 16 transmit trigger set number Data written in excess of this will be ignored The number of data bytes in SCFTDR2 is indicated by th...

Page 722: ...rom SCFRDR2 Setting condition When there is a framing error in the data that is to be read next from SCFRDR2 Bit 2 Parity Error PER Indicates whether or not a parity error has been found in the data that is to be read next from SCFRDR2 Bit 2 PER Description 0 There is no parity error that is to be read from SCFRDR2 Initial value Clearing conditions Power on reset or manual reset When there is no p...

Page 723: ...a bytes in SCFRDR2 falls below the receive trigger set number after reading RDF 1 and 0 is written to RDF When SCFRDR2 is read by the DMAC until the number of receive data bytes in SCFRDR2 falls below the receive trigger set number 1 The number of receive data bytes in SCFRDR2 is equal to or greater than the receive trigger set number Setting condition When SCFRDR2 contains at least the receive tr...

Page 724: ...ata has arrived Setting condition When SCFRDR2 contains fewer than the receive trigger set number of receive data bytes and no further data has arrived for at least 15 etu after the stop bit of the last data received Note Equivalent to 1 5 frames with an 8 bit 1 stop bit format etu Elementary time unit time for transfer of 1 bit 16 2 8 Bit Rate Register SCBRR2 Bit 7 6 5 4 3 2 1 0 Initial value 1 1...

Page 725: ...ation between n and the clock SCSMR2 Setting n Clock CKS1 CKS0 0 Pφ 0 0 1 Pφ 4 0 1 2 Pφ 16 1 0 3 Pφ 64 1 1 The bit rate error in asynchronous mode is found from the following equation Error 1 100 P 106 N 1 B 64 22n 1 φ 16 2 9 FIFO Control Register SCFCR2 Bit 15 14 13 12 11 10 9 8 RSTRG2 RSTRG1 RSTRG0 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R W R W R W Bit 7 6 5 4 3 2 1 0 RTRG1 RTRG0 TTRG1 TTRG...

Page 726: ... RTS2 Output Active Trigger RSTRG2 RSTG1 and RSTG0 These bits output the high level to the RTS2 signal when the number of received data stored in the receive FIFO data register SCFRDR2 exceeds the trigger number as shown in the table below Bit 10 RSTRG2 Bit 9 RSTRG1 Bit 8 RSTRG0 RTS2 RTS2 RTS2 RTS2 Output Active Trigger 0 15 Initial value 0 1 1 0 4 0 1 1 6 0 8 0 1 10 0 12 1 1 1 14 Bits 7 and 6 Rec...

Page 727: ...S2 modem control signals Bit 3 MCE Description 0 Modem signals disabled Initial value 1 Modem signals enabled Note CTS2 is fixed at active 0 regardless of the input value and RTS2 output is also fixed at 0 Bit 2 Transmit FIFO Data Register Reset TFRST Invalidates the transmit data in the transmit FIFO data register and resets it to the empty state Bit 2 TFRST Description 0 Reset operation disabled...

Page 728: ... SCFTDR2 and the lower 8 bits show the number of receive data bytes in SCFRDR2 SCFDR2 can be read by the CPU at all times Bit 15 14 13 12 11 10 9 8 T4 T3 T2 T1 T0 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R These bits show the number of untransmitted data bytes in SCFTDR2 A value of H 00 indicates that there is no transmit data and a value of H 10 indicates that SCFTDR2 is full of transmit d...

Page 729: ...2 pin by means of bits 5 and 4 Data can be read from and output data written to the RTS2 pin by means of bits 6 and 7 SCSPTR2 can be read or written to by the CPU at all times All SCSPTR2 bits except bits 6 4 and 0 are initialized to 0 by a power on reset or manual reset the value of bits 6 4 and 0 is undefined SCSPTR2 is not initialized in standby mode or in the module standby state Bits 15 to 8 ...

Page 730: ...tput to CTS2 pin Initial value 1 CTSDT bit value is output to CTS2 pin Bit 4 Serial Port CTS Port Data CTSDT Specifies the serial port CTS2 pin input output data Input or output is specified by the CTSIO bit see the description of bit 5 CTSIO for details In output mode the CTSDT bit value is output to the CTS2 pin The CTS2 pin value is read from the CTSDT bit regardless of the value of the CTSIO b...

Page 731: ...DT bit regardless of the value of the SPB2IO bit The initial value of this bit after a power on reset or manual reset is undefined Bit 0 SPB2DT Description 0 Input output data is low level 1 Input output data is high level SCIF I O port block diagrams are shown in figures 16 2 to 16 5 Reset Internal data bus SPTRW D7 D6 SCIF R Q D RTSIO C Reset Mode setting register SPTRR SPTRW R Q D RTSDT C MD8 S...

Page 732: ...bus SPTRW D5 D4 SCIF R Q D CTSIO C Reset SPTRR SPTRW R Q D CTSDT C SPTRW Write to SPTR SPTRR Read SPTR Note The pin function is designated as modem control by the MCE bit in SCFCR2 Modem control enable signal signal Figure 16 3 CTS2 CTS2 CTS2 CTS2 Pin ...

Page 733: ...ster SCIF R Q D D1 D0 SPB2IO C Reset SPTRW R Q D SPB2DT C MD1 TxD2 SPTRW Write to SPTR Transmit enable signal Serial transmit data Figure 16 4 MD1 TxD2 Pin Internal data bus Mode setting register SCIF MD2 RxD2 SPTRR D0 Serial receive data SPTRR Read SPTR Figure 16 5 MD2 RxD2 Pin ...

Page 734: ...abnormal termination Bit 0 ORER Description 0 Reception in progress or reception has ended normally 1 Initial value Clearing conditions Power on reset or manual reset When 0 is written to ORER after reading ORER 1 1 An overrun error occurred during reception 2 Setting condition When the next serial reception is completed while the receive FIFO is full Notes 1 The ORER flag is not affected and reta...

Page 735: ...bination of these parameters determines the transfer format and character length Detection of framing errors parity errors receive FIFO data full state overrun errors receive data ready state and breaks during reception Indication of the number of data bytes stored in the transmit and receive FIFO registers Choice of internal or external clock as SCIF clock source When internal clock is selected T...

Page 736: ...1 Mode Clock Source SCK2 Pin Function 0 Asynchronous mode Internal SCIF does not use SCK2 pin 1 External Inputs clock with frequency of 16 times the bit rate 16 3 2 Serial Operation Transmit Receive Format Table 16 5 shows the transmit receive formats that can be used Any of 8 transfer formats can be selected according to the SCSMR2 settings ...

Page 737: ... STOP 1 0 1 S 7 bit data STOP STOP 1 1 0 S 7 bit data P STOP 1 1 1 S 7 bit data P STOP STOP S Start bit STOP Stop bit P Parity bit Clock Either an internal clock generated by the on chip baud rate generator or an external clock input at the SCK2 pin can be selected as the SCIF s serial clock according to the setting of the CKE1 bit in SCSCR2 For details of SCIF clock source selection see table 16 ...

Page 738: ...nd RE bits to 0 does not change the contents of SCFSR2 SCFTDR2 or SCFRDR2 The TE bit should be cleared to 0 after all transmit data has been sent and the TEND flag in SCFSR2 has been set TEND can also be cleared to 0 during transmission but the data being transmitted will go to the mark state after the clearance Before setting TE again to start transmission the TFRST bit in SCFCR2 should first be ...

Page 739: ...d Wait No Yes 1 Set the clock selection in SCSCR2 Be sure to clear bits RIE and TIE and bits TE and RE to 0 2 Set the transmit receive format in SCSMR2 3 Write a value corresponding to the bit rate into SCBRR2 Not necessary if an external clock is used 4 Wait at least one bit interval then set the TE bit or RE bit in SCSCR2 to 1 Also set the RIE REIE and TIE bits Setting the TE and RE bits enables...

Page 740: ...that the TDFE flag is set to 1 then write transmit data to SCFTDR2 read 1 from the TDFE and TEND flags then clear these flags to 0 The number of transmit data bytes that can be written is 16 transmit trigger set number 2 Serial transmission continuation procedure To continue serial transmission read 1 from the TDFE flag to confirm that writing is possible then write data to SCFTDR2 and then clear ...

Page 741: ...is time a transmit FIFO data empty interrupt TXI request is generated The serial transmit data is sent from the TxD2 pin in the following order a Start bit One 0 bit is output b Transmit data 8 bit or 7 bit data is output in LSB first order c Parity bit One parity bit even or odd parity is output A format in which a parity bit is not output can also be selected d Stop bit s One or two 1 bits stop ...

Page 742: ...ity One Stop Bit 4 When modem control is enabled transmission can be stopped and restarted in accordance with the CTS2 input value When CTS2 is set to 1 if transmission is in progress the line goes to the mark state after transmission of one frame When CTS2 is set to 0 the next transmit data is output starting from the start bit Figure 16 9 shows an example of the operation when modem control is u...

Page 743: ... identify any error perform the appropriate error handling then clear the DR ER BRK and ORER flags to 0 In the case of a framing error a break can also be detected by reading the value of the RxD2 pin 2 SCIF status check and receive data read Read SCFSR2 and check that RDF 1 then read the receive data in SCFRDR2 read 1 from the RDF flag and then clear the RDF flag to 0 The transition of the RDF fl...

Page 744: ...ling ORER 1 Yes No No No 1 Whether a framing error or parity error has occurred that is to be read from SCFRDR2 can be ascertained from the FER and PER bits in SCFSR2 2 When a break signal is received receive data is not transferred to SCFRDR2 while the BRK flag is set However note that the last data in SCFRDR2 is H 00 the break data in which a framing error occurred is stored Figure 16 10 Sample ...

Page 745: ...un error check The SCIF checks that the ORER flag is 0 indicating that no overrun error has occurred d Break check The SCIF checks that the BRK flag is 0 indicating that the break state is not set If b c and d checks are passed the receive data is stored in SCFRDR2 Note Reception continues when parity error framing error occurs 4 If the RIE bit in SCSCR2 is set to 1 when the RDF or DR flag changes...

Page 746: ... 0 reception is possible SH7750 When RTS2 is 1 this indicates that SCFRDR2 contains 15 or more bytes of data SH7750S SH7750R When RTS2 is 1 this indicates that SCFRDR2 contains a number of data bytes equal to or greater than the RTS2 output active trigger set number The RTS2 output active trigger value is specified by bits 10 to 8 in the FIFO control register SCFCR2 described in section 16 2 9 FIF...

Page 747: ...upt request A transmit FIFO data empty request can activate the DMAC to perform data transfer When the RDF flag or DR flag in SCFSR2 is set to 1 a receive FIFO data full request is generated separately from the interrupt request A receive FIFO data full request can activate the DMAC to perform data transfer When using the DMAC for transmission reception set and enable the DMAC before making the SC...

Page 748: ...ster SCFSR2 is set when the number of receive data bytes in the receive FIFO data register SCFRDR2 has become equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in the FIFO control register SCFCR2 After RDF is set receive data equivalent to the trigger number can be read from SCFRDR2 allowing efficient continuous reception However if the number of data bytes in SCFRDR2...

Page 749: ...operates on a base clock with a frequency of 16 times the transfer rate In reception the SCIF synchronizes internally with the fall of the start bit which it samples on the base clock Receive data is latched at the rising edge of the eighth base clock pulse The timing is shown in figure 16 13 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 D0 D1 16 clocks 8 ...

Page 750: ...e value read will be the value two peripheral clock cycles earlier Overrun Error Flag SH7750 SCIF overrun error flag is not set in the case that overrun error and flaming error occurred simultaneously in receiving data that means 17th byte data which overrun was accompanying with flaming error In such case only SCFSR2 ER flag which shows occurrence of flaming error is set Receive FIFO stores data ...

Page 751: ...en flaming error SCFSR ER 1 is occurred bit7 to bit0 should be read out from SCFDR2 If bit7 to bit0 equals H 10 contents of the receive FIFO should be read When the data received last is not accompanied with flaming error SCFSR2 FER 0 both overrun error handling and flaming error handling shoud be conducted Bits 7 to 0 in SCFDR2 H 10 PER or FER bit in SCFSR2 set to 1 Figure 16 14 Overrun Error Fla...

Page 752: ...Rev 6 0 07 02 page 702 of 986 ...

Page 753: ...e are listed below Asynchronous mode Data length 8 bits Parity bit generation and checking Transmission of error signal parity error in receive mode Error signal detection and automatic data retransmission in transmit mode Direct convention and inverse convention both supported On chip baud rate generator allows any bit rate to be selected Three interrupt sources There are three interrupt sources ...

Page 754: ... rate generator Clock External clock Pφ Pφ 4 Pφ 16 Pφ 64 TXI RXI ERI SCI Bus interface Internal data bus SCSMR1 SCSCMR1 Smart card mode register SCRSR1 Receive shift register SCRDR1 Receive data register SCTSR1 Transmit shift register SCTDR1 Transmit data register SCSMR1 Serial mode register SCSCR1 Serial control register SCSSR1 Serial status register SCBRR1 Bit rate register SCSPTR1 Serial port r...

Page 755: ... initialized in standby mode and in the module standby state as well as by a power on reset or manual reset When recovering from standby mode or the module standby state the registers must be set again Table 17 2 Smart Card Interface Registers Name Abbreviation R W Initial Value P4 Address Area 7 Address Access Size Serial mode register SCSMR1 R W H 00 H FFE00000 H 1FE00000 8 Bit rate register SCB...

Page 756: ...er Direction SDIR Selects the serial parallel conversion format Bit 3 SDIR Description 0 SCTDR1 contents are transmitted LSB first Initial value Receive data is stored in SCRDR1 LSB first 1 SCTDR1 contents are transmitted MSB first Receive data is stored in SCRDR1 MSB first Bit 2 Smart Card Data Invert SINV Specifies inversion of the data logic level This function is used together with the bit 3 f...

Page 757: ...cates completion of transmission and the type of clock output used The details of the additional clock output control mode are specified by the CKE1 and CKE0 bits in the serial control register SCSCR1 In GSM mode the pulse width is guaranteed when SCK start stop specifications are made by CKE1 and CKE0 Bit 7 GM Description 0 Normal smart card interface mode operation Initial value The TEND flag is...

Page 758: ...0 Clock Enable 1 and 0 CKE1 CKE0 These bits specify the function of the SCK pin In smart card interface mode an internal clock is always used as the clock source In smart card interface mode it is possible to specify a fixed high level or fixed low level for the clock output in addition to the usual switching between enabling and disabling of the clock output GM CKE1 CKE0 SCK Pin Function 0 0 0 Po...

Page 759: ...it 4 indicates the status of the error signal sent back from the receiving side during transmission Framing errors are not detected in smart card interface mode Bit 4 ERS Description 0 Normal reception no error signal Initial value Clearing conditions Power on reset manual reset standby mode or module standby When 0 is written to ERS after reading ERS 1 1 An error signal has been sent from the rec...

Page 760: ...er transmission of a 1 byte serial character etu Elementary Time Unit time for transfer for 1 bit Bits 1 and 0 Reserved Not used with the smart card interface 17 3 Operation 17 3 1 Overview The main functions of the smart card interface are as follows One frame consists of 8 bit data plus a parity bit In transmission a guard time of at least 2 etu elementary time unit the time for transfer of one ...

Page 761: ...ock generated on the smart card interface is used by an IC card the SCK pin output is input to the CLK pin of the IC card No connection is needed if the IC card uses an internal clock Chip port output is used as the reset signal Other pins must normally be connected to the power supply or ground Note If an IC card is not connected and both TE and RE are set to 1 closed transmission reception is po...

Page 762: ...ransmitting station output Transmitting station output Receiving station output Figure 17 3 Smart Card Interface Data Format The operation sequence is as follows 1 When the data line is not in use it is in the high impedance state and is fixed high with a pull up resistor 2 The transmitting station starts transmission of one frame of data The data frame starts with a start bit Ds low level followe...

Page 763: ...ting of other bits is described below Table 17 3 Smart Card Interface Register Settings Bit Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SCSMR1 GM 0 1 O E 1 0 CKS1 CKS0 SCBRR1 BRR7 BRR6 BRR5 BRR4 BRR3 BRR2 BRR1 BRR0 SCSCR1 TIE RIE TE RE 0 0 CKE1 CKE0 SCTDR1 TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0 SCSSR1 TDRE RDRF ORER FER ERS PER TEND 0 0 SCRDR1 RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 RDR1 RDR0 ...

Page 764: ...verse convention type The SMIF bit is set to 1 when the smart card interface is used Figure 17 5 shows examples of register settings and the waveform of the start character for the two types of IC card direct convention and inverse convention With the direct convention type the logic 1 level corresponds to state Z and the logic 0 level to state A and transfer is performed in LSB first order The st...

Page 765: ...t card interface The bit rate is set with the bit rate register SCBRR1 and the CKS1 and CKS0 bits in the serial mode register SCSMR1 The equation for calculating the bit rate is shown below Table 17 5 shows some sample bit rates If clock output is selected with CKE0 set to 1 a clock with a frequency of 372 times the bit rate is output from the SCK pin B 106 1488 22n 1 N 1 φ P Where N Value set in ...

Page 766: ...heral module operating frequency and bit rate is shown below Here N is an integer in the range 0 N 255 and the smaller error is specified N 106 1 1488 22n 1 B φ P Table 17 6 Examples of SCBRR1 Settings for Bit Rate B bits s When n 0 Pφ φ φ φ MHz 7 1424 10 00 10 7136 14 2848 25 00 33 00 50 00 Bits s N Error N Error N Error N Error N Error N Error N Error 9600 0 0 00 1 30 00 1 25 00 1 8 99 3 14 27 4...

Page 767: ...TR1 1 0 0 1 SCK serial clock output state 2 2 1 1 0 0 Low output Low level output state 1 1 0 1 SCK serial clock output state 3 2 1 1 1 0 High output High level output state 1 1 1 1 SCK serial clock output state Notes 1 The SCK output state changes as soon as the CKE0 bit setting is changed Clear the CKE1 bit to 0 2 Stopping and starting the clock by changing the CKE0 bit setting does not affect t...

Page 768: ...bit O E and baud rate generator select bits CKS1 and CKS0 in the serial mode register SCSMR1 Clear the CHR and MP bits to 0 and set the STOP and PE bits to 1 4 Set the SMIF SDIR and SINV bits in the smart card mode register SCSCMR1 When the SMIF bit is set to 1 the TxD pin and RxD pin both go to the high impedance state 5 Set the value corresponding to the bit rate in the bit rate register SCBRR1 ...

Page 769: ...set parity in O bit clock in CKS1 and CKS0 bits and set GM Set SMIF SDIR and SINV bits in SCSCMR1 Set value in SCBRR1 In SCSCR1 set clock in CKE1 and CKE0 bits and clear TIE RIE TE RE MPIE and TEIE bits to 0 1 bit interval elapsed Set TIE RIE TE and RE bits in SCSCR1 End Wait No Yes 1 2 3 4 5 6 7 Figure 17 7 Sample Initialization Flowchart ...

Page 770: ...set to 1 4 Write the transmit data to SCTDR1 clear the TDRE flag to 0 and perform the transmit operation The TEND flag is cleared to 0 5 To continue transmitting data go back to step 2 6 To end transmission clear the TE bit to 0 With the above processing interrupt handling is possible If transmission ends and the TEND flag is set to 1 while the TIE bit is set to 1 and interrupt requests are enable...

Page 771: ...mit data to SCTDR1 and clear TDRE flag in SCSSR1 to 0 FER ERS 0 TEND 1 All data transmitted FER ERS 0 TEND 1 Clear TE bit in SCSCR1 to 0 End of transmission Error handling Error handling No Yes Yes Yes Yes No Yes No No No 1 2 3 4 5 6 Figure 17 8 Sample Transmission Processing Flowchart ...

Page 772: ...4 Read the receive data from SCRDR1 5 To continue receiving data clear the RDRF flag to 0 and go back to step 2 6 To end reception clear the RE bit to 0 With the above processing interrupt handling is possible If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled a receive data full interrupt RXI request will be generated If an error occur...

Page 773: ... When switching from receive mode to transmit mode first confirm that the receive operation has been completed then start from initialization clearing RE to 0 and setting TE to 1 The RDRF flag or the PER and ORER flags can be used to check that the receive operation has been completed When switching from transmit mode to receive mode first confirm that the transmit operation has been completed the...

Page 774: ...the TXI request and transfer of the transmit data will be carried out The TEND flag is automatically cleared to 0 when data transfer is performed by the DMAC In the event of an error the SCI retransmits the same data automatically The TEND flag remains cleared to 0 during this time and the DMAC is not activated Thus the number of bytes specified by the SCI and DMAC are transmitted automatically in...

Page 775: ...ceive data is latched at the rising edge of the 186th base clock pulse The timing is shown in figure 17 10 0 185 371 0 185 371 0 Base clock 372 clocks 186 clocks Start bit D0 D1 Receive data RxD Synchronization sampling timing Data sampling timing Figure 17 10 Receive Data Sampling Timing in Smart Card Mode The receive margin in smart card mode can therefore be expressed as shown in the following ...

Page 776: ...SCSSR1 should be cleared to 0 before the next parity bit is sampled 2 The RDRF bit in SCSSR1 is not set for a frame in which an error has occurred 3 If an error is found when the received parity bit is checked the PER bit in SCSSR1 is not set to 1 4 If no error is found when the received parity bit is checked the receive operation is judged to have been completed normally and the RDRF bit in SCSSR...

Page 777: ...ch an error signal indicating an error is received 3 If an error signal is not sent back from the receiving side the FER ERS bit in SCSSR1 is not set 4 If an error signal is not sent back from the receiving side transmission of one frame including a retransfer is judged to have been completed and the TEND bit in SCSSR1 is set to 1 If the TIE bit in SCSCR1 is enabled at this time a TXI interrupt re...

Page 778: ...Write 0 to the CKE0 bit in SCSCR1 to stop the clock 4 Wait for one serial clock cycle During this period the duty cycle is preserved and clock output is fixed at the specified level 5 Write H 00 to the serial mode register SCSMR1 and smart card mode register SCSMR1 6 Make the transition to the standby state Returning from Standby Mode to Smart Card Interface Mode 7 Clear the standby state 8 Set th...

Page 779: ...al state is port input and high impedance Use pull up or pull down resistors to fix the potential 2 Fix at the output specified by the CKE1 bit in the serial control register SCSCR1 3 Set the serial mode register SCSMR1 and smart card mode register SCSCMR1 and switch to smart card mode operation 4 Set the CKE0 bit in SCSCR1 to 1 to start clock output ...

Page 780: ...Rev 6 0 07 02 page 730 of 986 ...

Page 781: ...be output when the I O port is designated for output and SCI enabling has not been set This allows break function transmission The RxD pin value can be read at all times allowing break state detection SCK pin control is possible when the I O port is designated for output and SCI enabling has not been set The SCK pin value can be read at all times The features of the SCIF I O port are as follows Da...

Page 782: ... D Q C 0 1 0 1 MPX MPX MPX PTIRENn BCK C Q D Pull up resistor Port 15 input output D47 to Port 0 input output D32 Dn output data Internal bus Dn input data Interrupt controller PORTEN 0 Port not available 1 Port available PBnPuP 0 Pull up 1 Pull up off DnDIR 0 Input 1 Output PBnIO 0 Input 1 Output PTIRENn 0 Interrupt input disabled 1 Interrupt input enabled Figure 18 1 16 Bit Port ...

Page 783: ...IO 0 1 PDTRW BCK D Q C 0 1 0 1 BCK C Q D MPX MPX MPX Data input strobe Pull up resistor Port 19 input output D51 to Port 16 input output D48 Dn output data Internal bus PORTEN 0 Port not available 1 Port available PBnPuP 0 Pull up 1 Pull up off DnDIR 0 Input 1 Output PBnIO 0 Input 1 Output Dn input data Figure 18 2 4 Bit Port ...

Page 784: ... C SPTRR Clock output enable signal Serial clock output signal Serial clock input signal Clock input enable signal MD0 SCK Mode setting register SPTRW Write to SPTR SPTRR Read SPTR Note Signals that set the SCK pin function as internal clock output or external clock input according to the CKE0 and CKE1 bits in SCSCR1 and the C bit in SCSMR1 Figure 18 3 MD0 SCK Pin ...

Page 785: ...PTRW SCI R Q D SPB0IO C Reset SPTRW R Q D SPB0DT C MD7 TxD Mode setting register Transmit enable signal Serial transmit data SPTRW Write to SPTR Figure 18 4 MD7 TxD Pin Internal data bus SCI RxD SPTRR Serial receive data SPTRR Read SPTR Figure 18 5 RxD Pin ...

Page 786: ...nal data bus SPTRW Mode setting register SCIF R Q D SPB2IO C Reset SPTRW R Q D SPB2DT C MD1 TxD2 SPTRW Write to SPTR Transmit enable signal Serial transmit data Figure 18 6 MD1 TxD2 Pin Internal data bus Mode setting register SCIF MD2 RxD2 SPTRR Serial receive data SPTRR Read SPTR Figure 18 7 MD2 RxD2 Pin ...

Page 787: ...a bus SPTRW SCIF R Q D CTSIO C Reset SPTRR SPTRW R Q D CTSDT C SPTRW Write to SPTR SPTRR Read SPTR Note MCE bit in SCFCR2 signal that designates modem control as the pin function Modem control enable signal signal Figure 18 8 CTS2 CTS2 CTS2 CTS2 Pin ...

Page 788: ...F R Q D RTSIO C Reset Mode setting register SPTRR SPTRW R Q D RTSDT C MD8 SPTRW Write to SPTR SPTRR Read SPTR Note MCE bit in SCFCR2 signal that designates modem control as the pin function Modem control enable signal signal Figure 18 9 MD8 RTS2 RTS2 RTS2 RTS2 Pin ...

Page 789: ...GPIO interrupt Port 11 pin PORT11 D43 I O I O port GPIO interrupt Port 10 pin PORT10 D42 I O I O port GPIO interrupt Port 9 pin PORT9 D41 I O I O port GPIO interrupt Port 8 pin PORT8 D40 I O I O port GPIO interrupt Port 7 pin PORT7 D39 I O I O port GPIO interrupt Port 6 pin PORT6 D38 I O I O port GPIO interrupt Port 5 pin PORT5 D37 I O I O port GPIO interrupt Port 4 pin PORT4 D36 I O I O port GPIO...

Page 790: ... s SCSPTR1 register Table 18 3 shows the SCIF I O port pin configuration Table 18 3 SCIF I O Port Pins Pin Name Abbreviation I O Function Serial clock pin MRESET SCK2 Input Clock input Receive data pin MD2 RxD2 Input Receive data input Transmit data pin MD1 TxD2 Output Transmit data output Modem control pin CTS2 I O Transmission enabled Modem control pin MD8 RTS2 I O Transmission request Note The ...

Page 791: ... PCTRA R W H 00000000 H FF80002C H 1F80002C 32 Port data register A PDTRA R W Undefined H FF800030 H 1F800030 16 Port control register B PCTRB R W H 00000000 H FF800040 H 1F800040 32 Port data register B PDTRB R W Undefined H FF800044 H 1F800044 16 GPIO interrupt control register GPIOIC R W H 00000000 H FF800048 H 1F800048 16 Serial port register SCSPTR1 R W Undefined H FFE0001C H 1FE0001C 8 Seria...

Page 792: ... a power on reset It is not initialized by a manual reset or in standby mode and retains its contents Bit 31 30 29 28 27 26 25 24 PB15PUP PB15IO PB14PUP PB14IO PB13PUP PB13IO PB12PUP PB12IO Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 23 22 21 20 19 18 17 16 PB11PUP PB11IO PB10PUP PB10IO PB9PUP PB9IO PB8PUP PB8IO Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R ...

Page 793: ...Port Data Register A PDTRA Port data register A PDTRA is a 16 bit readable writable register used as a data latch for each bit in the 16 bit port When a bit is set as an output the value written to the PDTRA register is output from the external pin When a value is read from the PDTRA register while a bit is set as an input the external pin value sampled on the external bus clock is read When a bit...

Page 794: ...tains its contents Bit 31 30 29 28 27 26 25 24 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Bit 23 22 21 20 19 18 17 16 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Bit 15 14 13 12 11 10 9 8 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Bit 7 6 5 4 3 2 1 0 PB19PUP PB19IO PB18PUP PB18IO PB17PUP PB17IO PB16PUP PB16IO Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit...

Page 795: ...utput the value written to the PDTRB register is read PDTRB is not initialized by a power on or manual reset or in standby mode and retains its contents Bit 15 14 13 12 11 10 9 8 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Bit 7 6 5 4 3 2 1 0 PB19DT PB18DT PB17DT PB16DT Initial value 0 0 0 0 R W R R R R R W R W R W R W 18 2 5 GPIO Interrupt Control Register GPIOIC The GPIO interrupt control ...

Page 796: ...O SPB1DT SPB0IO SPB0DT Initial value 0 0 0 0 0 0 R W R W R W R W R W R W The serial port register SCSPTR1 is an 8 bit readable writable register that controls input output and data for the port pins multiplexed with the serial communication interface SCI pins Input data can be read from the RxD pin output data written to the TxD pin and breaks in serial transmission reception controlled by means o...

Page 797: ... reset is undefined Bit 2 SPB1DT Description 0 Input output data is low level 1 Input output data is high level Bit 1 Serial Port Break I O SPB0IO Specifies the serial port TxD pin output condition When the TxD pin is actually set as a port output pin and outputs the value set by the SPB0DT bit the TE bit in SCSCR1 should be cleared to 0 Bit 1 SPB0IO Description 0 SPB0DT bit value is not output to...

Page 798: ...ta writing can be performed by means of bits 5 and 4 and RTS2 pin data reading and output data writing by means of bits 7 and 6 SCSPTR2 can be read or written to by the CPU at all times All SCSPTR2 bits except bits 6 4 and 0 are initialized to 0 by a power on reset or manual reset the value of bits 6 4 and 0 is undefined SCSPTR2 is not initialized in standby mode or in the module standby state Bit...

Page 799: ... CTS2 pin Initial value 1 CTSDT bit value is output to the CTS2 pin Bit 4 Serial Port CTS Port Data CTSDT Specifies the serial port CTS2 pin input output data Input or output is specified by the CTSIO pin see the description of bit 5 CTSIO for details When the CTS2 pin is designated as an output the value of the CTSDT bit is output to the CTS2 pin The CTS2 pin value is read from the CTSDT bit rega...

Page 800: ...he description of bit 1 SPB2IO for details When the TxD2 pin is designated as an output the value of the SPB2DT bit is output to the TxD2 pin The RxD2 pin value is read from the SPB2DT bit regardless of the value of the SPB2IO bit The initial value of this bit after a power on reset or manual reset is undefined Bit 0 SPB2DT Description 0 Input output data is low level 1 Input output data is high l...

Page 801: ...ity levels can be set By setting the three interrupt priority registers the priorities of on chip peripheral module interrupts can be selected from 15 levels for different request sources NMI noise canceler function The NMI input level bit indicates the NMI pin state The pin state can be checked by reading this bit in the interrupt exception service routine enabling it to be used as a noise cancel...

Page 802: ... registers A D 1 INTPRI00 Interrupt priority level setting register 00 2 SR Status register Notes 1 IPRD is provided only in the SH7750S and SH7750R 2 INTPRI00 is provided only in the SH7750R NMI Input control TMU RTC SCI SCIF WDT REF DMAC H UDI GPIO Priority identifier 4 4 Interrupt request Com parator Bus interface Internal bus ICR IPRA IPRD 1 INTPRI00 2 Interrupt request Interrupt request Inter...

Page 803: ... 16 Interrupt priority register A IPRA R W H 0000 H FFD00004 H 1FD00004 16 Interrupt priority register B IPRB R W H 0000 H FFD00008 H 1FD00008 16 Interrupt priority register C IPRC R W H 0000 H FFD0000C H 1FD0000C 16 Interrupt priority register D 3 IPRD R W H DA74 H FFD00010 H 1FD00010 16 Interrupt priority level setting register 00 4 INTPRI00 R W H 00000000 H FE080000 H 1E080000 32 Interrupt sour...

Page 804: ...n the status register in the CPU is set to 1 In sleep or standby mode the interrupt is accepted even if the BL bit is set to 1 A setting can also be made to have the NMI interrupt accepted even if the BL bit is set to 1 Input from the NMI pin is edge detected The NMI edge select bit NMIE in the interrupt control register ICR is used to select either rising or falling edge When the NMIE bit in the ...

Page 805: ...s the level indicated by pins IRL3 IRL0 An IRL3 IRL0 value of 0 0000 indicates the highest level interrupt request interrupt priority level 15 A value of 15 1111 indicates no interrupt request interrupt priority level 0 Interrupt requests Priority encoder to 4 SH7750 Series to Figure 19 2 Example of IRL Interrupt Connection ...

Page 806: ...vels sampled at every bus clock cycle remain unchanged for three consecutive cycles so that no transient level on the IRL pin change is detected In standby mode as the bus clock is stopped noise cancellation is performed using the 32 768 kHz clock for the RTC instead When the RTC is not used therefore interruption by means of IRL interrupts cannot be performed in standby mode The priority level of...

Page 807: ...r INTEVT so it is easy to identify sources by using the INTEVT register value as a branch offset in the exception handling routine A priority level from 15 to 0 can be set for each module by means of interrupt priority registers A to D IPRA IPRD 00 INTPRI00 The interrupt mask bits I3 I0 in the status register SR are not affected by on chip peripheral module interrupt handling On chip peripheral mo...

Page 808: ...s why for instance the value of INTEVT is used as an offset at the start of the interrupt handler and branched to in order to identify the interrupt source The order of priority of the on chip peripheral modules is specified as desired by setting priority levels from 0 to 15 in interrupt priority registers A to D IPRA IPRD The order of priority of the on chip peripheral modules is set to 0 by a re...

Page 809: ...11 IRL3 IRL0 5 H 2A0 10 IRL3 IRL0 6 H 2C0 9 IRL3 IRL0 7 H 2E0 8 IRL3 IRL0 8 H 300 7 IRL3 IRL0 9 H 320 6 IRL3 IRL0 A H 340 5 IRL3 IRL0 B H 360 4 IRL3 IRL0 C H 380 3 IRL3 IRL0 D H 3A0 2 IRL3 IRL0 E H 3C0 1 IRL0 H 240 15 0 13 1 IPRD 15 12 1 IRL1 H 2A0 15 0 10 1 IPRD 11 8 1 IRL2 H 300 15 0 7 1 IPRD 7 4 1 IRL3 H 360 15 0 4 1 IPRD 3 0 1 H UDI H UDI H 600 15 0 0 IPRC 3 0 GPIO GPIOI H 620 15 0 0 IPRC 15 1...

Page 810: ...0 IPRA 3 0 PRI H 4A0 CUI H 4C0 High Low SCI1 ERI H 4E0 15 0 0 IPRB 7 4 High RXI H 500 TXI H 520 TEI H 540 Low SCIF ERI H 700 15 0 0 IPRC 7 4 High RXI H 720 BRI H 740 TXI H 760 Low WDT ITI H 560 15 0 0 IPRB 15 12 REF RCMI H 580 15 0 0 IPRB 11 8 High High ROVI H 5A0 Low Low Notes TUNI0 TUNI4 Underflow interrupts TICPI2 Input capture interrupt ATI Alarm interrupt PRI Periodic interrupt CUI Carry up i...

Page 811: ... are 16 bit readable writable registers that set priority levels from 0 to 15 for on chip peripheral module interrupts IPRA to IPRC are initialized to H 0000 and IPRD is to H DA74 by a reset They are not initialized in standby mode IPRA to IPRC Bit 15 14 13 12 11 10 9 8 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R...

Page 812: ...able 19 6 four on chip peripheral modules are assigned to each register Interrupt priority levels are established by setting a value from H F 1111 to H 0 0000 in each of the four bit groups 15 12 11 8 7 4 and 3 0 Setting H F designates priority level 15 the highest level and setting H 0 designates priority level 0 requests are masked 19 3 2 Interrupt Control Register ICR The interrupt control regi...

Page 813: ...terrupts are masked and standby is not cleared while the NMI pin is low Bit 9 NMI Block Mode NMIB Specifies whether an NMI request is to be held pending or detected immediately while the SR BL bit is set to 1 Bit 9 NMIB Description 0 NMI interrupt requests held pending while SR BL bit is set to 1 Initial value 1 NMI interrupt requests detected while SR BL bit is set to 1 Notes 1 If interrupt reque...

Page 814: ...ister 00 INTPRI00 SH7750R Only The interrupt priority level setting register 00 INTPRI00 sets the priority levels levels 15 0 for the on chip peripheral module interrupts INTPRI00 is a 32 bit readable writable register It is initialized to H 00000000 by a reset but is not initialized when the device enters standby mode Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value 0 0 0 0 0 0 0...

Page 815: ...ter 00 INTREQ00 SH7750R Only The interrupt source register 00 INTREQ00 indicates the origin of the interrupt request that has been sent to the INTC The states of the bits in this register is not affected by masking of the corresponding interrupts by the settings in the INTPRI00 or INTMSK00 register INTREQ00 is a 32 bit read only register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial ...

Page 816: ...2 21 20 19 18 17 16 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R R R R R R R R R Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 R W R R R R R R W R W R W R W R W R W R W R W R W R W R W Bit 31 to 0 Interrupt Mask Sets the masking of the interrupt request that corresponds to the given bit For the correspondence between bits and interrupt...

Page 817: ...o clear the masking of the interrupt source that corresponds to that bit For the correspondence between the bits and interrupt sources see section 19 3 7 Bit Assignments of INTREQ00 INTMSK00 and INTMSKCLR00 SH7750R Only Bits 31 to 0 Description 0 Masking of interrupt requests from the source that corresponds to the bit is not changed 1 Masking of interrupt requests from the source that corresponds...

Page 818: ...CPU accepts an interrupt at a break between instructions 5 The interrupt source code is set in the interrupt event register INTEVT 6 The status register SR and program counter PC are saved to SSR and SPC respectively The R15 contents at this time are saved in SGR 7 The block bit BL mode bit MD and register bank bit RB in SR are set to 1 8 The CPU jumps to the start address of the interrupt handler...

Page 819: ...e in INTEVT Set BL MD RB bits in SR to 1 Branch to exception handler Interrupt generated BL bit in SR 0 or sleep or standby mode NMI Level 14 interrupt Level 1 interrupt I3 I0 level 13 or lower I3 I0 level 0 Yes Level 15 interrupt I3 I0 level 14 or lower Note I3 I0 Interrupt mask bits in status register SR NMIB in ICR 1 and NMI Figure 19 3 Interrupt Operation Flowchart ...

Page 820: ...RTE instruction When these procedures are followed in order an interrupt of higher priority than the one being handled can be accepted after clearing BL in step 4 This enables the interrupt response time to be shortened for urgent processing 19 4 3 Interrupt Masking with MAI Bit By setting the MAI bit to 1 in the ICR register it is possible to mask interrupts while the NMI pin is low irrespective ...

Page 821: ...cyc 2Bcyc Wait time until end of sequence being executed by CPU S 1 0 Icyc S 1 0 Icyc S 1 0 Icyc Time from interrupt exception handling save of SR and PC until fetch of first instruction of exception handler is started 4 Icyc 4 Icyc 4 Icyc Total 5Icyc 4Bcyc S 1 Icyc 5Icyc 7Bcyc S 1 Icyc 5Icyc 2Bcyc S 1 Icyc Minimum case 13Icyc 19Icyc 9Icyc When Icyc Bcyc 2 1 Response time Maximum case 36 S Icyc 60...

Page 822: ...Rev 6 0 07 02 page 772 of 986 ...

Page 823: ...features Two break channels A and B User break interrupts can be generated on independent conditions for channels A and B or on sequential conditions sequential break setting channel A channel B The following can be set as break compare conditions Address selection of 32 bit virtual address and ASID for comparison Address All bits compared lower 10 bits masked lower 12 bits masked lower 16 bits ma...

Page 824: ...RA BBRB BARB BASRB BAMRB BDRB BDMRB BRCR Control User break trap request BBRA Break bus cycle register A BARA Break address register A BASRA Break ASID register A BAMRA Break address mask register A BBRB Break bus cycle register B BARB Break address register B BASRB Break ASID register B BAMRB Break address mask register B BDRB Break data register B BDMRB Break data mask register B BRCR Break cont...

Page 825: ... Undefined H FF000014 H 1F000014 8 Break address register B BARB R W Undefined H FF20000C H 1F20000C 32 Break address mask register B BAMRB R W Undefined H FF200010 H 1F200010 8 Break bus cycle register B BBRB R W H 0000 H FF200014 H 1F200014 16 Break ASID register B BASRB R W Undefined H FF000018 H 1F000018 8 Break data register B BDRB R W Undefined H FF200018 H 1F200018 32 Break data mask regist...

Page 826: ...uction When a UBC control register is updated use either of the following methods to make the updated value valid 1 Execute an RTE instruction after the memory store instruction that updated the register The updated value will be valid from the RTE instruction jump destination onward 2 Execute instructions requiring 5 states for execution after the memory store instruction that updated the registe...

Page 827: ... BAA14 BAA13 BAA12 BAA11 BAA10 BAA9 BAA8 Initial value R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 BAA7 BAA6 BAA5 BAA4 BAA3 BAA2 BAA1 BAA0 Initial value R W R W R W R W R W R W R W R W R W Note Undefined Break address register A BARA is a 32 bit readable writable register that specifies the virtual address used in the channel A break conditions BARA is not initialized by a power on res...

Page 828: ...k Address Mask Register A BAMRA Bit 7 6 5 4 3 2 1 0 BAMA2 BASMA BAMA1 BAMA0 Initial value 0 0 0 0 R W R R R R R W R W R W R W Note Undefined Break address mask register A BAMRA is an 8 bit readable writable register that specifies which bits are to be masked in the break ASID set in BASRA and the break address set in BARA BAMRA is not initialized by a power on reset or manual reset Bits 7 to 4 Res...

Page 829: ...cluded in break conditions 1 Lower 20 bits of BARA are masked and not included in break conditions 1 Reserved cannot be set Note Don t care 20 2 5 Break Bus Cycle Register A BBRA Bit 15 14 13 12 11 10 9 8 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Bit 7 6 5 4 3 2 1 0 SZA2 IDA1 IDA0 RWA1 RWA0 SZA1 SZA0 Initial value 0 0 0 0 0 0 0 0 R W R R W R W R W R W R W R W R W Break bus cycle register A...

Page 830: ... or write cycle is used as the bus cycle in the channel A break conditions Bit 3 RWA1 Bit 2 RWA0 Description 0 0 Condition comparison is not performed Initial value 1 Read cycle is used as break condition 1 0 Write cycle is used as break condition 1 Read cycle or write cycle is used as break condition Bits 6 1 and 0 Operand Size Select A SZA2 SZA0 These bits select the operand size of the bus cycl...

Page 831: ...25 24 BDB31 BDB30 BDB29 BDB28 BDB27 BDB26 BDB25 BDB24 Initial value R W R W R W R W R W R W R W R W R W Bit 23 22 21 20 19 18 17 16 BDB23 BDB22 BDB21 BDB20 BDB19 BDB18 BDB17 BDB16 Initial value R W R W R W R W R W R W R W R W R W Bit 15 14 13 12 11 10 9 8 BDB15 BDB14 BDB13 BDB12 BDB11 BDB10 BDB9 BDB8 Initial value R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 BDB7 BDB6 BDB5 BDB4 BDB3 BDB...

Page 832: ...BDMB22 BDMB21 BDMB20 BDMB19 BDMB18 BDMB17 BDMB16 Initial value R W R W R W R W R W R W R W R W R W Bit 15 14 13 12 11 10 9 8 BDMB15 BDMB14 BDMB13 BDMB12 BDMB11 BDMB10 BDMB9 BDMB8 Initial value R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 BDMB7 BDMB6 BDMB5 BDMB4 BDMB3 BDMB2 BDMB1 BDMB0 Initial value R W R W R W R W R W R W R W R W R W Note Undefined Break data mask register B BDMRB is a ...

Page 833: ...egister BRCR Bit 15 14 13 12 11 10 9 8 CMFA CMFB PCBA Initial value 0 0 0 0 0 0 0 R W R W R W R R R R W R R Bit 7 6 5 4 3 2 1 0 DBEB PCBB SEQ UBDE Initial value 0 0 0 0 0 R W R W R W R R R W R R R W Note Undefined The break control register BRCR is a 16 bit readable writable register that specifies 1 whether channels A and B are to be used as two independent channels or in a sequential condition 2...

Page 834: ... read as 0 and should only be written with 0 Bit 10 Instruction Access Break Select A PCBA Specifies whether a channel A instruction access cycle break is to be effected before or after the instruction is executed This bit is not initialized by a power on reset or manual reset Bit 10 PCBA Description 0 Channel A PC break is effected before instruction execution 1 Channel A PC break is effected aft...

Page 835: ...e performed as sequential conditions channel A channel B Bits 2 and 1 Reserved These bits are always read as 0 and should only be written with 0 Bit 0 User Break Debug Enable UBDE Specifies whether the user break debug function see section 20 4 User Break Debug Support Function is to be used Bit 0 UBDE Description 0 User break debug function is not used Initial value 1 User break debug function is...

Page 836: ...instruction s after as a measure of the distance between two instructions is defined as follows A branch is counted as an interval of two instructions Example of sequence of instructions with no branch 100 Instruction A 0 instructions after instruction A 102 Instruction B 1 instruction after instruction A 104 Instruction C 2 instructions after instruction A 106 Instruction D 3 instructions after i...

Page 837: ...r the break control register is in the initial state after a reset a break may be generated inadvertently 3 The operation when a break condition is satisfied depends on the BL bit in the CPU s SR register When the BL bit is 0 exception handling is started and the condition match flag CMFA CMFB for the respective channel is set for the matched condition When the BL bit is 1 the condition match flag...

Page 838: ... carried out first The instruction TLB exception handling is performed when the instruction is re executed see section 5 4 Exception Types and Priorities Also since a delayed branch instruction and the delay slot instruction are executed as a single instruction if a pre execution break is specified for a delay slot instruction the break will be effected before execution of the delayed branch instr...

Page 839: ...In this case break data register B BDRB and break data mask register B BDMRB settings are necessary in addition to the address condition A user break interrupt is generated when all three conditions address ASID and data are matched When a quadword access occurs the 64 bit access data is divided into an upper 32 bits and lower 32 bits and interpreted as two 32 bit data units A break is generated i...

Page 840: ...uction access pre execution is set as a break condition the program counter PC value saved to SPC in user break interrupt handling is the address of the instruction at which the break condition match occurred In this case a user break interrupt is generated and the fetched instruction is not executed 2 When instruction access post execution is set as a break condition the program counter PC value ...

Page 841: ...entially cannot be performed by exception 2 cannot be performed is guaranteed irrespective of the existence of exception 1 The program counter value saved is the address of the first instruction for which execution is suppressed Whether exception 1 or exception 2 is used for the exception jump destination and the value written to the exception register EXPEVT INTEVT is not guaranteed However if ex...

Page 842: ...execution instruction access break for the SLEEP instruction 2 Do not make an operand access break setting between 1 and 3 instructions before a SLEEP instruction 3 The value of the BL bit referenced in a user break exception depends on the break setting as follows a Pre execution instruction access break The BL bit value before the executed instruction is referenced b Post execution instruction a...

Page 843: ...ak state is initialized by a channel B condition match For example A A B user break generated B no break generated 7 In the event of contention between a re execution type exception and a post execution break in a multistep instruction the re execution type exception is generated In this case the CMF bit may or may not be set to 1 when the break condition occurs 8 A post execution break is classif...

Page 844: ... VBR vector offset Exception service routine Execute RTE instruction PC SPC SR SSR SGR R15 EXPEVT H 160 TRA TRAPA imm PC DBR Debug program R15 SGR STC instruction Reset exception BRCR UBDE 1 user break exception End of exception operations INTEVT interrupt code EXPEVT exception code Yes No No Yes Hardware operation Figure 20 2 User Break Debug Support Function Flowchart ...

Page 845: ... 000083FE with ASID H 70 Register settings BASRA H 80 BARA H 00037226 BAMRA H 00 BBRA H 0016 BASRB H 70 BARB H 0003722E BAMRB H 00 BBRB H 0016 BDRB H 00000000 BDMRB H 00000000 BRCR H 0008 Conditions set Channel A channel B sequential mode Channel A ASID H 80 address H 00037226 address mask H 00 Bus cycle instruction access pre instruction execution read word Channel B ASID H 70 address H 0003722E ...

Page 846: ...ASRB H 70 BARB H 000ABCDE BAMRB H 02 BBRB H 002A BDRB H 0000A512 BDMRB H 00000000 BRCR H 0080 Conditions set Independent channel A channel B mode Channel A ASID H 80 address H 00123456 address mask H 00 Bus cycle operand access read operand size not included in conditions Channel B ASID H 70 address H 000ABCDE address mask H 02 Data H 0000A512 data mask H 00000000 Bus cycle operand access write wo...

Page 847: ...of STBCR2 Make sure that if an exception or interrupt occurs while performing steps 1 to 5 you do not change the values of these registers in the exception handling routine Do not read or write the following registers while the user break controller clock is stopped BARA BAMRA BBRA BARB BAMRB BBRB BDRB BDMRB and BRCR If these registers are read or written the value cannot be guaranteed 20 6 2 Canc...

Page 848: ...1 2 Initialize BRCR to 0 mov l BRCR R1 mov w R0 R1 3 Dummy read BRCR mov w R1 R0 4 Read STBCR2 then set MSTP5 bit in the read data to 1 and write it back mov l STBCR2 R1 mov b R1 R0 or H 1 R0 mov b R0 R1 5 Twice dummy read STBCR2 mov b R1 R0 mov b R1 R0 Canceling user break controller stopped state 6 Read STBCR2 then clear MSTP5 bit in the read data to 0 and write it back mov l STBCR2 R1 mov b R1 ...

Page 849: ...s TCK TMS TDI TDO TRST and ASEBRK BRKACK The pin functions and serial transfer protocol conform to the JTAG specifications 21 1 2 Block Diagram Figure 21 1 shows a block diagram of the H UDI The TAP test access port controller and control registers are reset independently of the chip reset pin by driving the TRST pin low or setting TMS to 1 and applying TCK for at least five clock cycles The other...

Page 850: ...SDIR SDDRH SDDRL SDBPR SDBSR MUX TCK BRKACK TMS TDI TDO SDINT Interrupt reset etc TAP controller Break control Decoder Shift register Peripheral module bus Note Provided only in the SH7750R Figure 21 1 Block Diagram of H UDI Circuit ...

Page 851: ...ation 2 3 Data input pin TDI Input The data input pin Data is sent to the H UDI circuit by changing this signal in synchronization with TCK Open 1 Data output pin TDO Output The data output pin Data is sent to the H UDI circuit by reading this signal in synchronization with TCK Open Emulator pin ASEBRK BRKACK Input output Dedicated emulator pin Open 1 Notes 1 Pulled up inside the chip When designi...

Page 852: ... Side H UDI Side Name Abbre viation R W P4 Address Area 7 Address Access Size Initial Value 1 R W Access Size Initial Value 1 Instruction register SDIR R H FFF00000 H 1FF00000 16 H FFFF R W 32 H FFFFFFFD Fixed value 2 Data register H SDDR SDDRH R W H FFF00008 H 1FF00008 32 16 Unde fined Data register L SDDRL R W H FFF0000A H 1FF0000A 16 Unde fined Bypass register SDBPR Unde fined R W 1 Interrupt s...

Page 853: ... be possible to read the correct value In this case SDIR should be read twice and then read again if the read values do not match Operation is undefined if a reserved command is set in this register SH7750 SH7750S Bit 15 14 13 12 11 10 9 8 TI3 TI2 TI1 TI0 Initial value 1 1 1 1 1 1 1 1 R W R R R R R R R R Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 R W R R R R R R R R Bits 15 to 12 Test Instr...

Page 854: ... 15 to 8 Test Instruction Bits TI7 TI0 Bit 15 TI7 Bit 14 TI6 Bit 13 TI5 Bit 12 TI4 Bit 11 TI3 Bit 10 TI2 Bit 9 TI1 Bit 8 TI0 Description 0 0 0 0 0 0 0 0 EXTEST 0 0 0 0 0 1 0 0 SAMPLE PRELOAD 0 1 1 0 H UDI reset negate 0 1 1 1 H UDI reset assert 1 0 1 H UDI interrupt 1 1 1 1 1 1 1 1 Bypass mode Initial value Other than above Reserved Bits 7 to 0 Reserved These bits are always read as 1 and should o...

Page 855: ...W R W R W R W R W R W Bit 23 22 21 20 19 18 17 16 Initial value R W R W R W R W R W R W R W R W R W Bit 15 14 13 12 11 10 9 8 Initial value R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Initial value R W R W R W R W R W R W R W R W R W Note Undefined Bits 31 to 0 DR Data These bits store the SDDR value 21 2 3 Bypass Register SDBPR The bypass register SDBPR is a one bit register that cann...

Page 856: ...ed in the Test Logic Reset state of TRST or TAP Bit 15 14 13 12 11 10 9 8 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Bit 7 6 5 4 3 2 1 0 INTREQ Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R W Bits 15 to 1 Reserved These bits are always read as 0 When writing only 0s should be written here Bit 0 Interrupt Request INTREQ Indicates whether or not an interrupt request has been issued by an ...

Page 857: ... MD5 RAS2 IN 294 CTS2 IN 257 D60 OUT 330 MD5 RAS2 CTL 293 CTS2 CTL 256 D51 IN 329 MD5 RAS2 OUT 292 CTS2 OUT 255 D51 CTL 328 MD4 CE2B IN 291 NMI IN 254 D51 OUT 327 MD4 CE2B CTL 290 IRL3 IN 253 D59 IN 326 MD4 CE2B OUT 289 IRL2 IN 252 D59 CTL 325 MD3 CE2A IN 288 IRL1 IN 251 D59 OUT 324 MD3 CE2A CTL 287 IRL0 IN 250 D52 IN 323 MD3 CE2A OUT 286 MD2 RXD2 IN 249 D52 CTL 322 A25 CTL 285 MD1 TXD2 IN 248 D52...

Page 858: ... OUT 216 D29 CTL 177 WE7 CAS7 DQM7 REG OUT 138 A11 CTL 215 D29 OUT 176 WE6 CAS6 DQM6 CTL 137 A11 OUT 214 D18 IN 175 WE6 CAS6 DQM6 OUT 136 A12 CTL 213 D18 CTL 174 WE3 CAS3 DQM3 ICIOWR CTL 135 A12 OUT 212 D18 OUT 173 WE3 CAS3 DQM3 ICIOWR OUT 134 A13 CTL 211 D28 IN 172 WE2 CAS2 DQM2 ICIORD CTL 133 A13 OUT 210 D28 CTL 171 WE2 CAS2 DQM2 ICIORD OUT 132 A14 CTL 209 D28 OUT 170 RD WR CTL 131 A14 OUT 208 D...

Page 859: ...103 D6 OUT 63 D39 IN 23 D46 CTL 102 D9 IN 62 D39 CTL 22 D46 OUT 101 D9 CTL 61 D39 OUT 21 D32 IN 100 D9 OUT 60 D40 IN 20 D32 CTL 99 D5 IN 59 D40 CTL 19 D32 OUT 98 D5 CTL 58 D40 OUT 18 D47 IN 97 D5 OUT 57 D38 IN 17 D47 CTL 96 D10 IN 56 D38 CTL 16 D47 OUT 95 D10 CTL 55 D38 OUT 15 RD2 CTL 94 D10 OUT 54 D41 IN 14 RD2 OUT 93 D4 IN 53 D41 CTL 13 BS CTL 92 D4 CTL 52 D41 OUT 12 BS OUT 91 D4 OUT 51 D37 IN 1...

Page 860: ... edge The TDO value changes at the falling edge of TCK When not in the Shift DR or Shift IR state TDO is in the high impedance state In a transition to TRST 0 a transition is made to the Test Logic Reset state asynchronously with respect to TCK 1 0 0 0 Run Test Idle Select DR Scan Capture DR Shift DR Exit1 DR Pause DR Exit2 DR Update DR Test Logic Reset 0 1 1 1 0 0 1 0 1 1 1 1 0 0 0 0 Select IR Sc...

Page 861: ... interrupt can be controlled with bits 3 to 0 of control register IPRC In the SH7750 or SH7750S the H UDI interrupt request signal is asserted for about eight cycles of the LSI s on chip peripheral clock after the command is set The number of cycles for assertion is determined by the ratio of TCK to the frequency of the on chip peripheral clock Since the period of assertion is limited the CPU may ...

Page 862: ...he EXTAL pin any longer For details on the power on oscillation settling time see section 22 Electrical Characteristics 6 In BYPASS mode of the SH7750 or SH7750S the bypass register SPDBPR is not initialized in the Capture DR state 21 4 Usage Notes 1 SDIR Command Once an SDIR command has been set it remains unchanged until initialization by asserting TRST or placing the TAP in the Test Logic Reset...

Page 863: ... VDD 0 3 to 2 5 0 3 to 2 1 2 V Input voltage Vin 0 3 to VDDQ 0 3 V Operating temperature Topr 20 to 75 40 to 85 1 C Storage temperature Tstg 55 to 125 C Notes Permanent damage to the chip may result if the maximum ratings are exceeded Permanent damage to the chip may result if all VSS pins are not connected to GND For information on the power on and power off procedures refer to appendix H Power O...

Page 864: ...0 mA 400 Ta 25 C 1 Current dissipation Standby mode IDD 800 µA Ta 50 C 1 Normal operation 170 215 Sleep mode 35 40 mA Iφ 240 MHz Bφ 120 MHz 440 Ta 25 C 1 Current dissipation Standby mode IDDQ 880 µA Ta 50 C 1 15 25 RTC on 2 RTC current dissipation Standby mode IDD RTC 3 5 µA RTC off RESET NMI TRST VIH VDDQ 0 9 VDDQ 0 3 V Other input pins 2 0 VDDQ 0 3 RESET NMI TRST VIL 0 3 VDDQ 0 1 Input voltage O...

Page 865: ... and VSS RTC to GND regardless of whether or not the PLL circuits and RTC are used 2 The current dissipation values are for VIH min VDDQ 0 5 V and VIL max 0 5 V with all output pins unloaded 3 IDDQ is the total current value for the 3 3 V versions of VDDQ VDD PLL1 2 VDD RTC and VDD CPG 1 RCR2 RTCEN must be set to 1 to reduce the leak current in the standby mode There is no need to input a clock fr...

Page 866: ...0 Ta 25 C 1 Current dissipation Standby mode IDD 800 µA Ta 50 C 1 Normal operation 140 180 Sleep mode 35 40 mA Iφ 240 MHz Bφ 80 MHz 440 Ta 25 C 1 Current dissipation Standby mode IDDQ 880 µA Ta 50 C 1 15 25 RTC on 2 RTC current dissipation Standby mode IDD RTC 3 5 µA RTC off RESET NMI TRST VIH VDDQ 0 9 VDDQ 0 3 V Other input pins 2 0 VDDQ 0 3 RESET NMI TRST VIL 0 3 VDDQ 0 1 Input voltage Other inp...

Page 867: ...VSSQ RTC to GND regardless of whether or not the PLL circuits and RTC are used 2 The current dissipation values are for VIH min VDDQ 0 5 V and VIL max 0 5 V with all output pins unloaded 3 IDDQ is the total current value for the 3 3 V versions of VDDQ VDD PLL1 2 VDD RTC and VDD CPG 1 RCR2 RTCEN must be set to 1 to reduce the leak current in the standby mode There is no need to input a clock from E...

Page 868: ...00 Ta 25 C 1 Current dissipation Standby mode IDD 800 µA Ta 50 C 1 Normal operation 140 180 Sleep mode 30 35 mA Iφ 200 MHz Bφ 100 MHz 440 Ta 25 C 1 Current dissipation Standby mode IDDQ 880 µA Ta 50 C 1 15 25 RTC on 2 RTC current dissipation Standby mode IDD RTC 3 5 µA RTC off RESET NMI TRST VIH VDDQ 0 9 VDDQ 0 3 V Other input pins 2 0 VDDQ 0 3 RESET NMI TRST VIL 0 3 VDDQ 0 1 Input voltage Other i...

Page 869: ...G VSS PLL1 2 and VSS RTC to GND regardless of whether or not the PLL circuits and RTC are used 2 The current dissipation values are for VIH min VDDQ 0 5 V and VIL max 0 5 V with all output pins unloaded 3 IDDQ is the sum of the VDDQ VDD RTC and VDD CPG 3 3 V system currents 1 RCR2 RTCEN must be set to 1 to reduce the leak current in the standby mode There is no need to input a clock from EXTAL2 2 ...

Page 870: ...00 Ta 25 C 1 Current dissipation Standby mode IDD 800 µA Ta 50 C 1 Normal operation 140 180 Sleep mode 30 35 mA Iφ 200 MHz Bφ 67 MHz 440 Ta 25 C 1 Current dissipation Standby mode IDDQ 880 µA Ta 50 C 1 15 25 RTC on 2 RTC current dissipation Standby mode IDD RTC 3 5 µA RTC off RESET NMI TRST VIH VDDQ 0 9 VDDQ 0 3 V Other input pins 2 0 VDDQ 0 3 RESET NMI TRST VIL 0 3 VDDQ 0 1 Input voltage Other in...

Page 871: ... 2 and VSSQ RTC to GND regardless of whether or not the PLL circuits and RTC are used 2 The current dissipation values are for VIH min VDDQ 0 5 V and VIL max 0 5 V with all output pins unloaded 3 IDDQ is the sum of the VDDQ VDD PLL1 2 VDD RTC and VDD CPG 3 3 V system currents 1 RCR2 RTCEN must be set to 1 to reduce the leak current in the standby mode There is no need to input a clock from EXTAL2 ...

Page 872: ...dissipation Standby mode IDD 5000 µA Ta 50 C RTC on Normal operation 140 180 Sleep mode 40 50 mA Iφ 200 MHz Bφ 100 MHz 2200 Ta 25 C RTC on Current dissipation Standby mode IDDQ 5500 µA Ta 50 C RTC on RTC current dissipation During RTC operation IDD RTC 15 25 µA RTC input clock 32 768 kHz Power is supplied only to VDD RTC RESET NMI TRST VIH VDDQ 0 9 VDDQ 0 3 V Other input pins 2 0 VDDQ 0 3 RESET NM...

Page 873: ... not the PLL circuits and RTC are used 2 The current dissipation values are for VIH min VDDQ 0 5 V and VIL max 0 5 V with all output pins unloaded 3 IDDQ is the sum of the VDDQ VDD PLL1 2 VDD RTC and VDD CPG 3 3 V system currents To reduce the leakage current in standby mode the RTC must be turned on input the clock from EXTAL2 and set RCR2 RTCEN to 1 ...

Page 874: ...dissipation Standby mode IDD 5000 µA Ta 50 C RTC on Normal operation 140 180 Sleep mode 40 50 mA Iφ 200 MHz Bφ 67 MHz 2200 Ta 25 C RTC on Current dissipation Standby mode IDDQ 5500 µA Ta 50 C RTC on RTC current dissipation During RTC operation IDD RTC 15 25 µA RTC input clock 32 768 kHz Power is supplied only to VDD RTC RESET NMI TRST VIH VDDQ 0 9 VDDQ 0 3 V Other input pins 2 0 VDDQ 0 3 RESET NMI...

Page 875: ... not the PLL circuits and RTC are used 2 The current dissipation values are for VIH min VDDQ 0 5 V and VIL max 0 5 V with all output pins unloaded 3 IDDQ is the sum of the VDDQ VDD PLL1 2 VDD RTC and VDD CPG 3 3 V system currents To reduce the leakage current in standby mode the RTC must be turned on input the clock from EXTAL2 and set RCR2 RTCEN to 1 ...

Page 876: ...1200 Sleep mode 165 mA Iφ 200 MHz 2000 Ta 25 C RTC on Current dissipation Standby mode IDD 5000 µA Ta 50 C RTC on Normal operation 160 200 Sleep mode 40 mA Iφ 200 MHz Bφ 100 MHz 2200 Ta 25 C RTC on Current dissipation Standby mode IDDQ 5500 µA Ta 50 C RTC on RESET NMI TRST VIH VDDQ 0 9 VDDQ 0 3 V Other input pins 2 0 VDDQ 0 3 RESET NMI TRST VIL 0 3 VDDQ 0 1 Input voltage Other input pins 0 3 VDDQ ...

Page 877: ... not the PLL circuits and RTC are used 2 The current dissipation values are for VIH min VDDQ 0 5 V and VIL max 0 5 V with all output pins unloaded 3 IDDQ is the sum of the VDDQ VDD PLL1 2 VDD RTC and VDD CPG 3 3 V system currents To reduce the leakage current in standby mode the RTC must be turned on input the clock from EXTAL2 and set RCR2 RTCEN to 1 ...

Page 878: ...pation Standby mode IDD 100 800 µA Ta 50 C RTC on Normal operation 140 180 Sleep mode 40 50 mA Iφ 167 MHz Bφ 84 MHz 110 440 Ta 25 C RTC on Current dissipation Standby mode IDDQ 220 880 µA Ta 50 C RTC on RTC current dissipation During RTC operation IDD RTC 15 45 µA RTC input clock 32 768 kHz Power is supplied only to VDD RTC RESET NMI TRST VIH VDDQ 0 9 VDDQ 0 3 V Other input pins 2 0 VDDQ 0 3 RESET...

Page 879: ... not the PLL circuits and RTC are used 2 The current dissipation values are for VIH min VDDQ 0 5 V and VIL max 0 5 V with all output pins unloaded 3 IDDQ is the sum of the VDDQ VDD PLL1 2 VDD RTC and VDD CPG 3 3 V system currents To reduce the leakage current in standby mode the RTC must be turned on input the clock from EXTAL2 and set RCR2 RTCEN to 1 ...

Page 880: ...ipation Standby mode IDD 100 880 µA Ta 50 C RTC on Normal operation 180 220 Sleep mode 50 65 mA Iφ 167 MHz Bφ 84 MHz 110 440 Ta 25 C RTC on Current dissipation Standby mode IDDQ 220 960 µA Ta 50 C RTC on RTC current dissipation During RTC operation IDD RTC 15 45 µA RTC input clock 32 768 kHz Power is supplied only to VDD RTC RESET NMI TRST VIH VDDQ 0 9 VDDQ 0 3 V Other input pins 2 0 VDDQ 0 3 RESE...

Page 881: ... not the PLL circuits and RTC are used 2 The current dissipation values are for VIH min VDDQ 0 5 V and VIL max 0 5 V with all output pins unloaded 3 IDDQ is the sum of the VDDQ VDD PLL1 2 VDD RTC and VDD CPG 3 3 V system currents To reduce the leakage current in standby mode the RTC must be turned on input the clock from EXTAL2 and set RCR2 RTCEN to 1 ...

Page 882: ... 700 Sleep mode 120 mA Iφ 167 MHz 400 Ta 25 C RTC on Current dissipation Standby mode IDD 800 µA Ta 50 C RTC on Normal operation 160 200 Sleep mode 40 mA Iφ 167 MHz Bφ 84 MHz 440 Ta 25 C RTC on Current dissipation Standby mode IDDQ 880 µA Ta 50 C RTC on RESET NMI TRST VIH VDDQ 0 9 VDDQ 0 3 V Other input pins 2 0 VDDQ 0 3 RESET NMI TRST VIL 0 3 VDDQ 0 1 Input voltage Other input pins 0 3 VDDQ 0 2 V...

Page 883: ... not the PLL circuits and RTC are used 2 The current dissipation values are for VIH min VDDQ 0 5 V and VIL max 0 5 V with all output pins unloaded 3 IDDQ is the sum of the VDDQ VDD PLL1 2 VDD RTC and VDD CPG 3 3 V system currents To reduce the leakage current in standby mode the RTC must be turned on input the clock from EXTAL2 and set RCR2 RTCEN to 1 ...

Page 884: ...eep mode 140 mA Iφ 167 MHz 50 400 Ta 25 C RTC on Current dissipation Standby mode IDD 100 880 µA Ta 50 C RTC on Normal operation 180 220 Sleep mode 50 mA Iφ 167 MHz Bφ 83 MHz 110 440 Ta 25 C RTC on Current dissipation Standby mode IDDQ 220 960 µA Ta 50 C RTC on RESET NMI TRST VIH VDDQ 0 9 VDDQ 0 3 V Other input pins 2 0 VDDQ 0 3 RESET NMI TRST VIL 0 3 VDDQ 0 1 Input voltage Other input pins 0 3 VD...

Page 885: ... not the PLL circuits and RTC are used 2 The current dissipation values are for VIH min VDDQ 0 5 V and VIL max 0 5 V with all output pins unloaded 3 IDDQ is the sum of the VDDQ VDD PLL1 2 VDD RTC and VDD CPG 3 3 V system currents To reduce the leakage current in standby mode the RTC must be turned on input the clock from EXTAL2 and set RCR2 RTCEN to 1 ...

Page 886: ...rent dissipation Standby mode IDD 200 µA Ta 50 C RTC on Normal operation 80 160 Sleep mode 35 40 mA Iφ 133 MHz Bφ 67 MHz 110 Ta 25 C RTC on Current dissipation Standby mode IDDQ 220 µA Ta 50 C RTC on RTC current dissipation During RTC operation IDD RTC 15 25 µA RTC input clock 32 768 kHz Power is supplied only to VDD RTC RESET NMI TRST VIH VDDQ 0 9 VDDQ 0 3 V Other input pins 2 0 VDDQ 0 3 RESET NM...

Page 887: ... not the PLL circuits and RTC are used 2 The current dissipation values are for VIH min VDDQ 0 5 V and VIL max 0 5 V with all output pins unloaded 3 IDDQ is the sum of the VDDQ VDD PLL1 2 VDD RTC and VDD CPG 3 3 V system currents To reduce the leakage current in standby mode the RTC must be turned on input the clock from EXTAL2 and set RCR2 RTCEN to 1 ...

Page 888: ...rrent dissipation Standby mode IDD 200 µA Ta 50 C RTC on Normal operation 80 160 Sleep mode 35 40 mA Iφ 133 MHz Bφ 67 MHz 110 Ta 25 C RTC on Current dissipation Standby mode IDDQ 220 µA Ta 50 C RTC on RTC current dissipation During RTC operation IDD RTC 15 45 µA RTC input clock 32 768 kHz Power is supplied only to VDD RTC RESET NMI TRST VIH VDDQ 0 9 VDDQ 0 3 V Other input pins 2 0 VDDQ 0 3 RESET N...

Page 889: ... not the PLL circuits and RTC are used 2 The current dissipation values are for VIH min VDDQ 0 5 V and VIL max 0 5 V with all output pins unloaded 3 IDDQ is the sum of the VDDQ VDD PLL1 2 VDD RTC and VDD CPG 3 3 V system currents To reduce the leakage current in standby mode the RTC must be turned on input the clock from EXTAL2 and set RCR2 RTCEN to 1 ...

Page 890: ... Sleep mode 60 mA Iφ 128 MHz Bφ 64 MHz 100 Ta 25 C RTC on Current dissipation Standby mode IDD 200 µA Ta 50 C RTC on Normal operation 160 Sleep mode 40 mA Iφ 128 MHz Bφ 64 MHz 110 Ta 25 C RTC on Current dissipation Standby mode IDDQ 220 µA Ta 50 C RTC on RESET NMI TRST VIH VDDQ 0 9 VDDQ 0 3 V Other input pins 2 0 VDDQ 0 3 RESET NMI TRST VIL 0 3 VDDQ 0 1 Input voltage Other input pins 0 3 VDDQ 0 2 ...

Page 891: ...D PLL1 2 VDD RTC and VDD CPG 3 3 V system currents To reduce the leakage current in standby mode the RTC must be turned on input the clock from EXTAL2 and set RCR2 RTCEN to 1 Table 22 16 Permissible Output Currents Ta 20 to 75 C Item Symbol Min Typ Max Unit Permissible output low current per pin IOL 2 mA Permissible output low current total ΣIOL 120 Permissible output high current per pin IOH 2 Pe...

Page 892: ...l Min Typ Max Unit CPU FPU cache TLB 1 240 External bus 1 84 Operating frequency Peripheral modules f 1 60 MHz Table 22 19 Clock Timing HD6417750BP200M HD6417750SBP200 HD6417750RBP200 Item Symbol Min Typ Max Unit CPU FPU cache TLB 1 200 External bus 1 100 Operating frequency Peripheral modules f 1 50 MHz Table 22 20 Clock Timing HD6417750RF200 Item Symbol Min Typ Max Unit CPU FPU cache TLB 1 200 E...

Page 893: ... Operating frequency Peripheral modules 1 42 MHz Table 22 23 Clock Timing HD6417750SVF133 HD6417750SVBT133 Item Symbol Min Typ Max Unit CPU FPU cache TLB 1 134 External bus 1 67 Operating frequency Peripheral modules f 1 34 MHz Table 22 24 Clock Timing HD6417750VF128 Item Symbol Min Typ Max Unit CPU FPU cache TLB 1 128 External bus 1 64 Operating frequency Peripheral modules f 1 32 MHz ...

Page 894: ...ut cycle time tcyc 8 3 1000 ns 22 2 1 CKIO clock output low level pulse width tCKOL1 1 ns 22 2 1 CKIO clock output high level pulse width tCKOH1 1 ns 22 2 1 CKIO clock output rise time tCKOr 3 ns 22 2 1 CKIO clock output fall time tCKOf 3 ns 22 2 1 CKIO clock output low level pulse width tCKOL2 3 ns 22 2 2 CKIO clock output high level pulse width tCKOH2 3 ns 22 2 2 Power on oscillation settling ti...

Page 895: ...mination time RTC used standby mode tIRLSTB 200 µs 22 10 TRST reset hold time tTRSTRH 0 ns 22 3 22 5 Notes 1 When a crystal resonator is connected to EXTAL and XTAL the maximum frequency is 34 MHz When a 3rd overtone crystal resonator is used an external tank circuit is necessary 2 The maximum load capacitance to be connected to CKIO pin should be 50 pF in PLL2 operation because there is a feedbac...

Page 896: ...output low level pulse width tCKOL1 1 ns 22 2 1 CKIO clock output high level pulse width tCKOH1 1 ns 22 2 1 CKIO clock output rise time tCKOr 3 ns 22 2 1 CKIO clock output fall time tCKOf 3 ns 22 2 1 CKIO clock output low level pulse width tCKOL2 3 ns 22 2 2 CKIO clock output high level pulse width tCKOH2 3 ns 22 2 2 Power on oscillation settling time tOSC1 10 ms 22 3 22 5 Power on oscillation set...

Page 897: ... mode tIRLSTB 200 µs 22 10 TRST reset hold time tTRSTRH 0 ns 22 3 22 5 Notes 1 When a crystal resonator is connected to EXTAL and XTAL the maximum frequency is 34 MHz When a 3rd overtone crystal resonator is used an external tank circuit is necessary 2 The maximum load capacitance to be connected to CKIO pin should be 50 pF in PLL2 operation because there is a feedback from CKIO pin When the oscil...

Page 898: ...output low level pulse width tCKOL1 1 ns 22 2 1 CKIO clock output high level pulse width tCKOH1 1 ns 22 2 1 CKIO clock output rise time tCKOr 3 ns 22 2 1 CKIO clock output fall time tCKOf 3 ns 22 2 1 CKIO clock output low level pulse width tCKOL2 3 ns 22 2 2 CKIO clock output high level pulse width tCKOH2 3 ns 22 2 2 Power on oscillation settling time tOSC1 10 ms 22 3 22 5 Power on oscillation set...

Page 899: ... mode tIRLSTB 200 µs 22 10 TRST reset hold time tTRSTRH 0 ns 22 3 22 5 Notes 1 When a crystal resonator is connected to EXTAL and XTAL the maximum frequency is 34 MHz When a 3rd overtone crystal resonator is used an external tank circuit is necessary 2 The maximum load capacitance to be connected to CKIO pin should be 50 pF in PLL2 operation because there is a feedback from CKIO pin When the oscil...

Page 900: ...output low level pulse width tCKOL1 1 ns 22 2 1 CKIO clock output high level pulse width tCKOH1 1 ns 22 2 1 CKIO clock output rise time tCKOr 3 ns 22 2 1 CKIO clock output fall time tCKOf 3 ns 22 2 1 CKIO clock output low level pulse width tCKOL2 3 ns 22 2 2 CKIO clock output high level pulse width tCKOH2 3 ns 22 2 2 Power on oscillation settling time tOSC1 10 ms 22 3 22 5 Power on oscillation set...

Page 901: ... mode tIRLSTB 200 µs 22 10 TRST reset hold time tTRSTRH 0 ns 22 3 22 5 Notes 1 When a crystal resonator is connected to EXTAL and XTAL the maximum frequency is 34 MHz When a 3rd overtone crystal resonator is used an external tank circuit is necessary 2 The maximum load capacitance to be connected to CKIO pin should be 50 pF in PLL2 operation because there is a feedback from CKIO pin When the oscil...

Page 902: ... 100 MHz CKIO clock output PLL2 not operating fOP 1 100 MHz CKIO clock output cycle time tcyc 10 1000 ns 22 2 1 CKIO clock output low level pulse width tCKOL1 1 ns 22 2 1 CKIO clock output high level pulse width tCKOH1 1 ns 22 2 1 CKIO clock output rise time tCKOr 3 ns 22 2 1 CKIO clock output fall time tCKOf 3 ns 22 2 1 CKIO clock output low level pulse width tCKOL2 3 ns 22 2 2 CKIO clock output ...

Page 903: ...urn oscillation settling time 3 tOSC4 2 ms IRL interrupt determination time RTC used standby mode tIRLSTB 200 µs 22 10 TRST reset hold time tTRSTRH 0 ns 22 3 22 5 Notes 1 When a crystal resonator is connected to EXTAL and XTAL the maximum frequency is 34 MHz When a 3rd overtone crystal resonator is used an external tank circuit is necessary 2 The maximum load capacitance to be connected to CKIO pi...

Page 904: ...CKIO clock output PLL2 not operating fOP 1 67 MHz CKIO clock output cycle time tcyc 10 1000 ns 22 2 1 CKIO clock output low level pulse width tCKOL1 1 ns 22 2 1 CKIO clock output high level pulse width tCKOH1 1 ns 22 2 1 CKIO clock output rise time tCKOr 3 ns 22 2 1 CKIO clock output fall time tCKOf 3 ns 22 2 1 CKIO clock output low level pulse width tCKOL2 3 ns 22 2 2 CKIO clock output high level...

Page 905: ...urn oscillation settling time 3 tOSC4 2 ms IRL interrupt determination time RTC used standby mode tIRLSTB 200 µs 22 10 TRST reset hold time tTRSTRH 0 ns 22 3 22 5 Notes 1 When a crystal resonator is connected to EXTAL and XTAL the maximum frequency is 34 MHz When a 3rd overtone crystal resonator is used an external tank circuit is necessary 2 The maximum load capacitance to be connected to CKIO pi...

Page 906: ...dth tEXH 3 5 ns 22 1 EXTAL clock input rise time tEXr 4 ns 22 1 EXTAL clock input fall time tEXf 4 ns 22 1 PLL2 operating fOP 25 84 MHz CKIO clock output PLL2 not operating fOP 1 84 MHz CKIO clock output cycle time tcyc 12 1000 ns 22 2 1 CKIO clock output low level pulse width tCKOL1 1 ns 22 2 1 CKIO clock output high level pulse width tCKOH1 1 ns 22 2 1 CKIO clock output rise time tCKOr 3 ns 22 2...

Page 907: ...return oscillation settling time 2 tOSC3 2 ms Standby return oscillation settling time 3 tOSC4 2 ms IRL interrupt determination time RTC used standby mode tIRLSTB 200 µs 22 10 TRST reset hold time tTRSTRH 0 ns 22 3 22 5 Notes 1 When a crystal resonator is connected to EXTAL and XTAL the maximum frequency is 28 MHz When a 3rd overtone crystal resonator is used an external tank circuit is necessary ...

Page 908: ...all time tEXf 4 ns 22 1 PLL2 operating fOP 25 67 MHz CKIO clock output PLL2 not operating fOP 1 67 MHz CKIO clock output cycle time tcyc 14 1000 ns 22 2 1 CKIO clock output low level pulse width tCKOL1 1 ns 22 2 1 CKIO clock output high level pulse width tCKOH1 1 ns 22 2 1 CKIO clock output rise time tCKOr 3 ns 22 2 1 CKIO clock output fall time tCKOf 3 ns 22 2 1 CKIO clock output low level pulse ...

Page 909: ...urn oscillation settling time 3 tOSC4 2 ms IRL interrupt determination time RTC used standby mode tIRLSTB 200 µs 22 10 TRST reset hold time tTRSTRH 0 ns 22 3 22 5 Notes 1 When a crystal resonator is connected to EXTAL and XTAL the maximum frequency is 23 MHz When a 3rd overtone crystal resonator is used an external tank circuit is necessary 2 The maximum load capacitance to be connected to CKIO pi...

Page 910: ...CKIO clock output PLL2 not operating fOP 1 64 MHz CKIO clock output cycle time tcyc 15 1000 ns 22 2 1 CKIO clock output low level pulse width tCKOL1 1 ns 22 2 1 CKIO clock output high level pulse width tCKOH1 1 ns 22 2 1 CKIO clock output rise time tCKOr 3 ns 22 2 1 CKIO clock output fall time tCKOf 3 ns 22 2 1 CKIO clock output low level pulse width tCKOL2 3 ns 22 2 2 CKIO clock output high level...

Page 911: ...urn oscillation settling time 3 tOSC4 2 ms IRL interrupt determination time RTC used standby mode tIRLSTB 200 µs 22 10 TRST reset hold time tTRSTRH 0 ns 22 3 22 5 Notes 1 When a crystal resonator is connected to EXTAL and XTAL the maximum frequency is 22 MHz When a 3rd overtone crystal resonator is used an external tank circuit is necessary 2 The maximum load capacitance to be connected to CKIO pi...

Page 912: ... VIL VIH 1 2VDDQ Note When the clock is input from the EXTAL pin Figure 22 1 EXTAL Clock Input Timing tcyc tCKOH1 tCKOL1 tCKOr tCKOf 1 2VDDQ VOH VOH VOL VOL VOH 1 2VDDQ Figure 22 2 1 CKIO Clock Output Timing tCKOH2 tCKOL2 1 5 V 1 5 V 1 5 V Figure 22 2 2 CKIO Clock Output Timing ...

Page 913: ...cillation settling time when on chip resonator is used 2 PLL2 not operating Figure 22 3 Power On Oscillation Settling Time tRESW tOSC2 Standby Stable oscillation CKIO internal clock Notes 1 Oscillation settling time when on chip resonator is used 2 PLL2 not operating Figure 22 4 Standby Return Oscillation Settling Time Return by RESET RESET RESET RESET ...

Page 914: ...1 Oscillation settling time when on chip resonator is used 2 PLL2 operating Figure 22 5 Power On Oscillation Settling Time tRESW tOSC2 CKIO Stable oscillation Standby Internal clock Notes 1 Oscillation settling time when on chip resonator is used 2 PLL2 operating Figure 22 6 Standby Return Oscillation Settling Time Return by RESET RESET RESET RESET ...

Page 915: ...e when on chip resonator is used Figure 22 7 Standby Return Oscillation Settling Time Return by NMI tOSC4 Standby Stable oscillation CKIO internal clock Note Oscillation settling time when on chip resonator is used Figure 22 8 Standby Return Oscillation Settling Time Return by IRL3 IRL3 IRL3 IRL3 IRL0 IRL0 IRL0 IRL0 ...

Page 916: ...nchronization PLL synchronization Figure 22 9 PLL Synchronization Settling Time in Case of RESET RESET RESET RESET or NMI Interrupt interrupt request tIRLSTB STATUS1 STATUS0 Note When external clock from EXTAL is input Normal Standby Normal tPLL 2 EXTAL input PLL output CKIO output Internal clock Stable input clock Stable input clock PLL synchronization PLL synchronization Figure 22 10 PLL Synchro...

Page 917: ...Rev 6 0 07 02 page 867 of 986 CKIO SCK2 tSCK2RS tSCK2RH tRESW Figure 22 11 Manual Reset Input Timing tMDRS tMDRH MD6 MD3 Figure 22 12 Mode Input Timing ...

Page 918: ...hold time tBREQH 1 5 1 5 1 5 1 5 ns 22 13 BACK delay time tBACKD 5 3 6 6 6 ns 22 13 Bus tri state delay time tBOFF1 12 12 12 12 ns 22 13 Bus tri state delay time to standby mode tBOFF2 2 2 2 2 tcyc 22 14 Bus buffer on time tBON1 12 12 12 12 ns 22 13 Bus buffer on time from standby tBON2 1 1 1 1 tcyc 22 14 STATUS0 1 delay time tSTD1 5 6 6 6 ns 22 14 STATUS0 1 delay time to standby tSTD2 2 2 2 2 tcy...

Page 919: ... delay time tBOFF1 15 15 12 10 ns 22 13 Bus tri state delay time to standby mode tBOFF2 2 2 2 2 tcyc 22 14 Bus buffer on time tBON1 15 15 12 10 ns 22 13 Bus buffer on time from standby tBON2 1 1 1 1 tcyc 22 14 STATUS0 1 delay time tSTD1 11 11 9 7 ns 22 14 STATUS0 1 delay time to standby tSTD2 2 2 2 2 tcyc 22 14 Notes 1 VDDQ 3 0 to 3 6 V VDD typ 1 5 V Ta 20 to 75 C CL 30 pF PLL2 on 2 VDDQ 3 0 to 3 ...

Page 920: ...tion Normal operation Standby mode tSTD1 tBON2 CKIO STATUS 0 STATUS 1 RD RD DACKn DRAKn SCK TXD TXD2 Note When the PHZ bit in STBCR is set to 1 these pins go to the high impedance state except for pins being used as port pins which retain their port state A25 A0 D63 D0 tBOFF2 Standby Normal Normal tSTD2 Figure 22 14 Pin Drive Timing for Standby Mode ...

Page 921: ...s Write data delay time tWDD 1 5 5 3 1 5 6 1 5 6 1 5 6 ns RDY setup time tRDYS 2 2 5 3 5 3 5 ns RDY hold time tRDYH 1 5 1 5 1 5 1 5 ns RAS delay time tRASD 1 5 5 3 1 5 6 1 5 6 1 5 6 ns CAS delay time 1 tCASD1 1 5 5 3 1 5 6 1 5 6 1 5 6 ns DRAM CAS delay time 2 tCASD2 1 5 5 3 1 5 6 1 5 6 1 5 6 ns SDRAM CKE delay time tCKED 1 5 5 3 1 5 6 1 5 6 1 5 6 ns SDRAM DQM delay time tDQMD 1 5 5 3 1 5 6 1 5 6 1...

Page 922: ...tDTRH 1 5 1 5 1 5 1 5 ns DBREQ setup time tDBQS 2 0 2 5 3 5 3 5 ns DBREQ hold time tDBQH 1 5 1 5 1 5 1 5 ns TR setup time tTRS 2 0 2 5 3 5 3 5 ns TR hold time tTRH 1 5 1 5 1 5 1 5 ns BAVL delay time tBAVD 1 5 5 3 1 5 6 1 5 6 1 5 6 ns TDACK delay time tTDAD 1 5 5 3 1 5 6 1 5 6 1 5 6 ns ID1 ID0 delay time tIDD 1 5 5 3 1 5 6 1 5 6 1 5 6 ns Note VDDQ 3 0 to 3 6 V VDD typ 1 5 V Ta 20 to 75 C CL 30 pF P...

Page 923: ...e tWED1 1 5 10 1 5 8 1 5 6 ns Write data delay time tWDD 1 5 10 1 5 8 1 5 6 ns RDY setup time tRDYS 3 5 3 5 3 ns RDY hold time tRDYH 1 5 1 5 1 5 ns RAS delay time tRASD 1 5 10 1 5 8 1 5 6 ns CAS delay time 1 tCASD1 1 5 10 1 5 8 1 5 6 ns DRAM CAS delay time 2 tCASD2 1 5 10 1 5 8 1 5 6 ns SDRAM CKE delay time tCKED 1 5 10 1 5 8 1 5 6 ns SDRAM DQM delay time tDQMD 1 5 10 1 5 8 1 5 6 ns SDRAM FRAME de...

Page 924: ...5 1 5 ns TR setup time tTRS 3 5 3 5 3 ns TR hold time tTRH 1 5 1 5 1 5 ns BAVL delay time tBAVD 1 5 10 1 5 8 1 5 6 ns TDACK delay time tTDAD 1 5 10 1 5 8 1 5 6 ns ID1 ID0 delay time tIDD 1 5 10 1 5 8 1 5 6 ns Notes 1 VDDQ 3 0 to 3 6 V VDD typ 1 5 V Ta 20 to 75 C CL 30 pF PLL2 on 2 VDDQ 3 0 to 3 6 V VDD typ 1 8 V Ta 20 to 75 C CL 30 pF PLL2 on HD6417750SF167 HD6417750SF200 VDDQ 3 0 to 3 6 V VDD typ...

Page 925: ...8 1 2 6 ns Write data delay time tWDD 1 3 10 1 3 8 1 2 6 ns RDY setup time tRDYS 3 5 3 5 3 ns RDY hold time tRDYH 1 5 1 5 1 5 ns RAS delay time tRASD 1 3 10 1 3 8 1 2 6 ns CAS delay time 1 tCASD1 1 3 10 1 3 8 1 2 6 ns DRAM CAS delay time 2 tCASD2 1 3 10 1 3 8 1 2 6 ns SDRAM CKE delay time tCKED 0 5 10 0 5 8 0 5 6 ns SDRAM DQM delay time tDQMD 1 3 10 1 3 8 1 2 6 ns SDRAM FRAME delay time tFMD 1 3 1...

Page 926: ...R setup time tTRS 3 5 3 5 3 ns TR hold time tTRH 1 5 1 5 1 5 ns BAVL delay time tBAVD 1 3 10 1 3 8 1 2 6 ns TDACK delay time tTDAD 1 3 10 1 3 8 1 2 6 ns ID1 ID0 delay time tIDD 1 3 10 1 3 8 1 2 6 ns Notes 1 VDDQ 3 0 to 3 6 V VDD typ 1 5 V Ta 20 to 75 C CL 30 pF PLL2 on 2 VDDQ 3 0 to 3 6 V VDD typ 1 8 V Ta 20 to 75 C CL 30 pF PLL2 on HD6417750F167 VDDQ 3 0 to 3 6 V VDD typ 1 8 V Ta 40 to 85 C CL 30...

Page 927: ...RDH tRDS tCSD tCSD tRWD tRWD tRSD tRSD tRSD tWED1 tWEDF tWEDF tBSD tBSD tDACD tDACD tDACD tDACD tDACDF tDACDF tDACD Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high DACKn SA IO memory DACKn SA IO memory Figure 22 15 SRAM Bus Cycle Basic Bus Cycle No Wait ...

Page 928: ...tAD tRDH tRDS tCSD tRWD tRWD tCSD tRSD tRSD tRSD tWED1 tWEDF tWEDF tRDYH tRDYS tBSD tBSD tDACD tDACD tDACD tDACD tDACD DACKn SA IO memory DACKn SA IO memory Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 22 16 SRAM Bus Cycle Basic Bus Cycle One Internal Wait ...

Page 929: ... tCSD tRWD tRWD tCSD tRSD tRSD tRSD tWED1 tWEDF tWEDF tRDYH tRDYS tRDYH tRDYS tBSD tBSD tDACD tDACD tDACD tDACD tDACD DACKn SA IO memory DACKn SA IO memory Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 22 17 SRAM Bus Cycle Basic Bus Cycle One Internal Wait One External Wait ...

Page 930: ...D tWED1 tWEDF tWEDF tBSD tBSD tDACD tDACD CKIO A25 A0 RD D63 D0 read D63 D0 write DACKn SA IO memory DACKn SA IO memory DACKn DA Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high SH7750R only Figure 22 18 SRAM Bus Cycle Basic Bus Cycle No Wait Address Setup Hold Time Insertion AnS 1 AnH 1 ...

Page 931: ...B2 TB1 tCSD tAD tRWD tBSD tRDS tBSD tRSD tRSD tRDH tAD tAD tCSD tRWD tRDH tRSD tRDS DACKn SA IO memory DACKn DA tDACD tDACD tDACD tDACD tDACD Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 22 19 Burst ROM Bus Cycle No Wait ...

Page 932: ...H t RDYS t RDYH t RDYS t RDYH t RDYS t DACD t DACD t DACD t DACD t RWD t RWD CKIO A25 A5 RD D31 D0 read A4 A0 DACKn SA IO memory DACKn DA Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 22 20 Burst ROM Bus Cycle 1st Data One Internal Wait One External Wait 2nd 3rd 4th Data One Internal Wait ...

Page 933: ... TB1 t AD t CSD t RWD t RDH t RSD t RDS TH1 TS1 TH1 TS1 TH1 TS1 TH1 CKIO A25 A5 RD D31 D0 read A4 A0 DACKn SA IO memory DACKn DA Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high t DACD t DACD Figure 22 21 Burst ROM Bus Cycle No Wait Address Setup Hold Time Insertion AnS 1 AnH 1 ...

Page 934: ...S DACKn DA Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high t DACD t DACD t DACD t BSD t BSD t BSD t BSD t RSD t RSD t RWD t CSD t RWD t CSD t DACD t DACD t RSD RD t RDYH t RDYS t RDYH t RDYS t RDYH t RDYS t RDYH t RDYS DACKn SA IO memory Figure 22 22 Burst ROM Bus Cycle One Internal Wait One External Wait ...

Page 935: ...DS DQMn D63 D0 write CKE t WDD t WDD t CASD2 t CASD2 t CASD2 t DACD t DACD t DACD t RASD t RASD t DQMD t DQMD t RWD t BSD t BSD RD t CSD t CSD DACKn SA IO memory Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high t RWD Figure 22 23 Synchronous DRAM Auto Precharge Read Bus Cycle Single RCD 1 0 01 CAS Latency 3 TPC 2 0 011 ...

Page 936: ... DQMn D63 D0 write CKE t WDD t WDD t CASD2 t CASD2 t CASD2 t DACD t DACD t DACD t RASD t RASD t DQMD t DQMD t RWD t BSD t BSD RD t CSD t CSD t AD DACKn SA IO memory t RWD Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 22 24 Synchronous DRAM Auto Precharge Read Bus Cycle Burst RCD 1 0 01 CAS Latency 3 TPC 2 0 011 ...

Page 937: ...0 d1 d2 d3 tCSD tCSD tRWD tRWD tRASD tRASD tBSD tBSD tDQMD tDQMD tDACD tDACD tWDD tWDD tDACD tCASD2 tCASD2 tCASD2 D63 D0 read D63 D0 write DACKn SA IO memory Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 22 25 Synchronous DRAM Normal Read Bus Cycle ACT READ Commands Burst RCD 1 0 01 CAS Latency 3 ...

Page 938: ...SD tCSD tRWD tRWD tRASD tRASD tRASD tRASD tBSD tBSD tDQMD tDACD tDACD tWDD tWDD tDACD tCASD2 tCASD2 tCASD2 tDQMD D63 D0 read D63 D0 write DACKn SA IO memory Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 22 26 Synchronous DRAM Normal Read Bus Cycle PRE ACT READ Commands Burst RCD 1 0 01 TPC 2 0 001 CAS Latency 3 ...

Page 939: ...1 d2 d3 tCSD tCSD tRWD tRWD tRASD tRASD tBSD tBSD tDQMD tDQMD tCASD2 tCASD2 tDACD tDACD tWDD tWDD tDACD D63 D0 read D63 D0 write DACKn SA IO memory Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 22 27 Synchronous DRAM Normal Read Bus Cycle READ Command Burst CAS Latency 3 ...

Page 940: ...D DQMn CKE tWDD tCASD2 tCASD2 tCASD2 tDACD tDACD tRWD tRWD tRASD tRASD tDQMD tDQMD tBSD tBSD RD tCSD tCSD D63 D0 write DACKn SA IO memory Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 22 28 Synchronous DRAM Auto Precharge Write Bus Cycle Single RCD 1 0 01 TPC 2 0 001 TRWL 2 0 010 ...

Page 941: ...2 d3 DQMn CKE tWDD tCASD2 tCASD2 tCASD2 tDACD tDACD tRWD tRWD tRASD tRASD tDQMD tDQMD tBSD tBSD RD tCSD tCSD D63 D0 write DACKn SA IO memory Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 22 29 Synchronous DRAM Auto Precharge Write Bus Cycle Burst RCD 1 0 01 TPC 2 0 001 TRWL 2 0 010 ...

Page 942: ... d3 DQMn CKE tWDD tCASD2 tCASD2 tCASD2 tDACD tDACD tRWD tRWD tRASD tRASD tDQMD tDQMD tBSD tBSD RD tCSD tCSD D63 D0 write DACKn SA IO memory Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 22 30 Synchronous DRAM Normal Write Bus Cycle ACT WRITE Commands Burst RCD 1 0 01 TRWL 2 0 010 ...

Page 943: ... tWDD tCASD2 tCASD2 tCASD2 tDQMD tDQMD tDACD tRWD tRWD tRWD tRWD tRASD tRASD tRASD tRASD tDACD tDACD tBSD tBSD RD tCSD tCSD D63 D0 write DACKn SA IO memory Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 22 31 Synchronous DRAM Normal Write Bus Cycle PRE ACT WRITE Commands Burst RCD 1 0 01 TPC 2 0 001 TRWL 2 0 010 ...

Page 944: ...Kn SA IO memory Normal write SA DMA Notes In the case of SA DMA only the Tnop cycle is inserted and the DACKn signal is output as shown by the solid line In a normal write the Tnop cycle is omitted and the DACKn signal is output as shown by the dotted line IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 22 32 Synchronous DRAM Normal Write B...

Page 945: ...CASD2 tCASD2 tDQMD tDQMD tRWD tRWD DACKn tRASD tRASD tDACD tDACD tBSD tWDD tWDD RD tCSD tCSD D63 D0 write Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 22 33 Synchronous DRAM Bus Cycle Synchronous DRAM Precharge Command TPC 2 0 001 ...

Page 946: ...ACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high CKE tAD tAD tRWD tRWD tDQMD tDQMD tBSD tDACD tWDD tWDD tCASD2 tCASD2 tCASD2 tCASD2 tRASD tRASD tRASD tRASD tCSD tCSD tCSD tCSD tDACD D63 D0 write Figure 22 34 Synchronous DRAM Bus Cycle Synchronous DRAM Auto Refresh TRAS 1 TRC 2 0 001 ...

Page 947: ...DA Dual address DMA transfer DACK set to active high CKE TRs1 TRs2 TRs3 TRs4 TRs5 Trc Trc Trc tAD tAD tRWD tDQMD tDQMD tDACD tDACD tWDD tWDD tCASD2 tCASD2 tCASD2 tCKED tCKED tRASD tRASD tRASD tRASD tCSD tCSD tCSD tCSD D63 D0 write tRWD tCASD2 tBSD Figure 22 35 Synchronous DRAM Bus Cycle Synchronous DRAM Self Refresh TRC 2 0 001 ...

Page 948: ...IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high CKE tAD tAD tAD tRWD tRWD tRWD tCSD tCSD tCSD tBSD tDQMD tDACD tWDD tWDD tDACD tCASD2 tCASD2 tCASD2 tCASD2 tRASD tRASD tRASD tDQMD D63 D0 write Figure 22 36 a Synchronous DRAM Bus Cycle Synchronous DRAM Mode Register Setting PALL ...

Page 949: ...IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high CKE tAD tAD tAD tRWD tRWD tRWD tCSD tCSD tCSD tBSD tDQMD tDACD tWDD tWDD tDACD tCASD2 tCASD2 tCASD2 tCASD2 tRASD tRASD tRASD tDQMD D63 D0 write Figure 22 36 b Synchronous DRAM Bus Cycle Synchronous DRAM Mode Register Setting SET ...

Page 950: ...Tc1 Tc2 Tpc t AD t AD t AD Row column t WDD t WDD t WDD t CASD1 t CASD1 t CASD1 t BSD t BSD t DACD t DACD t DACD t CSD t CSD t DACD t DACD t DACD t RWD t RWD t RASD t RASD t RASD t RDH t RDS 1 2 DACKn SA IO memory DACKn SA IO memory D63 D0 read D63 D0 write Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 22 37 DRAM Bus Cycles 1 RCD 1 ...

Page 951: ...D tRWD tCASD1 tCASD1 tCASD1 tBSD tBSD RD tCSD tCSD tDACD tDACD tRDH tRDS A25 A0 DACKn SA IO memory D63 D0 read D63 D0 write tRWD Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 22 38 DRAM Bus Cycle EDO Mode RCD 1 0 00 AnW 2 0 000 TPC 2 0 001 ...

Page 952: ... CASD1 t CASD1 t CASD1 t BSD t BSD t BSD t BSD t DACD t CSD t CSD t DACD t DACD t RWD t RDH t RDS d0 t RDH t RDS d3 d2 d1 CKIO RD A25 A0 DACKn SA IO memory Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high D63 D0 read D63 D0 write Figure 22 39 DRAM Burst Bus Cycle EDO Mode RCD 1 0 00 AnW 2 0 000 TPC 2 0 001 ...

Page 953: ...Row c0 c1 c2 c3 RD t CSD t CSD t CASD1 t CASD1 t CASD1 t CASD1 t RASD t CASD1 t CASD1 t BSD t BSD t DACD t DACD t DACD t RWD t RWD t WDD A25 A0 DACKn SA IO memory Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high D63 D0 read D63 D0 write Figure 22 40 DRAM Burst Bus Cycle EDO Mode RCD 1 0 01 AnW 2 0 001 TPC 2 0 001 ...

Page 954: ...w c0 c1 c2 c3 RD t CSD t CSD t CASD1 t CASD1 t CASD1 t RASD t CASD1 t CASD1 t BSD t BSD t DACD t DACD t DACD t RWD t RWD t WDD A25 A0 DACKn SA IO memory Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high D63 D0 read D63 D0 write Figure 22 41 DRAM Burst Bus Cycle EDO Mode RCD 1 0 01 AnW 2 0 001 TPC 2 0 001 2 Cycle CAS Negate Pulse Width ...

Page 955: ...D t WDD t RASD t CASD1 t CASD1 t CASD1 t CASD1 d3 d2 d1 d0 t BSD t BSD t BSD t BSD t DACD t DACD t DACD Tc1 Tc1 Tc2 Tce Tc2 A25 A0 DACKn SA IO memory Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high D63 D0 read D63 D0 write Figure 22 42 DRAM Burst Bus Cycle RAS Down Mode State EDO Mode RCD 1 0 00 AnW 2 0 000 ...

Page 956: ...ended t CSD t CASD1 t WDD t CASD1 t CASD1 t CASD1 t CASD1 d3 d2 d1 d0 t BSD t BSD t BSD t BSD t DACD t DACD Tc1 Tce Tc2 DACKn SA IO memory Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high D63 D0 read D63 D0 write Figure 22 43 DRAM Burst Bus Cycle RAS Down Mode Continuation EDO Mode RCD 1 0 00 AnW 2 0 000 ...

Page 957: ...al address DMA transfer DACK set to active high DACKn SA IO memory t AD c0 Row c1 c2 c3 t AD t AD t RWD t RWD t RDH t RDS d0 t WDD d0 d1 d2 d3 t BSD t BSD t WDD d1 d2 t RDH t WDD t RDS d3 t WDD t CSD t CSD t DACD t DACD t DACD t CASD1 t CASD1 t CASD1 t CASD1 t CASD1 t RASD t RASD t RASD t DACD t DACD t DACD Figure 22 44 DRAM Burst Bus Cycle Fast Page Mode RCD 1 0 00 AnW 2 0 000 TPC 2 0 001 ...

Page 958: ...d3 t WDD t CSD t CSD t DACD t DACD t DACD t CASD1 t CASD1 t CASD1 t CASD1 t CASD1 t RASD t RASD t RASD t DACD t DACD t DACD Tc1 Tc2 Tc2 Tcw Tpc A25 A0 D63 D0 read D63 D0 write DACKn SA IO memory Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high DACKn SA IO memory Figure 22 45 DRAM Burst Bus Cycle Fast Page Mode RCD 1 0 01 AnW 2 0 001 TPC 2 0 0...

Page 959: ...ACD t DACD t DACD t CASD1 t CASD1 t CASD1 t CASD1 t CASD1 t RASD t RASD t RASD t DACD t DACD t DACD Tcw Tc1 Tcnw Tc2 Tc1 Tpc Tc2 Tcnw Tcw A25 A0 D63 D0 read D63 D0 write DACKn SA IO memory Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high DACKn SA IO memory Figure 22 46 DRAM Burst Bus Cycle Fast Page Mode RCD 1 0 01 AnW 2 0 001 TPC 2 0 001 2 C...

Page 960: ...s DMA transfer DACK set to active high DACKn SA IO memory t AD c0 Row c1 c2 c3 t AD t AD t AD t RWD t RWD t RWD t RDH t RDS d0 t WDD d0 d1 d2 d3 t BSD t BSD t WDD d1 d2 t RDH t WDD t RDS d3 t WDD t CSD t CSD t CSD t DACD t DACD t DACD t CASD1 t CASD1 t CASD1 t CASD1 t CASD1 t DACD t DACD t DACD t RASD t RASD Figure 22 47 DRAM Burst Bus Cycle RAS Down Mode State Fast Page Mode RCD 1 0 00 AnW 2 0 00...

Page 961: ...e ended t DACD t DACD t DACD t CASD1 t CASD1 t CASD1 t CASD1 t CASD1 t DACD t DACD t DACD Tnop Tc1 Tc2 Tc1 Tc1 Tc2 Tc2 Tc1 Tc2 A25 A0 D63 D0 read D63 D0 write DACKn SA IO memory Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high DACKn SA IO memory Figure 22 48 DRAM Burst Bus Cycle RAS Down Mode Continuation Fast Page Mode RCD 1 0 00 AnW 2 0 000...

Page 962: ...e DACKn SA IO memory Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high DACKn SA IO memory tAD tWDD tDACD tDACD tCSD tRWD tRASD tRASD tRASD tCASD1 tCASD1 tCASD1 Figure 22 49 DRAM Bus Cycle DRAM CAS Before RAS Refresh TRAS 2 0 000 TRC 2 0 001 ...

Page 963: ...tDACD tCSD tRWD tRASD tRASD tRASD tCASD1 tCASD1 tCASD1 A25 A0 D63 D0 write DACKn SA IO memory Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high DACKn SA IO memory Figure 22 50 DRAM Bus Cycle DRAM CAS Before RAS Refresh TRAS 2 0 001 TRC 2 0 001 ...

Page 964: ...D tDACD tDACD tCSD tRWD tRASD tRASD tRASD tCASD1 tCASD1 tCASD1 A25 A0 D63 D0 write DACKn SA IO memory Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high DACKn SA IO memory Figure 22 51 DRAM Bus Cycle DRAM Self Refresh TRC 2 0 001 ...

Page 965: ...t DACD t RDH t RDS t RDYH t RDYS t RDYH t RDYS t DACD t AD t AD t WDD t WDD t WDD t RWD t CSD t CSD t RWD t RSD t RSD t RSD t WEDF t WED1 t WEDF t DACD TED TEH t RDH t RDS t DACD 1 2 A25 A0 Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high SH7750S only Figure 22 52 PCMCIA Memory Bus Cycle 1 TED 2 0 000 TEH 2 0 000 No Wait 2 TED 2 0 001 TEH 2 0...

Page 966: ...t WDD t RWD t CSD t CSD t RWD t ICRSD t ICRSD t ICWSDF t ICWSDF t DACD t RDH t RDS t RDYH t RDYS t RDYH t RDYS t IO16H t IO16S t IO16H t IO16S t DACD t AD t AD t WDD t WDD t WDD t RWD t CSD t CSD t RWD t ICRSD t ICRSD t ICRSD t ICWSDF t ICWSDF t ICWSDF t DACD t RDH t RDS t DACD D15 D0 read D15 D0 write 1 2 A25 A0 Figure 22 53 PCMCIA I O Bus Cycle 1 TED 2 0 000 TEH 2 0 000 No Wait 2 TED 2 0 001 TEH...

Page 967: ...ddress DMA transfer DA Dual address DMA transfer DACK set to active high t BSD t BSD t AD t AD t WDD t WDD t WDD t WDD t WDD t RWD t RWD t AD t CSD t CSD t CSD t ICRSD t ICRSD t ICRSD t ICWSDF t ICWSDF t ICWSDF t ICWSDF t ICWSDF t RDH t RDS t RDYS t RDYH t IO16S t IO16H t RDYS t RDYH Figure 22 54 PCMCIA I O Bus Cycle TED 2 0 001 TEH 2 0 001 One Internal Wait Bus Sizing ...

Page 968: ...S t RDYH t RDYS 1st data bus cycle information D63 D61 Access size 000 Byte 001 Word 2 bytes 010 Long 4 bytes 011 Quad 8 bytes 1xx Burst 32 bytes D25 D0 Address 1st data bus cycle information D63 D61 Access size 000 Byte 001 Word 2 bytes 010 Long 4 bytes 011 Quad 8 bytes 1xx Burst 32 bytes D25 D0 Address Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to a...

Page 969: ... FMD t BSD t BSD t CSD t CSD t DACD t DACD t WED1 t WED1 D0 t RWD t RWD A t WDD t WDD t WDD 1st data bus cycle information D63 D61 Access size 000 Byte 001 Word 2 bytes 010 Long 4 bytes 011 Quad 8 bytes 1xx Burst 32 bytes D25 D0 Address 1st data bus cycle information D63 D61 Access size 000 Byte 001 Word 2 bytes 010 Long 4 bytes 011 Quad 8 bytes 1xx Burst 32 bytes D25 D0 Address 1st data bus cycle...

Page 970: ...D t CSD t RDYS t RDYH t RDYH t RDYS t DACD t DACD t WED1 t WED1 D3 t RWD t RWD A t WDD D2 D1 D0 t WDD t RDH t RDS 1st data bus cycle information D63 D61 Access size 000 Byte 001 Word 2 bytes 010 Long 4 bytes 011 Quad 8 bytes 1xx Burst 32 bytes D25 D0 Address 1st data bus cycle information D63 D61 Access size 000 Byte 001 Word 2 bytes 010 Long 4 bytes 011 Quad 8 bytes 1xx Burst 32 bytes D25 D0 Addr...

Page 971: ... t FMD t FMD t BSD t BSD t CSD t CSD t RDYS t RDYH t RDYH t RDYS t DACD t DACD t WED1 t WED1 t RWD t RWD A t WDD t WDD 1st data bus cycle information D63 D61 Access size 000 Byte 001 Word 2 bytes 010 Long 4 bytes 011 Quad 8 bytes 1xx Burst 32 bytes D25 D0 Address 1st data bus cycle information D63 D61 Access size 000 Byte 001 Word 2 bytes 010 Long 4 bytes 011 Quad 8 bytes 1xx Burst 32 bytes D25 D0...

Page 972: ... t RSD t RSD t RSD t RSD t RSD t WED1 t WED1 t WEDF t WED1 t WEDF t WED1 t WEDF t WED1 t CSD t CSD t DACD t BSD t BSD t BSD t BSD t BSD t BSD t DACD t DACD t RWD t RWD t RSD t AD t AD t RDH t RDS t RDH t RDS t RDH t RDS DACKn SA IO memory 2 3 Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 22 59 Memory Byte Control SRAM Bus Cycles 1 B...

Page 973: ... tDACD tBSD tBSD tDACD tRWD tRWD tRSD tAD tAD tRDH tRDS DACKn SA IO memory tDACD tDACD Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 22 60 Memory Byte Control SRAM Bus Cycle Basic Read Cycle No Wait Address Setup Hold Time Insertion AnS 0 1 AnH 1 0 0 1 ...

Page 974: ... 8 Pcyc 1 22 61 Timer clock fall time tTCLKf 0 8 0 8 0 8 0 8 Pcyc 1 22 61 Oscillation settling time tROSC 3 3 3 3 s 22 62 SCI Input clock cycle asyn chronous tScyc 4 4 4 4 Pcyc 1 22 63 Input clock cycle syn chronous tScyc 6 6 6 6 Pcyc 1 22 63 Input clock pulse width tSCKW 0 4 0 6 0 4 0 6 0 4 0 6 0 4 0 6 tScyc 22 63 Input clock rise time tSCKr 0 8 0 8 0 8 0 8 Pcyc 1 22 63 Input clock fall time tSCK...

Page 975: ...0 30 30 ns 22 71 Standby mode 5 5 5 5 tcyc 22 71 Normal or sleep mode INTC NMI pulse width low tNMIL 30 30 30 30 ns 22 71 Standby mode H UDI Input clock cycle tTCKcyc 50 50 50 50 ns 22 67 Input clock pulse width high tTCKH 15 15 15 15 ns 22 67 Input clock pulse width low tTCKL 15 15 15 15 ns 22 67 Input clock rise time tTCKr 10 10 10 10 ns 22 67 Input clock fall time tTCKf 10 10 10 10 ns 22 67 ASE...

Page 976: ...llation settling time tROSC 3 3 3 s 22 62 SCI Input clock cycle asyn chronous tScyc 4 4 4 Pcyc 1 22 63 Input clock cycle syn chronous tScyc 6 6 6 Pcyc 1 22 63 Input clock pulse width tSCKW 0 4 0 6 0 4 0 6 0 4 0 6 tScyc 22 63 Input clock rise time tSCKr 0 8 0 8 0 8 Pcyc 1 22 63 Input clock fall time tSCKf 0 8 0 8 0 8 Pcyc 1 22 63 Transfer data delay time tTXD 1 5 10 1 5 8 1 5 6 ns 22 64 Receive dat...

Page 977: ...ck pulse width high tTCKH 15 15 15 ns 22 67 Input clock pulse width low tTCKL 15 15 15 ns 22 67 Input clock rise time tTCKr 10 10 10 ns 22 67 Input clock fall time tTCKf 10 10 10 ns 22 67 ASEBRK setup time tASEBRKS 10 10 10 tcyc 22 68 ASEBRK hold time tASEBRKH 10 10 10 tcyc 22 68 TDI TMS setup time tTDIS 15 15 15 ns 22 69 TDI TMS hold time tTDIH 15 15 15 ns 22 69 TDO delay time tTDO 0 10 0 10 0 10...

Page 978: ...ime tROSC 3 3 3 s 22 62 SCI Input clock cycle asyn chronous tScyc 4 4 4 Pcyc 1 22 63 Input clock cycle syn chronous tScyc 6 6 6 Pcyc 1 22 63 Input clock pulse width tSCKW 0 4 0 6 0 4 0 6 0 4 0 6 tScyc 22 63 Input clock rise time tSCKr 0 8 0 8 0 8 Pcyc 1 22 63 Input clock fall time tSCKf 0 8 0 8 0 8 Pcyc 1 22 63 Transfer data delay time tTXD 1 3 10 1 3 8 1 2 6 ns 22 64 Receive data setup time synch...

Page 979: ...idth high tTCKH 15 15 15 ns 22 67 Input clock pulse width low tTCKL 15 15 15 ns 22 67 Input clock rise time tTCKr 10 10 10 ns 22 67 Input clock fall time tTCKf 10 10 10 ns 22 67 ASEBRK setup time tASEBRKS 10 10 10 tcyc 22 68 ASEBRK hold time tASEBRKH 10 10 10 tcyc 22 68 TDI TMS setup time tTDIS 15 15 15 ns 22 69 TDI TMS hold time tTDIH 15 15 15 ns 22 69 TDO delay time tTDO 0 10 0 10 0 10 ns 22 69 ...

Page 980: ... tTCLKWH tTCLKWL tTCLKr Figure 22 61 TCLK Input Timing RTC internal clock tROSC Stable oscillation VDD RTC VDD RTC min Figure 22 62 RTC Oscillation Settling Time at Power On SCK SCK2 tSCKf tScyc tSCKW tSCKr Figure 22 63 SCK Input Clock Timing ...

Page 981: ...tRXH tScyc Figure 22 64 SCI I O Synchronous Mode Clock Timing tPORTD tPORTD CKIO Ports 19 0 read Ports 19 0 write tPORTS tPORTH Figure 22 65 I O Port Input Output Timing tDRAKD tDRQH tDRQH tDRQS tDRQS CKIO DRAKn Figure 22 66 a DREQ DREQ DREQ DREQ DRAK Timing ...

Page 982: ...100 MHz tDTRS tDTRH DTR 10 ns Figure 22 66 b DBREQ DBREQ DBREQ DBREQ TR TR TR TR Input Timing and BAVL BAVL BAVL BAVL Output Timing tTCKcyc tTCKH tTCKL tTCKr tTCKf 1 2VDDQ VIH VIH VIL VIL VIH 1 2VDDQ Note When clock is input from TCK pin Figure 22 67 TCK Input Timing BRKACK SCK2 tASEBRKH tASEBRKS tASEBRKS tASEBRKH Low High Figure 22 68 RESET RESET RESET RESET Hold Timing ...

Page 983: ...Rev 6 0 07 02 page 933 of 986 TDI TMS TCK TDO tTCKcyc tTDO tTDIH tTDIS Figure 22 69 H UDI Data Transfer Timing tPINBRK Figure 22 70 Pin Break Timing tNMIH tNMIL NMI Figure 22 71 NMI Input Timing ...

Page 984: ...SQ 3 0 V VSSQ VDDQ for RESET TRST NMI and ASEBRK BRKACK Input rise fall time 1 ns The output load circuit is shown in figure 22 72 IOL IOH CL VREF LSI output pin DUT output Notes 1 2 CL is the total value including the capacitance of the test jig etc The capacitance of each pin is set to 30 pF IOL and IOH values are as shown in table 22 16 Permissible Output Currents Figure 22 72 Output Load Circu...

Page 985: ...o the SH7750 Series pins is shown below The graph shown in figure 22 73 should be taken into consideration if the stipulated capacitance is exceeded when connecting an external device The graph will not be linear if the connected load capacitance exceeds the range shown in figure 22 73 4 0 ns 3 0 ns 2 0 ns 1 0 ns 0 0 ns 0 pF 25 pF 50 pF Load Capacitance Delay Time Figure 22 73 Load Capacitance vs ...

Page 986: ...Rev 6 0 07 02 page 936 of 986 ...

Page 987: ...034 H 1F00 0034 32 Undefined Undefined Held Held Iclk CCN QACR0 H FF00 0038 H 1F00 0038 32 Undefined Undefined Held Held Iclk CCN QACR1 H FF00 003C H 1F00 003C 32 Undefined Undefined Held Held Iclk UBC BARA H FF20 0000 H 1F20 0000 32 Undefined Held Held Held Iclk UBC BAMRA H FF20 0004 H 1F20 0004 8 Undefined Held Held Held Iclk UBC BBRA H FF20 0008 H 1F20 0008 16 H 0000 Held Held Held Iclk UBC BAR...

Page 988: ...DMAC SAR0 H FFA0 0000 H 1FA0 0000 32 Undefined Undefined Held Held Bclk DMAC DAR0 H FFA0 0004 H 1FA0 0004 32 Undefined Undefined Held Held Bclk DMAC DMATCR0 H FFA0 0008 H 1FA0 0008 32 Undefined Undefined Held Held Bclk DMAC CHCR0 H FFA0 000C H 1FA0 000C 32 H 0000 0000 H 0000 0000 Held Held Bclk DMAC SAR1 H FFA0 0010 H 1FA0 0010 32 Undefined Undefined Held Held Bclk DMAC DAR1 H FFA0 0014 H 1FA0 001...

Page 989: ... Held Held Bclk DMAC SAR7 5 H FFA0 0080 H 1FA0 0080 32 Undefined Undefined Held Held Bclk DMAC DAR7 5 H FFA0 0084 H 1FA0 0084 32 Undefined Undefined Held Held Bclk DMAC DMATCR7 5 H FFA0 0088 H 1FA0 0088 32 Undefined Undefined Held Held Bclk DMAC CHCR7 5 H FFA0 008C H 1FA0 008C 32 H 0000 0000 H 0000 0000 Held Held Bclk CPG FRQCR H FFC0 0000 H 1FC0 0000 16 2 Held Held Held Pclk CPG 6 STBCR H FFC0 00...

Page 990: ...000 H 0000 Held Held Pclk INTC IPRC H FFD0 000C H 1FD0 000C 16 H 0000 H 0000 Held Held Pclk INTC IPRD 4 H FFD00010 H 1F000010 16 H DA74 H DA74 Held Held Pclk INTC INTPRI00 5 H FE08 0000 H 1E08 0000 32 H 0000 0000 Held Held Held Pclk INTC INTREQ00 5 H FE08 0020 H 1E08 0020 32 H 0000 0000 Held Held Held Pclk INTC INTMSK00 5 H FE08 0040 H 1E08 0040 32 H 0000 0300 Held Held Held Pclk INTC INTMSKCL R00...

Page 991: ...d Pclk SCI SCSMR1 H FFE0 0000 H 1FE0 0000 8 H 00 H 00 Held H 00 Pclk SCI SCBRR1 H FFE0 0004 H 1FE0 0004 8 H FF H FF Held H FF Pclk SCI SCSCR1 H FFE0 0008 H 1FE0 0008 8 H 00 H 00 Held H 00 Pclk SCI SCTDR1 H FFE0 000C H 1FE0 000C 8 H FF H FF Held H FF Pclk SCI SCSSR1 H FFE0 0010 H 1FE0 0010 8 H 84 H 84 Held H 84 Pclk SCI SCRDR1 H FFE0 0014 H 1FE0 0014 8 H 00 H 00 Held H 00 Pclk SCI SCSCMR1 H FFE0 00...

Page 992: ...d Held Held Pclk Notes 1 With control registers the above addresses in the physical page number field can be accessed by means of a TLB setting When these addresses are referenced directly without using the TLB operations are limited 2 Includes undefined bits See the descriptions of the individual modules 3 Use word size access when writing Perform the write with the upper byte set to H 5A or H A5...

Page 993: ...6 0 1 0 35 C C 0 20 C Details of the part A 256 φ0 75 0 15 0 30 C B A M 0 10 C M Y V T P M K H F D B W U R N L J G E C A A 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 Hitachi Code JEDEC JEITA Mass reference value BP 256 Conforms 3 0 g Unit mm Figure B 1 Package Dimensions 256 Pin BGA SH7750 and SH7750S ...

Page 994: ... C 0 20 C Details of the part A 256 φ0 75 0 15 0 30 C B A M 0 10 C M Y V T P M K H F D B W U R N L J G E C A A 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 Hitachi Code JEDEC JEITA Mass reference value BP 256A Conforms 3 0 g Unit mm Figure B 2 Package Dimensions 256 Pin BGA SH7750R Only ...

Page 995: ...Conforms 5 3 g Dimension including the plating thickness Base material dimension 30 6 0 2 30 6 0 2 0 5 3 56 Max 0 8 0 17 0 05 156 105 104 52 1 157 208 53 0 22 0 05 0 10 M 0 10 3 20 0 5 0 1 1 3 28 0 15 0 10 0 15 1 25 0 20 0 04 0 15 0 04 Unit mm Figure B 3 Package Dimensions 208 Pin QFP ...

Page 996: ...C C 0 10 C 0 80 0 40 0 05 1 40Max B A D C F E H G K J M L P N T R U 17 15 16 13 14 11 12 9 10 7 8 5 6 3 4 1 2 Hitachi Code JEDEC JEITA Mass reference value BP 264 0 6 g 0 20 C A 0 20 C B B C φ0 08 A B 264 φ0 50 0 05 M A Unit mm Figure B 4 Package Dimensions 264 Pin CSP ...

Page 997: ...perating mode 2 For the ranges of input clock frequency see the descriptions of the EXTAL clock input frequency fEX and CKIO clock output fOP in section 22 3 1 Clock and Control Signal Timing Clock Operating Modes SH7750R External Pin Combination Frequency vs Input Clock Clock Operating Mode MD2 MD1 MD0 PLL1 PLL2 CPU Clock Bus Clock Peripheral Module Clock FRQCR Initial Value 0 0 On 12 On 12 3 3 H...

Page 998: ...ited 1 0 16 bits Reserved 1 32 bits MPX interface 1 0 0 64 bits SRAM interface 1 8 bits SRAM interface 1 0 16 bits SRAM interface 1 32 bits SRAM interface 3 Endian Pin Value MD5 Endian 0 Big endian 1 Little endian 4 Master Slave Pin Value MD7 Master Slave 0 Slave 1 Master 5 Clock Input Pin Value MD8 Clock Input 0 External input clock 1 Crystal resonator ...

Page 999: ...onfiguration rd_pullup_control rd_dt_ rd_hiz_control rdwr_pullup_control rdwr_dt_ rdwr_hiz_control Bus clock ckio_hiz_control VSSQ CKIO2 CKIO RD RD VDDQ VDDQ VDDQ VDDQ VDDQ SH7750 Series PLL2 Figure D 1 CKIO2ENB CKIO2ENB CKIO2ENB CKIO2ENB Pin Configuration ...

Page 1000: ...Description 0 RD2 RD WR2 and CKIO2 have the same pin states as RD RD WR and CKIO respectively 1 RD2 RD WR2 and CKIO2 are in the high impedance state Note CKIO is fed back to PLL2 to coordinate the external clock and internal clock phases However CKIO2 is not fed back ...

Page 1001: ...63 I O Z 15 Z 15 Z 15 Z 15 Z 15 Z 15 Z A0 A1 A18 A25 O Z 16 Z 16 Z 14 O 17 Z 14 Z 14 O 7 Z 14 Z A2 A17 O Z 16 Z 16 Z 14 O 9 Z 14 Z 14 O 7 Z 14 Z RESET I I I I I I I I BACK BSREQ O H H H H H O Z BREQ BSACK I I 16 I 16 I 13 I 13 I 13 I 13 I BS O H Z 16 H Z 14 Z 14 H 7 Z 14 Z CKE O H H O 6 O 6 L O 6 Z CS6 CS0 O H Z 16 H Z 14 Z 14 H 7 Z 14 Z RAS O H Z 16 O 6 Z 14 Z 14 O 5 Z 14 O 5 Z RD CASS O H Z 16 O...

Page 1002: ...1 ZO 11 ZO 11 ZO 11 Z STATUS1 STATUS0 O O O O O O O Z 18 IRL3 IRL0 I PI 16 PI 16 I 13 I 13 I 13 I 13 I INTC NMI I PI 16 PI 16 I 13 I 13 I 13 I 13 I INTC DREQ1 DREQ0 I PI 16 PI 16 I 12 I 12 I 12 I 12 I DMAC DRAK1 DRAK0 O L L L L Z 12 O 8 O 12 Z DMAC MD0 SCK I O I 16 I 16 I 12 I 12 I 12 Z 12 O 8 I 12 O Z SCI RXD I PI 16 PI 16 I 12 I 12 I 12 I 12 I SCI SCK2 MRESET I PI 16 PI 16 I 12 I 12 I 12 I 12 I ...

Page 1003: ...depending on register setting BCR1 HIZCNT 6 Depends on refresh operation 7 Z I or H state held depending on register setting BCR1 HIZMEM 8 Z or O depending on register setting STBCR PHZ 9 Output when refreshing is set 10 Operation in respective state when CKIO2ENB 0 Z when CKIO2ENB 1 11 Z or O depending on register setting FRQCR CKOEN 12 Pulled up or not pulled up depending on register setting STB...

Page 1004: ...ed VDD RTC Power supply 3 3 V VSS RTC Power supply 0 V When PLL1 is not used VDD PLL1 Power supply 3 3 V VSS PLL1 Power supply 0 V When PLL2 is not used VDD PLL2 Power supply 3 3 V VSS PLL2 Power supply 0 V When on chip crystal oscillator is not used XTAL Leave unconnected VDD CPG Power supply 3 3 V VSS CPG Power supply 0 V ...

Page 1005: ...8MB SH7750 Series Address Pins RAS Cycle CAS Cycle Synchronous DRAM Address Pins Function A14 A22 A22 A11 BANK selects bank address A13 A21 H L A10 Address precharge setting A12 A20 0 A9 A11 A19 0 A8 A10 A18 A10 A7 A9 A17 A9 A6 A8 A16 A8 A5 A7 A15 A7 A4 A6 A14 A6 A3 A5 A13 A5 A2 A4 A12 A4 A1 A3 A11 A3 A0 Address A2 Not used A1 Not used A0 Not used ...

Page 1006: ...ss Pins RAS Cycle CAS Cycle Synchronous DRAM Address Pins Function A14 A13 A21 A21 A11 BANK selects bank address A12 A20 H L A10 Address precharge setting A11 A19 0 A9 A10 A18 0 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 Address A1 Not used A0 Not used ...

Page 1007: ...ns RAS Cycle CAS Cycle Synchronous DRAM Address Pins Function A14 A21 A21 A11 BANK selects bank address A13 A22 H L A10 Address precharge setting A12 A20 0 A9 A11 A19 0 A8 A10 A18 A10 A7 A9 A17 A9 A6 A8 A16 A8 A5 A7 A15 A7 A4 A6 A14 A6 A3 A5 A13 A5 A2 A4 A12 A4 A1 A3 A11 A3 A0 Address A2 Not used A1 Not used A0 Not used ...

Page 1008: ...ss Pins RAS Cycle CAS Cycle Synchronous DRAM Address Pins Function A14 A13 A20 A20 A11 BANK selects bank address A12 A21 H L A10 Address precharge setting A11 A19 0 A9 A10 A18 0 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 Address A1 Not used A0 Not used ...

Page 1009: ... RAS Cycle CAS Cycle Synchronous DRAM Address Pins Function A14 A23 A23 A11 BANK selects bank address A13 A22 H L A10 Address precharge setting A12 A21 0 A9 A11 A20 A11 A8 A10 A19 A10 A7 A9 A18 A9 A6 A8 A17 A8 A5 A7 A16 A7 A4 A6 A15 A6 A3 A5 A14 A5 A2 A4 A13 A4 A1 A3 A12 A3 A0 Address A2 Not used A1 Not used A0 Not used ...

Page 1010: ... Pins RAS Cycle CAS Cycle Synchronous DRAM Address Pins Function A14 A13 A22 A22 A11 BANK selects bank address A12 A21 H L A10 Address precharge setting A11 A20 0 A9 A10 A19 A10 A8 A9 A18 A9 A7 A8 A17 A8 A6 A7 A16 A7 A5 A6 A15 A6 A4 A5 A14 A5 A3 A4 A13 A4 A2 A3 A12 A3 A1 A2 A11 A2 A0 Address A1 Not used A0 Not used ...

Page 1011: ... RAS Cycle CAS Cycle Synchronous DRAM Address Pins Function A14 A22 A22 A11 BANK selects bank address A13 A23 H L A10 Address precharge setting A12 A21 0 A9 A11 A20 A11 A8 A10 A19 A10 A7 A9 A18 A9 A6 A8 A17 A8 A5 A7 A16 A7 A4 A6 A15 A6 A3 A5 A14 A5 A2 A4 A13 A4 A1 A3 A12 A3 A0 Address A2 Not used A1 Not used A0 Not used ...

Page 1012: ... Pins RAS Cycle CAS Cycle Synchronous DRAM Address Pins Function A14 A13 A21 A21 A11 BANK selects bank address A12 A22 H L A10 Address precharge setting A11 A20 0 A9 A10 A19 A10 A8 A9 A18 A9 A7 A8 A17 A8 A6 A7 A16 A7 A5 A6 A15 A6 A4 A5 A14 A5 A3 A4 A13 A4 A2 A3 A12 A3 A1 A2 A11 A2 A0 Address A1 Not used A0 Not used ...

Page 1013: ...le Synchronous DRAM Address Pins Function A16 A24 A24 A13 A15 A23 A23 A12 BANK selects bank address A14 A22 0 A11 A13 A21 H L A10 Address precharge setting A12 A20 0 A9 A11 A19 0 A8 A10 A18 A10 A7 A9 A17 A9 A6 A8 A16 A8 A5 A7 A15 A7 A4 A6 A14 A6 A3 A5 A13 A5 A2 A4 A12 A4 A1 A3 A11 A3 A0 Address A2 Not used A1 Not used A0 Not used ...

Page 1014: ...AS Cycle Synchronous DRAM Address Pins Function A16 A15 A23 A23 A13 A14 A22 A22 A12 BANK selects bank address A13 A21 0 A11 A12 A20 H L A10 Address precharge setting A11 A19 0 A9 A10 A18 0 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 Address A1 Not used A0 Not used ...

Page 1015: ...CAS Cycle Synchronous DRAM Address Pins Function A16 A25 A25 A13 A15 A24 A24 A12 BANK selects bank address A14 A23 0 A11 A13 A22 H L A10 Address precharge setting A12 A21 0 A9 A11 A20 A11 A8 A10 A19 A10 A7 A9 A18 A9 A6 A8 A17 A8 A5 A7 A16 A7 A4 A6 A15 A6 A3 A5 A14 A5 A2 A4 A13 A4 A1 A3 A12 A3 A0 Address A2 Not used A1 Not used A0 Not used ...

Page 1016: ...ycle CAS Cycle Synchronous DRAM Address Pins Function A16 A15 A24 A24 A13 A14 A23 A23 A12 BANK selects bank address A13 A22 0 A11 A12 A21 H L A10 Address precharge setting A11 A20 0 A9 A10 A19 A10 A8 A9 A18 A9 A7 A8 A17 A8 A6 A7 A16 A7 A5 A6 A15 A6 A4 A5 A14 A5 A3 A4 A13 A4 A2 A3 A12 A3 A1 A2 A11 A2 A0 Address A1 Not used A0 Not used ...

Page 1017: ...e CAS Cycle Synchronous DRAM Address Pins Function A15 A23 A23 A12 A14 A22 A22 A11 BANK selects bank address A13 A21 H L A10 Address precharge setting A12 A20 0 A9 A11 A19 0 A8 A10 A18 A10 A7 A9 A17 A9 A6 A8 A16 A8 A5 A7 A15 A7 A4 A6 A14 A6 A3 A5 A13 A5 A2 A4 A12 A4 A1 A3 A11 A3 A0 Address A2 Not used A1 Not used A0 Not used ...

Page 1018: ...Cycle CAS Cycle Synchronous DRAM Address Pins Function A15 A14 A22 A22 A12 A13 A21 A21 A11 BANK selects bank address A12 A20 H L A10 Address precharge setting A11 A19 0 A9 A10 A18 0 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 Address A1 Not used A0 Not used ...

Page 1019: ...e CAS Cycle Synchronous DRAM Address Pins Function A15 A23 A23 A12 BANK selects bank address A14 A22 0 A11 A13 A21 H L A10 Address precharge setting A12 A20 0 A9 A11 A19 0 A8 A10 A18 A10 A7 A9 A17 A9 A6 A8 A16 A8 A5 A7 A15 A7 A4 A6 A14 A6 A3 A5 A13 A5 A2 A4 A12 A4 A1 A3 A11 A3 A0 Address A2 Not used A1 Not used A0 Not used ...

Page 1020: ...Cycle CAS Cycle Synchronous DRAM Address Pins Function A15 A14 A22 A22 A12 BANK selects bank address A13 A21 0 A11 A12 A20 H L A10 Address precharge setting A11 A19 0 A9 A10 A18 0 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 Address A1 Not used A0 Not used ...

Page 1021: ...cle CAS Cycle Synchronous DRAM Address Pins Function A16 A26 A26 A13 A15 A25 A25 A12 BANK selects bank address A14 A24 0 A11 A13 A23 H L A10 Address precharge setting A12 A22 A12 A9 A11 A21 A11 A8 A10 A20 A10 A7 A9 A19 A9 A6 A8 A18 A8 A5 A7 A17 A7 A4 A6 A16 A6 A3 A5 A15 A5 A2 A4 A14 A4 A1 A3 A13 A3 A0 Address A2 Not used A1 Not used A0 Not used ...

Page 1022: ...S Cycle Synchronous DRAM Address Pins Function A17 A26 A26 A14 A16 A25 A25 A13 BANK selects bank address A15 A24 0 A12 A14 A23 0 A11 A13 A22 H L A10 Address precharge setting A12 A21 0 A9 A11 A20 A11 A8 A10 A19 A10 A7 A9 A18 A9 A6 A8 A17 A8 A5 A7 A16 A7 A4 A6 A15 A6 A3 A5 A14 A5 A2 A4 A13 A4 A1 A3 A12 A3 A0 Address A2 Not used A1 Not used A0 Not used ...

Page 1023: ...ins RAS Cycle CAS Cycle Synchronous DRAM Address Pins Function A15 A25 A25 A13 BANK selects bank address A14 A24 A24 A12 A13 A23 0 A11 Address precharge setting A12 A22 H L A10 A11 A21 A11 A9 A10 A20 A10 A8 A9 A19 A9 A7 A8 A18 A8 A6 A7 A17 A7 A5 A6 A16 A6 A4 A5 A15 A5 A3 A4 A14 A4 A2 A3 A13 A3 A1 A2 A12 A2 A0 Address A1 Not used A0 Not used ...

Page 1024: ... RAS Cycle CAS Cycle Synchronous DRAM Address Pins Function A16 A25 A25 A14 BANK selects bank address A15 A24 A24 A13 A14 A23 0 A12 A13 A22 0 A11 A12 A21 H L A10 Address precharge setting A11 A20 0 A9 A10 A19 A10 A8 A9 A18 A9 A7 A8 A17 A8 A6 A7 A16 A7 A5 A6 A15 A6 A4 A5 A14 A5 A3 A4 A13 A4 A2 A3 A12 A3 A1 A2 A11 A2 A0 Address A1 Not used A0 Not used ...

Page 1025: ... Pins RAS Cycle CAS Cycle Synchronous DRAM Address Pins Function A13 A21 A21 A10 BANK selects bank address A12 A20 H L A9 Address precharge setting A11 A19 0 A8 A10 A18 A10 A7 A9 A17 A9 A6 A8 A16 A8 A5 A7 A15 A7 A4 A6 A14 A6 A3 A5 A13 A5 A2 A4 A12 A4 A1 A3 A11 A3 A0 Address A2 Not used A1 Not used A0 Not used ...

Page 1026: ... Cycle Synchronous DRAM Address Pins Function A13 A12 A20 A20 A10 BANK selects bank address A11 A19 H L A9 Address precharge setting A10 A18 0 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 Address A1 Not used A0 Not used Note Example of a synchronous DRAM configuration ...

Page 1027: ... NOP Figure G 1 Instruction Prefetch Figure G 1 depicts a case in which the instruction ADD indicated by the program counter and the instruction at the address H 04000002 are fetched simultaneously The program is assumed to branch to a region other than area 1 after the subsequent JMP instruction and delay slot instruction have been executed In this case a bus access to area 1 instruction prefetch...

Page 1028: ...tions for the timing of RESET and SCK2 Turn off the I O PLL RTC CPG power supply voltage after or at the same time as 1 turning off the internal power supply voltage Note however that the internal power supply voltage may exceed the I O PLL RTC CPG power supply voltage by a maximum of 0 3 V only when the system is being turned off The power supply level must be lowered in compliance with the I O P...

Page 1029: ...208 40 to 85 C HD6417750F167I 1 5 V 128 MHz 20 to 75 C HD6417750VF128 SH7750S 1 95 V 200 MHz 20 to 75 C HD6417750SBP200 BGA 256 20 to 75 C HD6417750SF200 QFP 208 1 8 V 167 MHz 20 to 75 C HD6417750SF167 QFP 208 40 to 85 C HD6417750SF167I 1 5 V 133 MHz 20 to 75 C HD6417750SVF133 30 to 70 C HD6417750SVBT133 CSP 264 SH7750R 1 5 V 240 MHz 20 to 75 C HD6417750RBP240 BGA 256 20 to 75 C HD6417750RF240 QFP...

Page 1030: ...Rev 6 0 07 02 page 980 of 986 ...

Page 1031: ...rray 112 114 117 119 cache fill 108 Data Array 113 115 118 120 IC Index Mode 111 Instruction Cache 95 108 OC Index Mode 107 Operand Cache 95 99 prefetch 122 Prefetch Operation 108 RAM Mode 106 Store Queues 122 Tag 102 110 U bit 102 V bit 102 110 Write Back Buffer 105 Write Through Buffer 105 Clock Oscillation Circuits 247 Bus Clock Division Ratio 258 Changing the Frequency 257 Clock Operating Mode...

Page 1032: ...t Format 161 Geometric Operation Instructions 170 NaN 163 164 Non Numbers 163 Pair Single Precision Data Transfer 172 G General Registers 42 45 Graphics Support Functions 170 H Hitachi User Debug Interface 799 TAP Control 810 I I O Ports 731 Instruction Set 173 179 Arithmetic Operation Instructions 182 Branch instructions 186 214 Data transfer instructions 211 Double precision floating point instr...

Page 1033: ...xecution Cycles 204 211 Parallel Executability 200 Pipeline Stalling 204 Power Down Modes 221 Clock Pause Function 232 Deep Sleep Mode 230 Exit from Standby Mode 232 Hardware Standby Mode 235 High Impedance Control 226 Module Standby Function 233 Pull Up Control 226 Sleep Mode 230 Programming Model 41 Banks 42 Data Formats 41 Privileged Mode 42 R Realtime Clock 267 Alarm Function 288 Crystal Oscil...

Page 1034: ...SCSCMR1 706 SCSCR1 601 708 SCSCR2 665 SCSMR1 599 707 SCSMR2 663 SCSPTR1 609 746 SCSPTR2 679 748 SCSSR1 605 709 SCTDR1 598 SCTSR1 598 SCTSR2 662 SDBPR 805 SDDR 805 SDIR 803 SDMR 362 STBCR 224 STBCR2 227 TCNT 298 TCOR 298 TCPR2 303 TCR 299 TEA 61 TOCR 295 TRA 128 TSTR 296 TTB 61 WCR1 340 WCR2 343 WCR3 351 WTCNT 260 WTCSR 261 Resets 136 H UDI Reset 138 811 Manual Reset 137 Power On Reset 136 Rounding...

Page 1035: ...mulate register high 50 Multiply and accumulate register low 50 PC 50 PR 50 Procedure register 50 Program counter 50 T Timer Unit 291 Auto Reload Count Operation 305 Input Capture Function 307 TCNT Count Timing 306 U User Break Controller 773 Instruction Access Cycle Break 788 Operand Access Cycle Break 789 User Break Debug Support Function 793 User Break Operation Sequence 787 W Watchdog Timer 24...

Page 1036: ...Rev 6 0 07 02 page 986 of 986 ...

Page 1037: ... June 1998 6th Edition July 2002 Published by Business Operation Division Semiconductor Integrated Circuits Hitachi Ltd Edited by Technical Documentation Group Hitachi Kodaira Semiconductor Co Ltd Copyright Hitachi Ltd 1998 All rights reserved Printed in Japan ...

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