Rev. 6.0, 07/02, page 223 of 986
9.1.2
Register Configuration
Table 9.2 shows the registers used for power-down mode control.
Table 9.2
Power-Down Mode Registers
Name
Abbreviation
R/W
Initial Value
P4 Address
Area 7
Address
Access
Size
Standby control
register
STBCR
R/W
H'00
H'FFC00004
H'1FC00004
8
Standby control
register 2
STBCR2
R/W
H'00
H'FFC00010
H'1FC00010
8
Clock stop
register 00
*
CLKSTP00
R/W
H'00000000
H'FE0A0000
H'1E0A0000
32
Clock release
register 00
*
CLKSTPCLR00
W
H'00000000
H'FE0A0008
H'1E0A0008
32
Note:
*
SH7750R only
9.1.3
Pin Configuration
Table 9.3 shows the pins used for power-down mode control.
Table 9.3
Power-Down Mode Pins
Pin Name
Abbreviation
I/O
Function
Processor status 1
Processor status 0
STATUS1
STATUS0
Output
Indicate the processor’s operating status.
(STATUS1, STATUS0)
HH: Reset
HL: Sleep mode
LH: Standby mode
LL: Normal operation
Hardware standby
request
(SH7750S and
SH7750R only)
CA
Input
Transits to hardware standby mode by a
low-level input to the pin.
Notes: H: High level
L: Low level
Summary of Contents for SH7750 series
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