Rev. 6.0, 07/02, page 961 of 986
(7)
BUS 64
(16M: 1M × 8b × 2) × 8 *
AMX 1
AMXEXT 1
16M, column-addr-9bit
16MB
SH7750 Series Address Pins
RAS Cycle
CAS Cycle
Synchronous DRAM
Address Pins
Function
A14
A22
A22
A11
BANK selects bank address
A13
A23
H/L
A10
Address precharge setting
A12
A21
0
A9
A11
A20
A11
A8
A10
A19
A10
A7
A9
A18
A9
A6
A8
A17
A8
A5
A7
A16
A7
A4
A6
A15
A6
A3
A5
A14
A5
A2
A4
A13
A4
A1
A3
A12
A3
A0
Address
A2
Not used
A1
Not used
A0
Not used
Summary of Contents for SH7750 series
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