Rev. 6.0, 07/02, page 921 of 986
CKIO
RD/
D63
–
D0
DACKn
(DA)
Notes:
IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
/
Tm1
Tmd1
Tmd2
Tmd3
Tmd4
t
FMD
t
FMD
t
BSD
t
BSD
t
CSD
t
CSD
t
RDYS
t
RDYH
t
DACD
t
DACD
t
WED1
t
WED1
D3
t
RWD
t
RWD
A
t
WDD
D2
D1
D0
D3
D2
D1
D0
t
WDD
Tm1
Tmd1w
Tmd1
Tmd2w
Tmd2
Tmd3
Tmd4w
Tmd4
t
FMD
t
FMD
t
BSD
t
BSD
t
CSD
t
CSD
t
RDYS
t
RDYH
t
RDYH
t
RDYS
t
DACD
t
DACD
t
WED1
t
WED1
t
RWD
t
RWD
A
t
WDD
t
WDD
1st data bus cycle information
D63
–
D61: Access size
000: Byte
001: Word (2 bytes)
010: Long (4 bytes)
011: Quad (8 bytes)
1xx: Burst (32 bytes)
D25
–
D0: Address
1st data bus cycle information
D63
–
D61: Access size
000: Byte
001: Word (2 bytes)
010: Long (4 bytes)
011: Quad (8 bytes)
1xx: Burst (32 bytes)
D25
–
D0: Address
(1)
(2)
Figure 22.58 MPX Bus Cycle: Burst Write
(1) No Internal Wait
(2) 1st Data (One Internal Wait), 2nd to 4th Data (No Internal Wait + External Wait
Control)
Summary of Contents for SH7750 series
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