Epson S1C31D50, Technical Instructions

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Seiko Epson Corporation
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
P x Port Interrupt Flag Register
Register name Bit Bit name Initial Reset R/W Remarks
PPORTP x INTF 15 – 8 – 0x00 – R –
7 – 0 P x IF[7:0] 0x00 H0 R/W Cleared by writing 1.
*1: This register is effective when the GPIO function is selected.
*2: The bit configuration differs depending on the port group.
Bits 15 – 8 Reserved
Bits 7 – 0 P x IF[7:0]
These bits indicate the port input interrupt cause occurrence status.
1 (R): Cause of interrupt occurred
0 (R): No cause of interrupt occurred
1 (W): Clear flag
0 (W): Ineffective
P x Port Interrupt Control Register
Register name Bit Bit name Initial Reset R/W Remarks
PPORTP x INTCTL 15 – 8 P x EDGE[7:0] 0x00 H0 R/W –
7 – 0 P x IE[7:0] 0x00 H0 R/W
*1: This register is effective when the GPIO function is selected.
*2: The bit configuration differs depending on the port group.
Bits 15 – 8 P x EDGE[7:0]
These bits select the input signal edge to generate a port input interrupt.
1 (R/W): An interrupt will occur at a falling edge.
0 (R/W): An interrupt will occur at a rising edge.
Bits 7 – 0 P x IE[7:0]
These bits enable port input interrupts.
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
Note:
To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared
before enabling interrupts.
P x Port Chattering Filter Enable Register
Register name Bit Bit name Initial Reset R/W Remarks
PPORTP x CHATEN 15 – 8 – 0x00 – R –
7 – 0 P x CHATEN[7:0] 0x00 H0 R/W
*1: The bit configuration differs depending on the port group.
Bits 15 – 8 Reserved
Bits 7 – 0 P x CHATEN[7:0]
These bits enable/disable the chattering filter function.
1 (R/W): Enable (The chattering filter is used.)
0 (R/W): Disable (The chattering filter is bypassed.)