Epson S1C31D50, Technical Instructions

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6-16
Seiko Epson Corporation
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
DMAC Primary-Alternate Set Register
Register name Bit Bit name Initial Reset R/W Remarks
DMACPASET 31 – 0 PASET[31:0] 0x0000
0000
H0 R/W –
Bits 31 – 0 PASET[31:0]
These bits enable the alternate data structures.
1 (W): Enable alternate data structure
0 (W): Ineffective
1 (R): The alternate data structure has been enabled.
0 (R): The primary data structure has been enabled.
Ea ch bit corresponds to a DMAC channel. The high-order bits for the
unimplemented channels are ineffective.
DMAC Primary-Alternate Clear Register
Register name Bit Bit name Initial Reset R/W Remarks
DMACPACLR 31 – 0 PACLR[31:0] – – W –
Bits 31 – 0 PACLR[31:0]
These bits disable the alternate data structures.
1 (W): Disable alternate data structure (The DMACPASET register is cleared to 0.)
0 (W): Ineffective
Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented
channels are ineffective.
DMAC Priority Set Register
Register name Bit Bit name Initial Reset R/W Remarks
DMACPRSET 31 – 0 PRSET[31:0] 0x0000
0000
H0 R/W –
Bits 31 – 0 PRSET[31:0]
These bits increase the priority of each channel.
1 (W): Increase priority
0 (W): Ineffective
1 (R): Priority = High
0 (R): Priority = Normal
Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented
channels are ineffective.
DMAC Priority Clear Register
Register name Bit Bit name Initial Reset R/W Remarks
DMACPRCLR 31 – 0 PRCLR[31:0] – – W –
Bits 31 – 0 PRCLR[31:0]
These bits decrease the priority of each channel.
1(W): Decrease priority (The DMACPRSET register is cleared to 0.)
0 (W): Ineffective
Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented
channels are ineffective.