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Epson S1C31D50, Technical Instructions

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15-13

 

Seiko Epson Corporation

 

S1C31D50 TECHNICAL MANUAL

 

(Rev. 1.00)

 

 

 

15.5.4.

 

Data Transmission in Master Mode 

 

A data sending procedure and operations in master mode are shown below. Figures 15.5.4.1 and 
15.5.4.2 show a timing chart and a flowchart, respectively. 

 

Data sending procedure 

 

1.

 

Set the QSPI_

n

CTL.DIR bit to 0 when QSPI Ch.

n 

is set to dual or quad transfer mode. (This 

setting is not necessary in single transfer mode.) 

2.

 

Assert the slave select signal for the external slave device to be accessed by controlling the 
QSPI_

n

CTL. MSTSSO bit or the general-purpose output port used for an extra slave select signal 

output (if necessary). 

3.

 

Check to see if the QSPI_

n

INTF.TBEIF bit is set to 1 (transmit buffer empty). 

4.

 

Write transmit data to the QSPI_

n

TXD register. 

5.

 

Wait for a QSPI interrupt when using interrupt. 

6.

 

Repeat Steps 3 to 5 (or 3 and 4) until the end of transmit data. 

7.

 

Negate the slave select signal that has been asserted in Step 2 by controlling the 
QSPI_

n

CTL.MSTSSO bit or the general-purpose output port (if necessary). 

 

Data sending operations 

QSPI Ch.

n 

starts data sending operations when transmit data is written into the QSPI_

n

TXD register. 

The transmit data in the QSPI_

n

TXD register is automatically transferred to the shift register and 

the QSPI_ 

n

INTF.TBEIF bit is set to 1. If the QSPI_

n

INTE.TBEIE bit = 1 (transmit buffer empty 

interrupt enabled), a transmit buffer empty interrupt occurs at the same time. 
The QSPICLK

n 

pin outputs clocks for the number of cycles specified by the QSPI_

n

MOD.CHLN[3:0] 

bits and the transmit data bits are output in sequence from the QSDIO

n 

pins, according to the transfer 

mode specified by the QSPI_

n

MOD.TMOD[1:0] bits, in sync with these clocks. 

Even if the clock is being output from the QSPICLK

n 

pin, the next transmit data can be written to 

the QSPI_ 

n

TXD register after making sure the QSPI_

n

INTF.TBEIF bit is set to 1. 

If transmit data has not been written to the QSPI_

n

TXD register after the last clock is output from 

the QSPI- CLK

n 

pin, the clock output halts and the QSPI_

n

INTF.TENDIF bit is set to 1. At the same 

time QSPI issues an end-of-transmission interrupt request if the QSPI_

n

INTE.TENDIE bit = 1. 

 

 

Figure 15.5.4.1  Example of Data Sending Operations in Master Mode (QSPI_

n

MOD.CHDL[3:0] bits = 

QSPI_

n

MOD.CHLN[3:0] bits = 0x3) 

 

Data (W) 

→

 QSPI_

n

TXD

 

Data (W) 

→

 QSPI_

n

TXD

 

Data (W) 

→

 QSPI_

n

TXD

 

1 (W) 

→

 QSPI_

n

INTF.TENDIF

 

2

 

3

 

4

 

1

 

2

 

3

 

4

 

1

 

2

 

3

 

4

 

1

 

QSDIO

n

[3:0]

 

QSPI_

n

INTF.TBEIF

 

QSPI_

n

INTF.TENDIF

 

Software operations

 

QSPICLK

n

 

Summary of Contents for S1C31D50

Page 1: ...Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL Rev 1 00 CMOS 32 BIT SINGLE CHIP MICROCONTROLLER S1C31D50 Technical Manual Rev 1 00 ...

Page 2: ...t assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and further there is no representation that this material is applicable to products requiring high level reliability such as medical products Moreover no license to any intellectual property rights is granted by implication or otherwise and there ...

Page 3: ...5 0 bits R W Read write bit R WP Read write bit with a write protection using the SYSPROT PROT 15 0 bits reserved Reserved bit Do not alter from the initial value Control bit read write values This manual describes control bit values in a hexadecimal notation except for one bit values and except when decimal or binary notation is required in terms of explanation The values are described as shown b...

Page 4: ...__________________________________________________ 2 7 2 3 2 Input Output Pins ______________________________________________________ 2 8 2 3 3 Clock Sources __________________________________________________________ 2 9 2 3 4 Operations ___________________________________________________________ 2 12 2 4 Operating Mode ___________________________________________________ 2 18 2 4 1 Initial Boot Se...

Page 5: ...End Pointer _______________________________________________ 6 4 6 4 2 Transfer Destination End Pointer ___________________________________________ 6 4 6 4 3 Control Data ___________________________________________________________ 6 4 6 5 DMA Transfer Mode _________________________________________________ 6 6 6 5 1 Basic Transfer __________________________________________________________ 6 6 6 5 2 ...

Page 6: ..._______________________________________ 7 25 7 7 13 Common Registers between Port Groups___________________________________ 7 26 8 Universal Port Multiplexer UPMUX __________________________________ 8 1 8 1 Overview __________________________________________________________ 8 1 8 2 Peripheral Circuit I O Function Assignment _______________________________ 8 1 8 3 ControlRegisters _________________...

Page 7: ...___________ 11 6 11 5 2 SVD3 Reset ___________________________________________________________ 11 6 11 6 ControlRegisters _________________________________________________ 11 7 12 16 bit Timers T16 _____________________________________________ 12 1 12 1 Overview _______________________________________________________ 12 1 12 2 Input Pin _______________________________________________________ 12 1 ...

Page 8: ..._________ 13 12 13 8 DMA Transfer Requests___________________________________________ 13 12 13 9 ControlRegisters ________________________________________________ 13 13 14 Synchronous Serial Interface SPIA ________________________________ 14 1 14 1 Overview _______________________________________________________ 14 1 14 2 Input Output Pins and External Connections __________________________ 14 2 1...

Page 9: ...5 27 15 5 8 Terminating Data Transfer in Master Mode ________________________________ 15 27 15 5 9 Data Transfer in Slave Mode ____________________________________________ 15 28 15 5 10 Terminating Data Transfer in Slave Mode ________________________________ 15 29 15 6 Interrupts _____________________________________________________ 15 30 15 7 DMA Transfer Requests_________________________________...

Page 10: ...________ 17 24 17 6 DMA Transfer Requests___________________________________________ 17 24 17 7 ControlRegisters ________________________________________________ 17 25 18 IR Remote Controller REMC3 ____________________________________ 18 1 18 1 Overview _______________________________________________________ 18 1 18 2 Output Pins and External Connections ________________________________ 18 2 18 2 ...

Page 11: ..._____________________________________ 20 3 20 3 2 Clock Supply in SLEEP Mode______________________________________________ 20 3 20 3 3 Clock Supply in DEBUG Mode ____________________________________________ 20 3 20 4 Operations ______________________________________________________ 20 4 20 4 1 Initialization___________________________________________________________ 20 4 20 4 2 Operating Modes____...

Page 12: ...1 32 21 5 9 Memory Check Error __________________________________________________ 21 33 21 5 10 Memory Check Interrupt Masking _____________________________________ 21 33 21 5 11 Memory Check Function Registers _____________________________________ 21 34 21 6 ControlRegisters ________________________________________________ 21 36 22 Peripheral Circuit Control Registers ____________________________...

Page 13: ...Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL Rev 1 00 26 Appendix _____________________________________________________ 26 1 ...

Page 14: ... Play FUNCTION Sound Algorithm EPSON high quality High compress algorithm Playchannels 2ch mixing support suitable for background music Voice play Sampling Frequency 15 625kHz suitable for background music Voice play Bitrate 16 24 32 40 kbps Voice Speed Conversion 75 125 5 step Self Memory Check FUNCTION On Chip RAM Check W R Check MARCH C On Chip Flash check Checksum CRC External SPI Flash Check ...

Page 15: ...ay day of the week month year counters Theoretical regulation function for 1 second correction Alarm and stopwatch functions 16 bit timer T16 8 channels Generates the SPIA and QSPI master clocks and the ADC12A operating clock trigger signal 16 bit PWM timer T16B 2 channels Event counter capture function PWM waveform generation function Number of PWM output or capture input ports 4 ports channel Su...

Page 16: ... Operating temperature range 40 to 85 C Current consumption Typ value SLEEPmode 1 0 46 µA IOSC OFF OSC1 OFF OSC3 OFF 0 95 µA IOSC OFF OSC1 32 768 kHz crystal oscillator OSC3 OFF RTCA ON HALT mode 2 1 8 µA IOSC OFF OSC1 32 768 kHz crystal oscillator OSC3 OFF RUN mode 250 µA MHz VD1 voltage mode mode0 CPU IOSC 155 µA MHz VD1 voltage mode mode1 CPU IOSC Shipping form 1 TQFP12 48 7mm x 7mm 0 5mm pitch...

Page 17: ...er SRC Power on reset Brown out reset POR BOR Power generator PWGA System clock Interrupt signal DMA request Cache controller Cache RAM 512 bytes 12bit A D convertor ADC12A 1 Ch ADIN00 07 I O port23 PPORT I O portOthers PPORT VREFA0 RESET EXCL00 01 CAP10 13 SDACOUT_P SDACOUT_N P00 07 P10 17 ADTRG QSDIO00 03 QSPICLK0 QSPISS0 SDI0 2 SDO0 2 SPICLK0 2 USIN0 2 SPISS0 2 SDA0 2 SCL0 2 USOUT0 2 P20 27 P30...

Page 18: ...5 ADTRG OSC1 39 22 P40 VREFA OSC2 40 21 P17 UPMUX ADIN0 P83 EXOSC 41 20 P16 UPMUX ADIN1 P84 EXCL00 42 19 P15 UPMUX ADIN2 P85 EXCL01 43 18 P14 UPMUX ADIN3 P72 EXCL10 44 17 P13 UPMUX ADIN4 P73 EXCL11 45 16 P06 UPMUX SWCLK PD0 46 15 P05 UPMUX SWD PD1 47 14 P04 UPMUX TEST 48 13 P03 UPMUX 1 2 3 4 5 6 7 8 9 10 11 12 P30 RFCLKO0 UPMUX P31 REMO UPMUX P32 CLPLS UPMUX VPP P90 QSPICLK0 P91 QSDIO00 P92 QSDIO0...

Page 19: ...EFA P82 54 27 P17 UPMUX ADIN0 P83 EXOSC 55 26 P16 UPMUX ADIN1 P84 EXCL00 56 25 P15 UPMUX ADIN2 P85 EXCL01 57 24 P14 UPMUX ADIN3 P70 58 23 P13 UPMUX ADIN4 P71 59 22 P12 UPMUX ADIN5 P72 EXCL10 60 21 P11 UPMUX ADIN6 P73 EXCL11 61 20 P06 UPMUX SWCLK PD0 62 19 P05 UPMUX SWD PD1 63 18 P04 UPMUX TEST 64 17 P03 UPMUX 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 P30 RFCLKO0 UPMUX P31 REMO UPMUX P32 CLPLS UPMUX P...

Page 20: ...SC 68 33 P17 UPMUX ADIN0 P84 EXCL00 69 32 P16 UPMUX ADIN1 P85 EXCL01 70 31 P15 UPMUX ADIN2 P86 71 30 P14 UPMUX ADIN3 P87 72 29 P13 UPMUX ADIN4 P70 73 28 P12 UPMUX ADIN5 P71 74 27 P11 UPMUX ADIN6 P72 EXCL10 75 26 P10 UPMUX ADIN7 P73 EXCL11 76 25 P07 UPMUX P74 77 24 P06 UPMUX SWCLK PD0 78 23 P05 UPMUX SWD PD1 79 22 P04 UPMUX TEST 80 21 P03 UPMUX 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PD4...

Page 21: ...N0 P84 EXCL00 86 40 P16 UPMUX ADIN1 P85 EXCL01 87 39 P15 UPMUX ADIN2 P86 88 38 P14 UPMUX ADIN3 P87 89 37 P13 UPMUX ADIN4 P70 90 36 P12 UPMUX ADIN5 P71 91 35 P11 UPMUX ADIN6 P72 EXCL10 92 34 P10 UPMUX ADIN7 P73 EXCL11 93 33 P07 UPMUX P74 94 32 P06 UPMUX P75 95 31 P05 UPMUX SWCLK PD0 96 30 P04 UPMUX SWD PD1 97 29 P03 UPMUX TEST 98 28 P02 UPMUX P76 99 27 P01 UPMUX P77 100 26 P00 UPMUX 1 2 3 4 5 6 7 8...

Page 22: ...D1 A VD1 Regulator Output VDDQSPI VDDQSPI P SPI interface voltage supply OSC1 OSC1 A OSC1 oscillator input OSC2 OSC2 A OSC1 oscillator output TEST TEST I I Pull down Test mode enable RESET RESET I I Pull up Reset input P00 P00 I O Hi Z I O port UPMUX User selected I O universal port multiplexer P01 P01 I O Hi Z I O port UPMUX User selected I O universal port multiplexer P02 P02 I O Hi Z I O port U...

Page 23: ...ser selected I O universal port multiplexer P23 P23 I O Hi Z I O port RFIN0 R F converter Ch 0 oscillation input UPMUX User selected I O universal port multiplexer P24 P24 I O Hi Z I O port UPMUX User selected I O universal port multiplexer P25 P25 I O Hi Z I O port UPMUX User selected I O universal port multiplexer P26 P26 I O Hi Z I O port UPMUX User selected I O universal port multiplexer P27 P...

Page 24: ...O Hi Z I O port P61 P61 I O Hi Z I O port EXSVD0 Supply voltage detector external voltage detection input 0 P62 P62 I O Hi Z I O port EXSVD1 Supply voltage detector external voltage detection input 1 P63 P63 I O Hi Z I O port P64 P64 I O Hi Z I O port P65 P65 I O Hi Z I O port P66 P66 I O Hi Z I O port P67 P67 I O Hi Z I O port P70 P70 I O Hi Z I O port P71 P71 I O Hi Z I O port P72 P72 I O Hi Z I...

Page 25: ...P95 I O Hi Z I O port QSPISS0 Quad synchronous serial interface Ch 0 slave select input output PA0 PA0 I O Hi Z I O port PA1 PA1 I O Hi Z I O port PA2 PA2 I O Hi Z I O port PA3 PA3 I O Hi Z I O port FOUT Clock external output PA4 PA4 I O Hi Z I O port PA5 PA5 I O Hi Z I O port PA6 PA6 I O Hi Z I O port PD0 SWCLK I O Pull up Serial wire debugger clock input default PD0 I O port PD1 SWD I O Pull up ...

Page 26: ...t output SDAn I O I2C Ch n data input output UART USINn I n 0 1 2 UART Ch n data input USOUTn O UART Ch n data output SPI SDIn I n 0 1 2 SPIA ch n data input SDOn O SPIA ch n data output SPICLKn I O SPIA Ch n clock input output SPISSn I SPIA Ch n slave select input PWM timer TOUTn0 CAPn0 I O n 0 1 16 bit PWM timer Ch n PWM output capture input 0 TOUTn1 CAPn1 I O 16 bit PWM timer Ch n PWM output ca...

Page 27: ...5 QSPISS0 18 15 13 11 VDDQSPI VDDQSPI 19 16 PA0 PA0 20 17 14 PA1 PA1 21 18 15 PA2 PA2 22 19 16 12 PA3 PA3 FOUT 23 20 PA4 PA4 24 PA5 PA5 25 PA6 PA6 26 P00 P00 UPMUX 27 P01 P01 UPMUX 28 P02 P02 UPMUX 29 21 17 13 P03 P03 UPMUX 30 22 18 14 P04 P04 UPMUX 31 23 19 15 P05 P05 UPMUX 32 24 20 16 P06 P06 UPMUX 33 25 P07 P07 UPMUX 34 26 P10 P10 UPMUX ADIN7 35 27 21 P11 P11 UPMUX ADIN6 36 28 22 P12 P12 UPMUX ...

Page 28: ...4 32 P51 P51 SDACOUT_N 68 55 P52 P52 69 56 P53 P53 70 P54 P54 71 P55 P55 72 57 45 33 PD2 PD2 OSC3 73 58 46 34 PD3 PD3 OSC2 74 59 47 35 VD1 VD1 75 60 48 36 VSS VSS 76 61 49 37 RESET RESET 77 62 50 38 VDD VDD 78 63 51 39 OSC1 OSC1 79 64 52 40 OSC2 OSC2 80 P56 P56 81 P57 P57 82 65 P80 P80 83 66 53 P81 P81 84 67 54 P82 P82 85 68 55 41 P83 P83 EXOSC 86 69 56 42 P84 P84 EXCL00 87 70 57 43 P85 P85 EXCL01...

Page 29: ...internal circuits this makes it possible to keep current consumption constant independent of the VDD voltage level The VD1 regulator supports two operation modes normal mode and economy mode and setting the VD1 regulator into economy mode at light loads helps achieve low power operations The VD1 regulator supports two voltage modes mode0 and mode1 and setting the VD1 regulator into mode1 during lo...

Page 30: ...lator supports two operation modes normal mode and economy mode Setting the VD1 regulator into economy mode at light loads helps achieve low power operations Table 2 1 3 1 lists examples of light load conditions in which economy mode can be set Table 2 1 3 1 Examples of Light Load Conditions in which Economy Mode Can be Set Light load condition Exceptions SLEEP mode when all oscillators are stoppe...

Page 31: ...ACTL REGDIS bit to 1 Discharge Set the PWGACTL REGMODE 1 0 bits to 0x2 Set to normal mode 6 Configure the following PWGACTL register bits after the system clock supply has resumed Set the PWGACTL REGDIS bit to 0 Stop discharging Set the PWGACTL REGMODE 1 0 bits to 0x0 Set to automatic mode 7 Write a value other than 0x0096 to the SYSPROT PROT 15 0 bits Set system protection Procedure to switch fro...

Page 32: ...th an appropriate initialization condition ac cording to changes in status Figure 2 2 1 1 shows the SRC configuration Figure 2 2 1 1 SRC Configuration 2 2 2 Input Pin Table 2 2 2 1 shows the SRC pin Table 2 2 2 1 SRC Pin Pin name I O Initial status Function RESET I I Pull up Reset input The RESET pin is connected to the noise filter that removes pulses not conforming to the requirements An interna...

Page 33: ...s configured to a reset input issues a reset re quest This function must be enabled using an I O port register For more information refer to the I O Ports chapter Watchdog timer reset Setting the watchdog timer into reset mode will issue a reset request when the counter overflows This helps re turn the runaway CPU to a normal operating state For more information refer to the Watchdog timer chapter...

Page 34: ...ers and control bits refer to the CPU and Debugger chapter or Control Registers in each peripheral circuit chapter Table 2 2 4 1 List of Reset Groups Reset group Reset source Reset cancelation timing H0 RESET pin POR and BOR Reset request from the CPU Key entry reset Supply voltage detector reset Watchdog timer reset Reset state is maintained for the reset hold time tRSTR after the reset request i...

Page 35: ...put circuit that allows input of square wave and sine wave clock signals up to 16 MHz The system clock SYSCLK which is used as the operating clock for the CPU and bus and the peripheral circuit operating clocks can be configured individually by selecting the suitable clock source and division ratio Controls the oscillator and clock input circuits to enable disable according to the operating mode R...

Page 36: ...C1 oscillator circuit output OSC3 A OSC3 oscillator circuit input OSC4 A OSC3 oscillator circuit output EXOSC I I EXOSC clock input FOUT O O L FOUT clock output Peripheral circuit n Peripheral circuit 1 IOSCEN CLKSRC 1 0 CLKDIV 1 0 WUPMD WUPSRC 1 0 WUPDIV 1 0 FOUTDIV 2 0 IOSC oscillator circuit Divider Clock selector System clock controller OSC1EN OSC1 oscillator circuit Divider OSC3EN OSC3 oscill...

Page 37: ...m two different types shown below Figure 2 3 3 2 shows the configuration of the OSC1 oscillator circuit Figure 2 3 3 2 OSC1 Oscillator Circuit Configuration IOSCEN Clock oscillator Oscillation stabilization waiting circuit Interrupt control circuit CPU core IOSCSTAIE IOSCSTAIF IOSCFQ 1 0 IOSCCLK IOSC oscillator circuit Internal data bus Oscillation startup control circuit OSC1 oscillator circuit v...

Page 38: ... the oscillation characteristics refer to the Basic External Connection Diagram chapter and OSC1 oscillator circuit characteristics in the Electrical Characteristics chapter respectively OSC3 oscillator circuit The OSC3 oscillator circuit is a crystal ceramic oscillator internal oscillator that generates a high speed clock Figure 2 3 3 3 shows the configuration of the OSC3 oscillator circuit Figur...

Page 39: ...and OSC3 oscillator circuit characteristics in the Electrical Characteristics chapter respectively EXOSC clock input EXOSC is an external clock input circuit that supports square wave and sine wave clocks Figure 2 3 3 4 shows the configuration of the EXOSC clock input circuit Figure 2 3 3 4 EXOSC Clock Input Circuit EXOSC has no oscillation stabilization waiting circuit included therefore it must ...

Page 40: ...tion stabilization waiting time is set properly and the clock is stabilized immediately after the oscillation starts or not monitor the oscillation clock using the FOUT output function The oscillation stabilization waiting time for the IOSC oscillator circuit is fixed at 16 IOSCCLK clocks The oscillation stabilization waiting time for the OSC1 oscillator circuit should be set to 16 384 OSC1CLK clo...

Page 41: ...rtup boosting operation Furthermore the oscillation start time being actually reduced depends on the characteristics of the resonator used Figure 2 3 4 2 shows an operation example when the oscillation start up control circuit is used 1 CLGOSC1 OSC1BUP bit 0 startup boosting operation disabled 2 CLGOSC1 OSC1BUP bit 1 startup boosting operation enabled Figure 2 3 4 2 Operation Example when the Osci...

Page 42: ...lear interrupt flag 2 Write 1 to the CLGINTE OSC1STAIE bit Enable interrupt 3 Write 0x0096 to the SYSPROT PROT 15 0 bits Remove system protection 4 Configure the following CLGOSC1 register bits CLGOSC1 OSC1SELCR bit Select oscillator type CLGOSC1 OSC1WT 1 0 bits Set oscillation stabilization waiting time In addition to the above configure the following bits when using the crystal oscillator CLGOSC...

Page 43: ...o start oscillation of the OSC3 oscillator circuit 1 Write 1 to the CLGINTF OSC3STAIF bit Clear interrupt flag 2 Write 1 to the CLGINTE OSC3STAIE bit Enable interrupt 3 Write 0x0096 to the SYSPROT PROT 15 0 bits Remove system protection 4 Configure the following CLGOSC3 register bits CLGOSC3 OSC3WT 2 0 bits Set oscillation stabilization waiting time CLGOSC3 OSC3MD bits Set CR oscillation mode 5 Wr...

Page 44: ...trol Example in SLEEP Mode SLEEP mode CPU stop CLK stop IOSCCLK Unstable IOSCCLK SYSCLK CPU operating clock IOSCCLK CLK stop OSC1CLK Unstable OSC1CLK Real time clock operating clock OSC1CLK Executing the WFI WFE instruction SLEEPDEEP bit 1 Executing the WFI WFE instruction SLEEPDEEP bit 1 The real time clock is turned off in SLEEP mode as the clock stops SLEEP mode CPU stop CLK stop IOSCCLK Unstab...

Page 45: ...Clear interrupt flag 5 Configure the following CLGINTF register bits Set the CLGINTE OSC3TEDIE bit to 1 Enable interrupt Set the CLGINTE OSC3TERIE bit to 1 Enable interrupt 6 Write 1 to the CLGOSC3 OSC3STM bit Enable OSC3 oscillation auto trimming 7 Write a value other than 0x0096 to the SYSPROT PROT 15 0 bits Set system protection After the trimming operation has completed the CLGIOSC OSC3STM bit...

Page 46: ...om the system reset controller is canceled RUN mode is classified into IOSC RUN OSC1 RUN OSC3 RUN and EXOSC RUN by the SYSCLK clock source HALT mode When the Cortex M0 core executes the WFI or WFE instruction with the SLEEPDEEP bit of the system control register set to 0 it suspends program execution and stops operating This state is referred to HALT mode in this IC In this mode the clock sources ...

Page 47: ...required power consumption can be less than HALT mode Figure 2 4 2 1 Operating Mode to Mode State Transition Diagram Canceling HALT or SLEEP mode The conditions listed below generate the HALT SLEEP cancelation signal to cancel HALT or SLEEP mode and put the CPU into RUN mode Interrupt request from a peripheral circuit NMI from the watchdog timer Reset request IOSC RUN IOSC HALT RESET Initial state...

Page 48: ...CLGINTF OSC3STAIF When the OSC3 oscillation stabilization waiting operation has completed after the oscillation starts Writing 1 OSC3 oscillation auto trimming error CLGINTF OSC3TERIF When the OSC3 oscillation auto trimming operation has terminated due to an error Writing 1 OSC1 oscillation stop CLGINTF OSC1STPIF When OSC1CLK is stopped or when the CLGOSC OSC1EN or CLGOSC1 OSDEN bit setting is alt...

Page 49: ...0x0 H0 R WP Bits 15 6 Reserved Bit 5 REGDIS This bit enables the VD1 regulator discharge function 1 R WP Enable 0 R WP Disable Bit 4 REGSEL This bit controls the VD1 regulator voltage mode 1 R WP mode0 0 R WP mode1 Bits 3 2 Reserved Bits 1 0 REGMODE 1 0 These bits control the VD1 regulator operating mode Table 2 6 1 Internal Regulator Operating Mode PWGACTL REGMODE 1 0 bits Operating mode 0x3 Econ...

Page 50: ...hese bits select the SYSCLK clock source for resetting the CLGSCLK CLKSRC 1 0 bits at wake up When a currently stopped clock source is selected it will automatically start oscillating or clock input at wake up However this setting is ineffective when the CLGSCLK WUPMD bit 0 Table 2 6 2 SYSCLK Clock Source and Division Ratio Settings at Wake up CLGSCLK WUPDIV 1 0 bits CLGSCLK WUPSRC 1 0 bits 0x0 0x...

Page 51: ...ion state before SLEEP Each bit corresponds to the clock source as follows CLGOSC EXOSCSLPC bit EXOSC clock input CLGOSC OSC3SLPC bit OSC3 oscillator circuit CLGOSC OSC1SLPC bit OSC1 oscillator circuit CLGOSC IOSCSLPC bit IOSC oscillator circuit Bits 7 4 Reserved Bit 3 EXOSCEN Bit 2 OSC3EN Bit 1 OSC1EN Bit 0 IOSCEN These bits control the clock source operation 1 R W Start oscillating or clock inpu...

Page 52: ... 7 5 0x0 R 4 0 R 3 2 0 R 1 0 IOSCFQ 1 0 0x2 H0 R WP Bits 15 5 Reserved Bit 4 Reserved Bits 3 2 Reserved Bits 1 0 IOSCFQ 1 0 These bits select the IOSCCLK frequency Table 2 6 4 IOSCCLK Frequency Selection CLGIOSC IOSCFQ 1 0 bits IOSCCLK frequency VD1 voltage mode mode0 VD1 voltage mode mode1 0x3 Setting prohibited 0x2 8 MHz 0x1 2 0 MHz 1 8 MHz 0x0 1 0 MHz 0 9 MHz ...

Page 53: ...C1 oscillation stop detector on 0 R WP OSC1 oscillation stop detector off Note Do not write 1 to the CLGOSC1 OSDEN bit before stabilized OSC1CLK is supplied Further more the CLGOSC1 OSDEN bit should be set to 0 when the CLGOSC OSC1EN bit is set to 0 Bit 12 OSC1BUP This bit enables the oscillation startup control circuit in the OSC1 oscillator circuit 1 R WP Enable Activate booster operation at sta...

Page 54: ...n the CLGOSC1 INV1N 1 0 bits Bits 5 4 INV1N 1 0 These bits set the oscillation inverter gain applied at normal operation of the OSC1 oscillator circuit Table 2 6 7 Setting Oscillation Inverter Gain at OSC1 Normal Operation CLGOSC1 INV1N 1 0 bits Inverter gain 0x3 Max Min 0x2 0x1 0x0 Bits 3 2 Reserved Bits 1 0 OSC1WT 1 0 These bits set the oscillation stabilization waiting time for the OSC1 oscilla...

Page 55: ... 6 Reserved Bits 5 4 OSC3INV 1 0 These bits set the oscillation inverter gain when crystal ceramic oscillator is selected as the OSC3 oscillator type Table 2 6 11 OSC3 Oscillation Inverter Gain Setting CLGOSC3 OSC3INV 1 0 bits Inverter gain 0x3 Max Min 0x2 0x1 0x0 Bit 3 OSC3STM This bit controls the OSC3CLK auto trimming function 1 WP Start trimming 0 WP Stop trimming 1 R Trimming is executing 0 R...

Page 56: ...H0 R W 0 IOSCSTAIF 0 H0 R W Bits 15 9 7 6 3 Reserved Bit 8 OSC3TERIF Bit 5 OSC1STPIF Bit 4 OSC3TEDIF Bit 2 OSC3STAIF Bit 1 OSC1STAIF Bit 0 IOSCSTAIF These bits indicate the CLG interrupt cause occurrence statuses 1 R Cause of interrupt occurred 0 R No cause of interrupt occurred 1 W Clear flag 0 W Ineffective Each bit corresponds to the interrupt as follows CLGINTF OSC3TERIF bit OSC3 oscillation a...

Page 57: ...e bits enable the OSC1 oscillation stop and OSC3 oscillation auto trimming completion interrupts 1 R W Enable interrupts 0 R W Disable interrupts Each bit corresponds to the interrupt as follows CLGINTE OSC3TERIE bit OSC3 oscillation auto trimming error interrupt CLGINTE OSC1STPIE bit OSC1 oscillation stop interrupt CLGINTE OSC3TEDIE bit OSC3 oscillation auto trimming completion interrupt CLGINTE ...

Page 58: ... 1 0 bits 0x0 0x1 0x2 0x3 IOSCCLK OSC1CLK OSC3CLK SYSCLK 0x7 1 128 1 32 768 1 128 Reserved 0x6 1 64 1 4 096 1 64 Reserved 0x5 1 32 1 1 024 1 32 Reserved 0x4 1 16 1 256 1 16 Reserved 0x3 1 8 1 8 1 8 Reserved 0x2 1 4 1 4 1 4 Reserved 0x1 1 2 1 2 1 2 Reserved 0x0 1 1 1 1 1 1 1 1 Note When the CLGFOUT FOUTSRC 1 0 bits are set to 0x3 the FOUT output will be stopped in SLEEP HALT mode as SYSCLK is stopp...

Page 59: ...le 3 3 3 1 lists the debug pins Table 3 3 1 1 List of Debug Pins Pin name I O Initial state Function SWCLK I I On chip debugger clock input pin Input a clock from a debugging tool SWD I O I On chip debugger data input output pin Used to input output debugging data The debugger input output pins are shared with general purpose I O ports and are initially set as the debug pins If the debugging funct...

Page 60: ... 0xf01f_ffff Reserved 0xf000_1000 0xf000_0fff System ROM table 4K bytes Device size 32 bits 0xf000_0000 0xefff_ffff Cortex M0 private peripherals 0xe000_0000 0xdfff_ffff Reserved 0x0020_4000 0x0020_3fff Peripherals 12KB 32bit 0x0020_1000 0x0020_0fff Peripherals 4KB 16bit 0x0020_0000 0x001f_ffff Reserved 0x0015_6800 0x0015_67ff Voice RAM area 14K bytes Device size 32 bits 0x0015_3000 0x0015_2fff Re...

Page 61: ...ripheral circuits that can be accessed in one cycle Access size Access size designated by the CPU instructions e g LDR Rt Rn 32 bit data transfer Table 4 2 1 lists numbers of bus access cycles by different device size and access size The peripheral circuits can be accessed with an 8 or 16 bit instruction Table 4 2 1 Number of Bus Access Cycles Device size Access size Number of bus access cycles 8 ...

Page 62: ...is a limit of frequency to access the Flash memory with no wait cycle therefore the number of bus access cycles for reading must be changed according to the system clock frequency The number of bus access cycles for reading can be configured using the FLASHCWAIT RDWAIT 1 0 bits Select a setting for higher frequency than the system clock 4 3 3 Flash Programming The Flash memory supports on board pr...

Page 63: ...tify the registers and bits with write protection Note Once write protection is removed using the SYSPROT PROT 15 0 bits write enabled status is maintained until write protection is applied again After the registers bits required have been al tered apply write protection 4 6 Instruction Cache This IC includes an instruction cache Enabling the cache function translates into reduced current consumpt...

Page 64: ... R 7 2 0x00 R 1 reserved 1 R 0 CACHEEN 0 H0 R W Bits 15 1 Reserved Bit 0 CACHEEN This bit enables the instruction cache function 1 R W Enable instruction cache 0 R W Disable instruction cache FLASHC Flash Read Cycle Register Register name Bit Bit name Initial Reset R W Remarks FLASHCWAIT 15 9 0x00 R 8 reserved 0 H0 R WP 7 2 0x00 R 1 0 RDWAIT 1 0 0x1 H0 R WP Bits 15 2 Reserved Bits 1 0 RDWAIT 1 0 T...

Page 65: ... detailed information on the NVIC refer to the Cortex M0 Technical Reference Manual Figure 5 1 1 shows the configuration of the interrupt system Figure 5 1 1 Configuration of Interrupt System CPU core Clock Generator NVIC Watchdog timer Peripheral circuit Interrupt request Peripheral circuit Interrupt request NMI IRQn IRQ0 HALT SLEEP cancelation signal ...

Page 66: ...em Reserved 9 0x24 System Reserved 10 0x28 System Reserved 11 0x2c CPU SV call SVC instruction Configurable 12 0x30 System Reserved 13 0x34 System Reserved 14 0x38 CPU PendSV Configurable 15 0x3c Sys Tick SysTick timer underflow 16 0 0x40 DMA DMA controller interrupt Transfer complete Transfer error 17 1 0x44 SVD Supply voltage detector interrupt Power supply voltage drop detection 18 2 0x48 PORT01...

Page 67: ...6B CH1 16 bit PWM timer Ch 1 interrupt Capture overwrite Compare capture Counter MAX Counter zero 31 15 0x7c UART CH1 UART Ch 1 interrupt End of transmission Framing error Parity error Overrun error Receive buffer two bytes full Receive buffer one byte full Transmit buffer empty 32 16 0x80 T16 CH2 16 bit timer Ch 2 interrupt Underflow 33 17 0x84 QSPI Quad synchronous serial interface Ch 0 interrupt En...

Page 68: ...converter interrupt Analog input signal m A D conversion completion Analog input signal m A D conversion result overwrite error 43 27 0xac SPI CH2 Synchronous serial interface Ch 2 interrupt End of transmission Receive buffer full Transmit buffer empty Overrun error T16_CH7 16 bit timer Ch 7 interrupt Underflow 44 28 0xb0 I2C CH2 I2C Ch 2 interrupt End of data transfer General call address reception ...

Page 69: ... 5 3 Peripheral Circuit Interrupt Control The peripheral circuit that generates interrupts includes an interrupt enable bit and an interrupt flag for each interrupt cause Interrupt flag The flag is set to 1 when the interrupt cause occurs The clear condition depends on the peripheral circuit Interrupt enable bit By setting this bit to 1 interrupt enabled an interrupt request will be sent to the CP...

Page 70: ... 6 1 1 shows the configuration of the DMAC Table 6 1 1 DMAC Channel Configuration of S1C31D50 Item S1C31D50 Number of channels 4 channels Ch 0 to Ch 3 Transfer source memories Internal Flash memory external Flash memory RAM Transfer destination memories RAM Transfer source peripheral circuits UART3 SPIA QSPI I2C T16B ADC12A Transfer destination peripheral circuits UART3 SPIA QSPI I2C T16B Figure 6...

Page 71: ...el is set to 1 by the DMACPRSET PRSETn bit has the highest priority If two or more channels have been set to the same priority level the smaller channel number takes precedence 6 4 Data Structure To perform DMA transfers a data structure that contains basic transfer control information must be provided The data structure consists of two blocks primary data structure and alternate data structure an...

Page 72: ...y 0x2b0 0x0b0 Ch 10 alternate Ch 10 primary 0x2a0 0x0a0 Ch 9 alternate Ch 9 primary 0x290 0x090 Ch 8 alternate Ch 8 primary 0x280 0x080 Ch 7 alternate Ch 7 primary 0x270 0x070 0x240 0x040 Ch 3 alternate Ch 3 primary Reserved 0x230 0x030 Ch 6 alternate Ch 6 primary 0x260 0x060 Ch 5 alternate Ch 5 primary 0x250 0x050 Ch 4 alternate Ch 4 primary Ch 2 alternate Ch 2 primary Control data 0x220 0x020 Ch...

Page 73: ...of the transfer destination address The setting value must be equal to or larger than the transfer data size when the address is incremented Table 6 4 3 1 Increment Value of Transfer Destination Address dst_inc Increment value 0x3 No increment 0x2 4 0x1 2 0x0 1 dst_size Set the size of the data to be written to the transfer destination It should be the same value as the src_size Table 6 4 3 2 Size...

Page 74: ...ansfers will not be suspended n_minus_1 Set the number of DMA transfers to be executed successively Number of successive transfers N n_minus_1 1 When the set number of successive transfers has completed a transfer completion interrupt occurs cycle_ctrl Set the DMA transfer mode For detailed information on each transfer mode refer to Section 6 5 DMA Transfer Mode Table 6 4 3 5 DMA Transfer Mode cyc...

Page 75: ...ar to the basic transfer DMA transfer starts when a DMA transfer request from a peripheral circuit or a soft ware DMA request is issued and it continues until it is completed for the set number of successive transfers or it is suspended at the arbitration cycle The DMAC resumes the DMA transfer suspended at the arbitration cycle with out a DMA transfer request being reissued When the set number of...

Page 76: ...using primary data structure Transfer using alternate data structure cycle_ctrl 0x3 2R 4 N 6 Task A Task B Task C Task D Task E Termination DMA transfer request DMA transfer request DMA transfer request DMA transfer request DMA transfer request DMA transfer request DMA transfer request DMA transfer request DMA transfer request DMA transfer request DMA transfer completion interrupt DMA transfer com...

Page 77: ...tructure from the data structure table which has been prepared with multiple data structures included in advance to the alternate data structure and then it performs DMA transfer using the alternate data structure The DMAC performs this operation repeatedly By programming the transfer mode of the data structure located at the end of the table as a basic transfer the DMA transfer can be terminated ...

Page 78: ... Auto request Copy the data structure for Task A to the alternate data structure DMA transfer completion interrupt cycle_ctrl 0x5 2R 4 N 3 cycle_ctrl 0x5 2R 2 N 8 cycle_ctrl 0x5 2R 8 N 5 Copy the data structure for Task B to the alternate data structure cycle_ctrl 0x1 2R 4 N 4 Auto request Auto request Copy the data structure for Task C to the alternate data structure Copy the data structure for T...

Page 79: ...edure shown in Section 6 2 1 Initialization In Step 2 of the initialization procedure configure the primary data structure with the control data shown below Transfer source end pointer Data structure table end address Transfer destination end pointer Alternate data structure end address dst_inc 0x2 dst_size 0x2 src_inc 0x2 src_size 0x2 R_power 0x2 n_minus_1 Number of tasks 4 1 cycle_ctrl 0x4 3 The...

Page 80: ... Task D DMA transfer request DMA transfer request DMA transfer request Copy the data structure for Task A to the alternate data structure DMA transfer completion interrupt cycle_ctrl 0x7 2R 4 N 3 cycle_ctrl 0x7 2R 2 N 8 cycle_ctrl 0x7 2R 8 N 5 Copy the data structure for Task B to the alternate data structure cycle_ctrl 0x1 2R 4 N 4 DMA transfer request DMA transfer request Copy the data structure...

Page 81: ...sfer cycle Note that the number of clock cycles for a DMA transfer may be increased due to a conflict with an access from the CPU or the Flash bus access cycle setting Figure 6 6 1 DMA Transfer Cycle 6 7 Interrupts The DMAC has a function to generate the interrupts shown in Table 6 7 1 Table 6 7 1 DMAC Interrupt Function Interrupt Interrupt flag Set condition Clear condition DMA transfer completio...

Page 82: ... STATE 3 0 These bits indicates the DMA transfer status Table 6 8 1 DMA Transfer Status DMACSTAT STATE 3 0 bits DMA transfer status 0xf 0xbf Reserved 0xa Peripheral scatter gather transfer is in progress 0x9 Transfer has completed 0x8 Transfer has been suspended 0x7 Control data is being written 0x6 Standby for transfer request to be cleared 0x5 Transfer data is being written 0x4 Transfer data is ...

Page 83: ...ts Depending On Number of Channel Implemented Number of channel implemented Writable bits Read only bits 1 CPTR 31 5 CPTR 4 0 2 CPTR 31 6 CPTR 5 0 3 4 CPTR 31 7 CPTR 6 0 5 8 CPTR 31 8 CPTR 7 0 9 16 CPTR 31 9 CPTR 8 0 17 32 CPTR 31 10 CPTR 9 0 DMAC Alternate Control Data Base Pointer Register Register name Bit Bit name Initial Reset R W Remarks DMACACPTR 31 0 ACPTR 31 0 H0 R Bits 31 0 ACPTR 31 0 Th...

Page 84: ...circuits 1 W Cancel mask state of DMA transfer requests from peripheral circuits The DMACRMSET register is cleared to 0 0 W Ineffective Each bit corresponds to a DMAC channel The high order bits for the unimplemented channels are ineffective DMAC Enable Set Register Register name Bit Bit name Initial Reset R W Remarks DMACENSET 31 0 ENSET 31 0 0x0000 0000 H0 R W Bits 31 0 ENSET 31 0 These bits ena...

Page 85: ...alternate data structure The DMACPASET register is cleared to 0 0 W Ineffective Each bit corresponds to a DMAC channel The high order bits for the unimplemented channels are ineffective DMAC Priority Set Register Register name Bit Bit name Initial Reset R W Remarks DMACPRSET 31 0 PRSET 31 0 0x0000 0000 H0 R W Bits 31 0 PRSET 31 0 These bits increase the priority of each channel 1 W Increase priori...

Page 86: ...g 1 Bits 31 0 ENDIF 31 0 These bits indicate the DMA transfer completion interrupt cause occurrence status of each DMAC channel 1 R Cause of interrupt occurred 0 R No cause of interrupt occurred 1 W Clear flag 0 W Ineffective Each bit corresponds to a DMAC channel The high order bits for the unimplemented channels are ineffective DMAC Transfer Completion Interrupt Enable Set Register Register name...

Page 87: ...nels are ineffective DMAC Error Interrupt Enable Set Register Register name Bit Bit name Initial Reset R W Remarks DMACERRIESET 31 24 0x00 R 23 16 0x00 R 15 8 0x00 R 7 1 0x00 R 0 ERRIESET 0 H0 R W Bits 31 1 Reserved Bit 0 ERRIESET This bit enables DMA error interrupts 1 W Enable interrupt 0 W Ineffective 1 R Interrupt has been enabled 0 R Interrupt has been disabled DMAC Error Interrupt Enable Cle...

Page 88: ...tion of S1C31D50 Item S1C31D50 Port groups included Ports with general purpose I O function GPIO P0 7 0 P1 7 0 P2 7 0 P3 7 0 P4 7 0 P5 7 0 P6 7 0 P7 7 0 P8 7 0 P9 5 0 PA 6 0 PD 5 0 Ports with interrupt function P0 7 0 P1 7 0 P2 7 0 P3 7 0 P4 7 0 P5 7 0 P6 7 0 P7 7 0 P8 7 0 P9 5 0 PA 6 0 Ports for debug function PD 1 0 Figure 7 1 1 PPORT Configuration KRSTCFG 1 0 CLKSRC 1 0 CLKDIV 3 0 Clock generat...

Page 89: ...ally This function may also be disabled for the port that does not require pulling up down When the port level is switched from low to high through the pull up resistor included in the I O cell or from high to low through the pull down resistor a delay will occur in the waveform rising falling edge depending on the time constant by the pull up pull down resistance and the pin load capacitance The ...

Page 90: ...3 determine the input sampling time of the chattering filter 7 3 2 Clock Supply in SLEEP Mode When using the chattering filter function during SLEEP mode the PPORT operating clock CLK_PPORT must be configured so that it will keep suppling by writing 0 to the CLGOSC xxxxSLPC bit for the CLK_PPORT clock source If the CLGOSC xxxxSLPC bit for the CLK_PPORT clock source is 1 the CLK_PPORT clock source ...

Page 91: ...ut Set the PPORTPxIOEN PxOENy bit to 0 Disable output 2 Set the PPORTPxMODSEL PxSELy bit to 0 Disable peripheral I O function 3 Initialize the peripheral circuit that uses the pin 4 Set the PPORTPxFNCSEL PxyMUX 1 0 bits Select peripheral I O function 5 Set the PPORTPxMODSEL PxSELy bit to 1 Enable peripheral I O function For the list of the peripheral I O functions that can be assigned to each port...

Page 92: ...ng edge Set the PPORTPxINTCTL PxIEy bit to 1 Enable interrupt 6 Set the following PPORTPxIOEN register bits Set the PPORTPxIOEN PxOENy bit to 0 Disable output Set the PPORTPxIOEN PxIENy bit to 1 Enable input Steps 1 and 5 are required for the ports with an interrupt function Step 2 is required for the ports with a chattering filter function Table 7 4 1 1 lists the port status according to the comb...

Page 93: ...ter a lapse of four or more CLK_PPORT cycles from enabling the chattering filter function If the clock generator is configured so that it will supply CLK_PPORT to PPORT in SLEEP mode the chattering filter of the port will function even in SLEEP mode If CLK_PPORT is configured to stop in SLEEP mode PPORT inactivates the chattering filter during SLEEP mode to input pin status transitions directly to...

Page 94: ...Ey bit corresponding to each interrupt flag An interrupt request is sent to the CPU core only when the interrupt flag of which interrupt has been enabled by the interrupt enable bit is set For more information on interrupt control refer to the Interrupt chapter Interrupt check in port group unit When interrupts are enabled in two or more port groups check the PPORTINTFGRP PxINT bit in the interrup...

Page 95: ...15 8 PxOUT 7 0 These bits are used to set data to be output from the GPIO port pins 1 R W Output high level from the port pin 0 R W Output low level from the port pin When output is enabled PPORTPxIOEN PxOENy bit 1 the port pin outputs the data set here Al though data can be written when output is disabled PPORTPxIOEN PxOENy bit 0 it does not affect the pin status These bits do not affect the outp...

Page 96: ...function Px Port Pull up down Control Register Register name Bit Bit name Initial Reset R W Remarks PPORTPxRCTL 15 8 PxPDPU 7 0 0x00 H0 R W 7 0 PxREN 7 0 0x00 H0 R W 1 This register is effective when the GPIO function is selected 2 The bit configuration differs depending on the port group Bits 15 8 PxPDPU 7 0 These bits select either the pull up resistor or the pull down resistor when using a resi...

Page 97: ...ective when the GPIO function is selected 2 The bit configuration differs depending on the port group Bits 15 8 PxEDGE 7 0 These bits select the input signal edge to generate a port input interrupt 1 R W An interrupt will occur at a falling edge 0 R W An interrupt will occur at a rising edge Bits 7 0 PxIE 7 0 These bits enable port input interrupts 1 R W Enable interrupts 0 R W Disable interrupts ...

Page 98: ...Register name Bit Bit name Initial Reset R W Remarks PPORTPxFNCSEL 15 14 Px7MUX 1 0 0x0 H0 R W 13 12 Px6MUX 1 0 0x0 H0 R W 11 10 Px5MUX 1 0 0x0 H0 R W 9 8 Px4MUX 1 0 0x0 H0 R W 7 6 Px3MUX 1 0 0x0 H0 R W 5 4 Px2MUX 1 0 0x0 H0 R W 3 2 Px1MUX 1 0 0x0 H0 R W 1 0 Px0MUX 1 0 0x0 H0 R W 1 The bit configuration differs depending on the port group 2 The initial value may be changed by the port Bits 15 14 P...

Page 99: ...ed Bits 1 0 CLKSRC 1 0 These bits select the clock source of PPORT chattering filter The PPORT operating clock should be configured by selecting the clock source using the PPORT CLK CLKSRC 1 0 bits and the clock division ratio using the PPORTCLK CLKDIV 3 0 bits as shown in Table 7 6 2 These settings determine the input sampling time of the chattering filter Table 7 6 2 Clock Source and Division Ra...

Page 100: ...R 5 P5INT 0 H0 R 4 P4INT 0 H0 R 3 P3INT 0 H0 R 2 P2INT 0 H0 R 1 P1INT 0 H0 R 0 P0INT 0 H0 R 1 Only the bits corresponding to the port groups that support interrupts are provided Bits 15 11 Reserved Bits 10 0 PxINT These bits indicate that Px port group includes a port that has generated an interrupt 1 R A port generated an interrupt 0 R No port generated an interrupt The PPORTINTFGRP PxINT bit is ...

Page 101: ...P0IF 7 0 0x00 H0 R W Cleared by writing 1 PPORTP0INTCTL P0 Port Interrupt Control Register 15 8 P0EDGE 7 0 0x00 H0 R W 7 0 P0IE 7 0 0x00 H0 R W PPORTP0CHATEN P0 Port Chattering Filter Enable Register 15 8 0x00 R 7 0 P0CHATEN 7 0 0x00 H0 R W PPORTP0MODSEL P0 Port Mode Select Register 15 8 0x00 R 7 0 P0SEL 7 0 0x00 H0 R W PPORTP0FNCSEL P0 Port Function Select Register 15 14 P07MUX 1 0 0x0 H0 R W 13 ...

Page 102: ...0 H0 R W PPORTP1CHATEN P1 Port Chattering Filter Enable Register 15 8 0x00 R 7 0 P1CHATEN 7 0 0x00 H0 R W PPORTP1MODSEL P1 Port Mode Select Register 15 8 0x00 R 7 0 P1SEL 7 0 0x00 H0 R W PPORTP1FNCSEL P1 Port Function Select Register 15 14 P17MUX 1 0 0x0 H0 R W 13 12 P16MUX 1 0 0x0 H0 R W 11 10 P15MUX 1 0 0x0 H0 R W 9 8 P14MUX 1 0 0x0 H0 R W 7 6 P13MUX 1 0 0x0 H0 R W 5 4 P12MUX 1 0 0x0 H0 R W 3 2 ...

Page 103: ... P2IE 7 0 0x00 H0 R W PPORTP2CHATEN P2 Port Chattering Filter Enable Register 15 8 0x00 R 7 0 P2CHATEN 7 0 0x00 H0 R W PPORTP2MODSEL P2 Port Mode Select Register 15 8 0x00 R 7 0 P2SEL 7 0 0x00 H0 R W PPORTP2FNCSEL P2 Port Function Select Register 15 14 P27MUX 1 0 0x0 H0 R W 13 12 P26MUX 1 0 0x0 H0 R W 11 10 P25MUX 1 0 0x0 H0 R W 9 8 P24MUX 1 0 0x0 H0 R W 7 6 P23MUX 1 0 0x0 H0 R W 5 4 P22MUX 1 0 0x...

Page 104: ...GE 7 0 0x00 H0 R W 7 0 P3IE 7 0 0x00 H0 R W PPORTP3CHATEN P3 Port Chattering Filter Enable Register 15 8 0x00 R 7 0 P3CHATEN 7 0 0x00 H0 R W PPORTP3MODSEL P3 Port Mode Select Register 15 8 0x00 R 7 0 P3SEL 7 0 0x00 H0 R W PPORTP3FNCSEL P3 Port Function Select Register 15 14 P37MUX 1 0 0x0 H0 R W 13 12 P36MUX 1 0 0x0 H0 R W 11 10 P35MUX 1 0 0x0 H0 R W 9 8 P34MUX 1 0 0x0 H0 R W 7 6 P33MUX 1 0 0x0 H0...

Page 105: ...Interrupt Control Register 15 8 P4EDGE 7 0 0x00 H0 R W 7 0 P4IE 7 0 0x00 H0 R W PPORTP4CHATEN P4 Port Chattering Filter Enable Register 15 8 0x00 R 7 0 P4CHATEN 7 0 0x00 H0 R W PPORTP4MODSEL P4 Port Mode Select Register 15 8 0x00 R 7 0 P4SEL 7 0 0x00 H0 R W PPORTP4FNCSEL P4 Port Function Select Register 15 14 P47MUX 1 0 0x0 H0 R W 13 12 P46MUX 1 0 0x0 H0 R W 11 10 P45MUX 1 0 0x0 H0 R W 9 8 P44MUX ...

Page 106: ...TP5INTCTL P5 Port Interrupt Control Register 15 8 P5EDGE 7 0 0x00 H0 R W 7 0 P5IE 7 0 0x00 H0 R W PPORTP5CHATEN P5 Port Chattering Filter Enable Register 15 8 0x00 R 7 0 P5CHATEN 7 0 0x00 H0 R W PPORTP5MODSEL P5 Port Mode Select Register 15 8 0x00 R 7 0 P5SEL 7 0 0x00 H0 R W PPORTP5FNCSEL P5 Port Function Select Register 15 14 P57MUX 1 0 0x0 H0 R W 13 12 P56MUX 1 0 0x0 H0 R W 11 10 P55MUX 1 0 0x0 ...

Page 107: ... Port Interrupt Control Register 15 8 P6EDGE 7 0 0x00 H0 R W 7 0 P6IE 7 0 0x00 H0 R W PPORTP6CHATEN P6 Port Chattering Filter Enable Register 15 8 0x00 R 7 0 P6CHATEN 7 0 0x00 H0 R W PPORTP6MODSEL P6 Port Mode Select Register 15 8 0x00 R 7 0 P6SEL 7 0 0x00 H0 R W PPORTP6FNCSEL P6 Port Function Select Register 15 14 P67MUX 1 0 0x0 H0 R W 13 12 P66MUX 1 0 0x0 H0 R W 11 10 P65MUX 1 0 0x0 H0 R W 9 8 P...

Page 108: ... Interrupt Control Register 15 8 P7EDGE 7 0 0x00 H0 R W 7 0 P7IE 7 0 0x00 H0 R W PPORTP7CHATEN P7 Port Chattering Filter Enable Register 15 8 0x00 R 7 0 P7CHATEN 7 0 0x00 H0 R W PPORTP7MODSEL P7 Port Mode Select Register 15 8 0x00 R 7 0 P7SEL 7 0 0x00 H0 R W PPORTP7FNCSEL P7 Port Function Select Register 15 14 P77MUX 1 0 0x0 H0 R W 13 12 P76MUX 1 0 0x0 H0 R W 11 10 P75MUX 1 0 0x0 H0 R W 9 8 P74MUX...

Page 109: ...rrupt Control Register 15 8 P8EDGE 7 0 0x00 H0 R W 7 0 P8IE 7 0 0x00 H0 R W PPORTP8CHATEN P8 Port Chattering Filter Enable Register 15 8 0x00 R 7 0 P8CHATEN 7 0 0x00 H0 R W PPORTP8MODSEL P8 Port Mode Select Register 15 8 0x00 R 7 0 P8SEL 7 0 0x00 H0 R W PPORTP8FNCSEL P8 Port Function Select Register 15 14 P87MUX 1 0 0x0 H0 R W 13 12 P86MUX 1 0 0x0 H0 R W 11 10 P85MUX 1 0 0x0 H0 R W 9 8 P84MUX 1 0 ...

Page 110: ... PPORTP9INTCTL P9 Port Interrupt Control Register 15 14 0 R 13 8 P9EDGE 5 0 0x00 H0 R W 7 6 0 R 5 0 P9IE 5 0 0x00 H0 R W PPORTP9CHATEN P5 Port Chattering Filter Enable Register 15 8 0x00 R 7 6 0 R 5 0 P9CHATEN 5 0 0x00 H0 R W PPORTP9MODSEL P9 Port Mode Select Register 15 8 0x00 R 7 6 0 R 5 0 P9SEL 5 0 0x00 H0 R W PPORTP9FNCSEL P9 Port Function SelectRegister 15 14 0x0 R 13 12 0x0 R 11 10 P95MUX 1 ...

Page 111: ... 0x00 H0 R W Cleared by writing 1 PPORTPAINTCTL PA Port Interrupt Control Register 15 0 R 14 8 PAEDGE 6 0 0x00 H0 R W 7 0 R 6 0 PAIE 6 0 0x00 H0 R W PPORTPACHATEN PA Port Chattering Filter Enable Register 15 8 0x00 R 7 0 R 6 0 PACHATEN 6 0 0x00 H0 R W PPORTPAMODSEL PA Port Mode Select Register 15 8 0x00 R 7 0 R 6 0 PASEL 6 0 0x00 H0 R W PPORTPAFNCSEL PA Port Function Select Register 15 14 0x0 R 13...

Page 112: ...Pull up down Control Register 15 14 0x0 R 13 8 PDPDPU 5 0 0x0 H0 R W 7 6 0x0 R 5 0 PDREN 5 0 0x0 H0 R W PPORTPDINTF PPORTPDINTCTL PPORTPDCHATEN 15 0 0x0000 R PPORTPDMODSEL PD Port Mode Select Register 15 8 0x00 R 7 6 0x0 R 5 0 PDSEL 5 0 0x3 H0 R W PPORTPDFNCSEL PD Port Function Select Register 15 12 0x00 R 11 10 PD5MUX 1 0 0x0 H0 R W 9 8 PD4MUX 1 0 0x0 H0 R W 7 6 PD3MUX 1 0 0x0 H0 R W 5 4 PD2MUX 1...

Page 113: ...al Reset R W Remarks PPORTCLK P Port Clock Control Register 15 9 0x00 R 8 DBRUN 0 H0 R WP 7 4 CLKDIV 3 0 0x0 H0 R WP 3 2 KRSTCFG 1 0 0x0 H0 R WP 1 0 CLKSRC 1 0 0x0 H0 R WP PPORTINTFGRP P Port Interrupt Flag Group Register 15 8 0x00 R 11 0 R 10 PAINT 0 H0 R 9 P9INT 0 H0 R 8 P8INT 0 H0 R 7 P7INT 0 H0 R 6 P6INT 0 H0 R 5 P5INT 0 H0 R 4 P4INT 0 H0 R 3 P3INT 0 H0 R 2 P2INT 0 H0 R 1 P1INT 0 H0 R 0 P0INT ...

Page 114: ...ay be assigned to peripheral I O function 1 of an I O port listed above The following shows the procedure to assign a peripheral I O function and enable it in the I O port 1 Configure the PPORTPxIOEN register of the I O port Set the PPORTPxIOEN PxIENy bit to 0 Disable input Set the PPORTPxIOEN PxOENy bit to 0 Disable output 2 Set the PPORTPxMODSEL PxSELy bit of the I O port to 0 Disable peripheral...

Page 115: ...PERISEL 2 0 Bits 2 0 PxyPERISEL 2 0 These bits specify a peripheral circuit See Table 8 3 1 Table 8 3 1 Peripheral I O Function Selections UPMUXPxMUXn PxyPPFNC 2 0 bits Peripheral I O function UPMUXPxMUXn PxyPERISEL 2 0 bits Peripheral circuit 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 None I2C SPIA UART3 T16B Reserved Reserved Reserved UPMUXPxMUXn PxyPERICH 1 0 bits Peripheral circuit channel 0x0 0x1 0x0 0x...

Page 116: ...he clock source in the clock generator if it is stopped refer to Clock Generator in the Power Supply Reset and Clocks chapter 3 Set the following WDT2CLK register bits WDT2CLK CLKSRC 1 0 bits Clock source selection WDT2CLK CLKDIV 1 0 bits Clock division ratio selection Clock frequency setting 4 Write a value other than 0x0096 to the MSCPROT PROT 15 0 bits Set system protection 9 2 2 Clock Supply i...

Page 117: ...eriodically via software while WDT2 is running 1 Write 0x0096 to the MSCPROT PROT 15 0 bits Remove system protection 2 Write 1 to the WDT2CTL WDTCNTRST bit Reset WDT2 counter 3 Write a value other than 0x0096 to the MSCPROT PROT 15 0 bits Set system protection A location should be provided for periodically processing this routine Process this routine within the tWDT cycle After resetting WDT2 star...

Page 118: ...2 before re suming operations after HALT mode is cleared During SLEEP mode WDT2 operates in SLEEP mode if the selected clock source is running SLEEP mode is cleared by an NMI or reset if it continues for more than the NMI reset generation cycle and the CPU executes the interrupt handler Therefore stop WDT2 by setting the WDT2CTL WDTRUN 3 0 bits before executing the slp instruction If the clock sou...

Page 119: ... No clock supplied in DEBUG mode Bits 7 6 Reserved Bits 5 4 CLKDIV 1 0 These bits select the division ratio of the WDT2 operating clock counter clock The clock frequency should be set to around 256 Hz Bits 3 2 Reserved Bits 1 0 CLKSRC 1 0 These bits select the clock source of WDT2 Table 9 4 1 Clock Source and Division Ratio Settings WDT2CLK CLKDIV 1 0 bits WDT2CLK CLKSRC 1 0 bits 0x0 0x1 0x2 0x3 I...

Page 120: ... WDT2 issues a reset when a counter compare match occurs Bit 8 STATNMI This bit indicates that a counter compare match and NMI have occurred 1 R NMI counter compare match occurred 0 R NMI not occurred When the NMI generation function of WDT2 is used read this bit in the NMI handler routine to con firm that WDT2 was the source of the NMI The WDT2CTL STATNMI bit set to 1 is cleared to 0 by writing 1...

Page 121: ...t Bit name Initial Reset R W Remarks WDT2CMP 15 10 0x00 R 9 0 CMP 9 0 0x3ff H0 R WP Bits 15 10 Reserved Bits 9 0 CMP 9 0 These bits set the NMI reset generation cycle The value set in this register is compared with the 10 bit counter value while WDT2 is running and an NMI or reset is generated when they are matched ...

Page 122: ...e I O Initial status Function RTC1S O O L 1 second signal monitor output pin Indicates the status when the pin is configured for RTCA If the port is shared with the RTCA output function and other functions the RTCA function must be assigned to the port For more information refer to the I O Ports chapter RTC count control circuit Comparator 128 Hz RTCTRM 6 0 RTC 128HZ 64 Hz RTC 64HZ 32 Hz RTC 32HZ ...

Page 123: ...esults in Steps 1 and 2 4 Write the value determined in Step 3 to the RTCACTLH RTCTRM 6 0 bits periodically in n second cycles using an RTCA alarm or second interrupt 5 Monitor the RTC1S signal to check that every n second cycle has no error included The correction value for theoretical regulation can be specified within the range from 64 to 63 and it should be written to the RTCACTLH RTCTRM 6 0 b...

Page 124: ...ection value decimal Correction rate ppm 0x00 0 0 0 0x40 64 61 0 0x01 1 1 0 0x41 63 60 1 0x02 2 1 9 0x42 62 59 1 0x03 3 2 9 0x43 61 58 2 0x3e 62 59 1 0x7e 2 1 9 0x3f 63 60 1 0x7f 1 1 0 Minimum resolution 1 ppm Correction rate range 61 0 to 60 1 ppm Notes The theoretical regulation affects only the real time clock counter and 1 Hz counter It does not affect the stopwatch counter After a value is wr...

Page 125: ... the RTCAINTF register to clear them 7 Write 1 to the interrupt enable bits in the RTCAINTE register to enable real time clock counter interrupts Time read 1 Check to see if the RTCACTLL RTCBSY bit 0 If the RTCACTLL RTCBSY bit 1 wait until it is set to 0 2 Write 1 to the RTCACTLL RTCHLD bit to suspend count up operation of the real time clock counter 3 Read the date and time from the control bits ...

Page 126: ... to the RTCACTLL RTCADJ bit adds 1 to the minute counter if the second counter represents 30 to 59 seconds or clears the second counter with the minute counter left unchanged if the second counter represents 0 to 29 seconds 1 second correction If a second count up timing occurred while the RTCACTLL RTCHLD bit 1 count hold state the real time clock counter counts up by 1 second performs 1 second co...

Page 127: ...he count up patterns shown in Figure 10 4 4 1 Figure 10 4 4 1 Stopwatch Count Up Patterns 0 0 1 2 3 4 5 6 7 8 9 0 1 1 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 3 256 s 2 256 s 3 256 s 2 256 s 3 256 s 2 256 s 3 256 s 2 256 s 3 256 s 2 256 s 3 256 s 3 256 s 3 256 s 2 256 s 3 256 s 2 256 s 3 256 s 2 256 s 3 256 s 2 256 s 26 256 s 26 256 s 25 256 s 25 256 s 26 256 s 26 256 s 25 256 s 25 256 s 26 256 s 26 256 s ...

Page 128: ... 1 Stopwatch 10 Hz RTCAINTF SW10IF 1 10 second counter count up Writing 1 Stopwatch 100 Hz RTCAINTF SW100IF 1 100 second counter count up Writing 1 Theoretical regulation completion RTCAINTF RTCTRMIF At the end of theoretical regulation operation Writing 1 Figure 10 5 1 RTCA Interrupt Timings Notes 1 second to 1 32 second interrupts occur after a lapse of 1 256 second from change of the 1 Hzcounte...

Page 129: ...unter 1 R W Halt real time clock counter count up operation 0 R W Normal operation Writing 1 to this bit halts the count up operation of the real time clock counter this makes it possible to read the counter value correctly without changing the counter Write 0 to this bit to resume count up operation immediately after the counter has been read Depending on these operation timings the 1 second corr...

Page 130: ... 30 second correction refer to Real Time Clock Counter Operations Notes Be sure to avoid writing to this bit when the RTCACTLL RTCBSY bit 1 Do not write 1 to this bit again while the RTCACTLL RTCADJ bit 1 Bit 1 RTCRST This bit resets the 1 Hz counter the RTCACTLL RTCADJ bit and the RTCACTLL RTCHLD bit 1 W Reset 0 W Ineffective 1 R Reset is being executed 0 R Reset has finished Normal operation Thi...

Page 131: ...on method of correction value refer to Theoretical Regulation Function Notes When the RTCACTLH RTCTRMBSY bit 1 the RTCACTLH RTCTRM 6 0 bits cannot be rewritten Writing 0x00 to the RTCACTLH RTCTRM 6 0 bits sets the RTCACTLH RTCTRMBSY bit to 1 as well However no correcting operation is performed RTCA Second Alarm Register Register name Bit Bit name Initial Reset R W Remarks RTCAALM1 15 0 R 14 12 RTC...

Page 132: ... bit 0 1 R W P M 0 R W A M This setting is ineffective in 24H mode RTCACTLL RTC24H bit 1 Bits 13 12 RTCHHA 1 0 Bits 11 8 RTCHLA 3 0 The RTCAALM2 RTCHHA 1 0 bits and the RTCAALM2 RTCHLA 3 0 bits set the 10 hour digit and 1 hour digit of the alarm time respectively A value within 1 to 12 o clock in 12H mode or 0 to 23 in 24H mode can be set in BCD code Bit 7 Reserved Bits 6 4 RTCMIHA 2 0 Bits 3 0 RT...

Page 133: ...ter value was read successfully if the two read results are the same Bits 7 5 Reserved Bit 4 SWRST This bit resets the stopwatch counter to 0x00 1 W Reset 0 W Ineffective 0 R Always 0 when being read When the stopwatch counter in running status is reset it continues counting from count 0x00 The stopwatch counter retains 0x00 if it is reset in idle status Bits 3 1 Reserved Bit 0 SWRUN This bit star...

Page 134: ...tively The setting read values are a BCD code within the range from 0 to 59 Note Be sure to avoid writing to the RTCASEC RTCSH 2 0 RTCSL 3 0 bits while the RTCACTLL RTCBSY bit 1 Bit 7 RTC1HZ Bit 6 RTC2HZ Bit 5 RTC4HZ Bit 4 RTC8HZ Bit 3 RTC16HZ Bit 2 RTC32HZ Bit 1 RTC64HZ Bit 0 RTC128HZ 1 Hz counter data can be read from these bits The following shows the correspondence between the bit and frequenc...

Page 135: ... hour counter Bits 13 12 RTCHH 1 0 Bits 11 8 RTCHL 3 0 The RTCAHUR RTCHH 1 0 bits and the RTCAHUR RTCHL 3 0 bits are used to set and read the 10 hour digit and the 1 hour digit of the hour counter respectively The setting read values are a BCD code within the range from 1 to 12 in 12H mode or 0 to 23 in 24H mode Note Be sure to avoid writing to the RTCAHUR RTCHH 1 0 RTCHL 3 0 bits while the RTCACT...

Page 136: ...ectively The setting read values are a BCD code within the range from 1 to 12 Note Be sure to avoid writing to the RTCAMON RTCMOH RTCMOL 3 0 bits while the RT CACTLL RTCBSY bit 1 Bits 7 6 Reserved Bits 5 4 RTCDH 1 0 Bits 3 0 RTCDL 3 0 The RTCAMON RTCDH 1 0 bits and the RTCAMON RTCDL 3 0 bits are used to set and read the 10 day digit and the 1 day digit of the day counter respectively The setting r...

Page 137: ... value and day of the week Table 10 6 2 Correspondence between the count value and day of the week RTCAYAR RTCWK 2 0 bits Day of the week 0x6 Saturday 0x5 Friday 0x4 Thursday 0x3 Wednesday 0x2 Tuesday 0x1 Monday 0x0 Sunday Note Be sure to avoid writing to the RTCAYAR RTCWK 2 0 bits while the RTCACTLL RTCBSY bit 1 Bits 7 4 RTCYH 3 0 Bits 3 0 RTCYL 3 0 The RTCAYAR RTCYH 3 0 bits and the RTCAYAR RTCY...

Page 138: ...correspondence between the bit and interrupt RTCAINTF RTCTRMIF bit Theoretical regulation completion interrupt RTCAINTF SW1IF bit Stopwatch 1 Hz interrupt RTCAINTF SW10IF bit Stopwatch 10 Hz interrupt RTCAINTF SW100IF bit Stopwatch 100 Hz interrupt Bit 11 9 Reserved Bit 8 ALARMIF Bit 7 T1DAYIF Bit 6 T1HURIF Bit 5 T1MINIF Bit 4 T1SECIF Bit 3 T1_2SECIF Bit 2 T1_4SECIF Bit 1 T1_8SECIF Bit 0 T1_32SECI...

Page 139: ...he correspondence between the bit and interrupt RTCAINTE RTCTRMIE bit Theoretical regulation completion interrupt RTCAINTE SW1IE bit Stopwatch 1 Hz interrupt RTCAINTE SW10IE bit Stopwatch 10 Hz interrupt RTCAINTE SW100IE bit Stopwatch 100 Hz interrupt Bits 11 9 Reserved Bit 8 ALARMIE Bit 7 T1DAYIE Bit 6 T1HURIE Bit 5 T1MINIE Bit 4 T1SECIE Bit 3 T1_2SECIE Bit 2 T1_4SECIE Bit 1 T1_8SECIE Bit 0 T1_32...

Page 140: ...operations Three detection cycles are selectable Low power supply voltage detection count function to generate an interrupt reset when low power supply voltage is successively detected the number of times specified Continuous operation is also possible Figure 11 1 1 shows the configuration of SVD3 Table 11 1 1 SVD3 Configuration of S1C31D50 Item S1C31D50 Power supply voltage to be detected VDD and...

Page 141: ...her functions the EXSVDn function must be assigned to the port before SVD3 can be activated For more information refer to the I O Ports chapter 11 2 2 External Connection Figure 11 2 2 1 Connection between EXSVD1 Pin and External Power Supply REXT resistance value must be determined so that it will be sufficiently smaller than the EXSVD input impedance REXSVD For the EXSVDn pin input voltage range...

Page 142: ...n SLEEP Mode When using SVD3 during SLEEP mode the SVD3 operating clock CLK_SVD3 must be configured so that it will keep supplying by writing 0 to the CLGOSC xxxxSLPC bit for the CLK_SVD3 clock source If the CLGOSC xxxxSLPC bit for the CLK_SVD3 clock source is 1 the CLK_SVD3 clock source is deactivated during SLEEP mode and SVD3 stops with the register settings maintained at those before entering ...

Page 143: ... SVD3INTF SVDDT bit 0 Power supply voltage VDD EXSVDn SVD detection voltage VSVD or EXSVD detection voltage VSVD_EXT When SVD3INTF SVDDT bit 1 Power supply voltage VDD EXSVDn SVD detection voltage VSVD or EXSVD detection voltage VSVD_EXT Before reading the SVD3INTF SVDDT bit wait for at least SVD circuit enable response time after 1 is written to the SVD3CTL MODEN bit refer to Supply Voltage Detec...

Page 144: ...urthermore an interrupt or a reset can be generated when SVD3 has successively detected low power supply voltage the number of times specified by the SVD3CTL SVDSC 1 0 bits 1 When the SVD3CTL SVDMD 1 0 bits 0x0 continuous operation mode 2 When the SVD3CTL SVDMD 1 0 bits 0x0 intermittent operation mode Figure 11 4 2 1 SVD3 Operations VDD SVD3CTL MODEN SVD3 operating status VSVD VSVD DET SVD3INTF SV...

Page 145: ...t in the interrupt handler routine 11 5 2 SVD3 Reset Setting the SVD3CTL SVDRE 3 0 bits to 0xa allows use of the SVD3 reset issuance function The reset issuing timing is the same as that of the SVD3INTF SVDIF bit being set when a low voltage is detected After a reset has been issued SVD3 enters continuous operation mode even if it was operating in intermittent operation mode and continues operatin...

Page 146: ...supplied in DEBUG mode Bit 7 Reserved Bits 6 4 CLKDIV 2 0 These bits select the division ratio of the SVD3 operating clock Bits 3 2 Reserved Bits 1 0 CLKSRC 1 0 These bits select the clock source of SVD3 Table 11 6 1 Clock Source and Division Ratio Settings SVD3CLK CLKDIV 2 0 bits SVD3CLK CLKSRC 1 0 bits 0x0 0x1 0x2 0x3 IOSC OSC1 OSC3 EXOSC 0x7 0x6 Reserved 1 1 Reserved 1 1 0x5 1 512 1 512 0x4 1 2...

Page 147: ...ected eight times 0x2 Low power supply voltage is successively detected four times 0x1 Low power supply voltage is successively detected twice 0x0 Low power supply voltage is successively detected once This setting is ineffective in continuous operation mode SVD3CTL SVDMD 1 0 bits 0x0 Bits 12 8 SVDC 4 0 These bits select an SVD detection voltage VSVD EXSVD detection voltage VSVD_EXT for detecting ...

Page 148: ...ables for the SVD3 circuit to operate 1 R WP Enable Start detection operations 0 R WP Disable Stop detection operations After this bit has been altered wait until the value written is read out from this bit without subsequent operations being performed Notes Writing 0 to the SVD3CTL MODEN bit resets the SVD3 hardware However the register values set and the interrupt flag are not cleared The SVD3CT...

Page 149: ...pt cause occurrence status 1 R Cause of interrupt occurred 0 R No cause of interrupt occurred 1 W Clear flag 0 W Ineffective Note The SVD3 internal circuit is initialized if the interrupt flag is cleared while SVD3 is in operation after 1 is written to the SVD3CTL MODEN bit SVD3 Interrupt Enable Register Register name Bit Bit name Initial Reset R W Remarks SVD3INTE 15 8 0x00 R 7 1 0x00 R 0 SVDIE 0...

Page 150: ...ronous serial interface Ch 0 master clock Ch 5 Synchronous serial interface Ch 2 master clock Ch 6 Synchronous serial interface Ch 1 master clock Ch 7 12 bit A D converter trigger signal Figure 12 1 1 Configuration of a T16 Channel 12 2 Input Pin Table 12 2 1 shows the T16 input pin Table 12 2 1 T16 Input Pin Pin name I O Initial status Function EXCLm I I Hi Z External event signal input pin Indic...

Page 151: ...SLEEP mode and T16 stops with the register settings and counter value maintained at those before entering SLEEP mode After the CPU returns to normal mode CLK_T16_n is supplied and the T16 operation resumes 12 3 3 Clock Supply During Debugging The CLK_T16_n supply during debugging should be controlled using the T16_nCLK DBRUN bit The CLK_T16_n supply to T16 Ch n is suspended when the CPU enters deb...

Page 152: ...rate an interrupt and may be output to a specific peripheral circuit as a clock T16 Ch n must be set to repeat mode to generate a clock The underflow cycle is determined by the T16 Ch n operating clock setting and reload data counter initial value set in the T16_nTR register The following shows the equations to calculate the underflow cycle and frequency 𝑇 𝑇𝑅 1 𝑓𝐶𝐿𝐾_𝑇16_𝑛 𝑓𝑇 𝑓𝐶𝐿𝐾_𝑇16_𝑛 𝑇𝑅 1 Eq 12 ...

Page 153: ... operates on CLK_T16_n one of the operations shown below is required to read correctly by the CPU Read the counter value twice or more and check to see if the same value is read Stop the timer and then read the counter value 12 5 Interrupt Each T16 channel has a function to generate the interrupt shown in Table 12 5 1 Table 12 5 1 T16 Interrupt Function Interrupt Interrupt flag Set condition Clear...

Page 154: ... CLKSRC 1 0 These bits select the clock source of T16 Ch n Table 12 6 1 Clock Source and Division Ratio Settings T16_nCLK CLKDIV 3 0 bits T16_nCLK CLKSRC 1 0 bits 0x0 0x1 0x2 0x3 IOSC OSC1 OSC3 EXOSC EXCLm 0xf 1 32 768 1 1 1 32 768 1 1 0xe 1 16 384 1 16 384 0xd 1 8 192 1 8 192 0xc 1 4 096 1 4 096 0xb 1 2 048 1 2 048 0xa 1 1 024 1 1 024 0x9 1 512 1 512 0x8 1 256 1 256 1 256 0x7 1 128 1 128 1 128 0x...

Page 155: ...s count operations However the T16_nCTL MODEN bit must be set to 1 in conjunction with this bit or it must be set in advance While the timer is running writing 0 to this bit stops count operations When the counter stops due to a counter underflow in one shot mode this bit is automatically cleared to 0 Bits 7 2 Reserved Bit 1 PRESET This bit presets the reload data stored in the T16_nTR register to...

Page 156: ...ter name Bit Bit name Initial Reset R W Remarks T16_nTC 15 0 TC 15 0 0xffff H0 R Bits 15 0 TC 15 0 The current counter value can be read out from these bits T16 Ch n Interrupt Flag Register Register name Bit Bit name Initial Reset R W Remarks T16_nINTF 15 8 0x00 R 7 1 0x00 R 0 UFIF 0 H0 R W Cleared by writing 1 Bits 15 1 Reserved Bit 0 UFIF This bit indicates the T16 Ch n underflow interrupt cause...

Page 157: ...duplex communications Includes a 2 byte receive data buffer and a 1 byte transmit data buffer Includes an RZI modulator demodulator circuit to support IrDA 1 0 compatible infrared communications Can detect parity error framing error and overrun error Can generate receive buffer full 1 byte 2 bytes transmit buffer empty end of transmission parity error framing error and overrun error interrupts Can...

Page 158: ...e port is shared with the UART3 pin and other functions the UART3 input output function must be assigned to the port before activating the UART3 For more information refer to the I O Ports chapter DMA request control circuit DMA controller RB1FDMAENx TBEDMAENx Interrupt control circuit TENDIE FEIE PEIE OEIE RB2FIE RB1FIE TBEIE TENDIF FEIF PEIF OEIF RB2FIF RB1FIF TBEIF CLKSRC 1 0 CLKDIV 1 0 Baud ra...

Page 159: ...2 4 Output Pin Open Drain Output Function The USOUTn pin supports the open drain output function Default configuration is a push pull output and it is switched to an open drain output by setting the UART3_nMOD OUTMD bit to 1 13 2 5 Input Output Signal Inverting Function The UART3 can invert the signal polarities of the USINn pin input and the USOUTn pin output by setting the UART3_nMOD INVRX bit a...

Page 160: ...3_nCLK DBRUN bit The CLK_UART3_n supply to the UART3 Ch n is suspended when the CPU enters debug state if the UART3_ nCLK DBRUN bit 0 After the CPU returns to normal mode the CLK_UART3_n supply resumes Although the UART3 Ch n stops operating when the CLK_UART3_n supply is suspended the output pin and registers retain the status before the debug state was entered If the UART3_nCLK DBRUN bit 1 the C...

Page 161: ...ART3_nMOD STPB bit 1 Parity function The parity function is configured using the UART3_nMOD PREN and UART3_nMOD PRMD bits Table 13 4 1 Parity Function Setting Figure 13 4 1 Data Format UART3_nMOD PREN bit UART3_nMOD PRMD bit Parity function 1 1 Odd parity 1 0 Even parity 0 Non parity D0 D1 D2 D3 D4 D5 D6 D0 D1 D2 D3 D4 D5 D6 p D0 D1 D2 D3 D4 D5 D6 D0 D1 D2 D3 D4 D5 D6 p D0 D1 D2 D3 D4 D5 D6 D7 D0 ...

Page 162: ...terrupt flags in the UART3_nINTF register Clear interrupt flags Set the interrupt enable bits in the UART3_nINTE register to 1 Enable interrupts The initial value of the UART3_nINTF TBEIF bit is 1 therefore an interrupt will occur immediately after the UART3_nINTE TBEIE bit is set to 1 8 Configure the DMA controller and set the following UART3 control bits when using DMA transfer Write 1 to the DM...

Page 163: ...nnel must be enabled to start a DMA transfer in advance so that transmit data will be transferred to the UART3_nTXD register For more information on DMA refer to the DMA Controller chapter Table 13 5 2 1 DMA Data Structure Configuration Example for Data Transmission Item Setting example End pointer Transfer source Memory address in which the last transmit data is stored Transfer destination UART3_...

Page 164: ...e receive shift register The UART3_nINTF RBSY bit is set to 1 when the start bit is detected The UART3_nINTF RBSY bit is cleared to 0 and the receive shift register data is transferred to the receive data buffer at the stop bit receive timing The receive data buffer consists of a 2 byte FIFO and receives data until it becomes full When the receive data buffer receives the first data it sets the UA...

Page 165: ...figuration Example for Data Reception Item Setting example End pointer Transfer source UART3_nRXDregisteraddress Transfer destination Memory address to which the last received data is stored Control data dst_inc 0x0 1 dst_size 0x0 byte src_inc 0x3 no increment src_size 0x0 byte R_power 0x0 arbitrated for every transfer n_minus_1 Number of transfer data cycle_ctrl 0x1 basic transfer 13 5 4 IrDA Int...

Page 166: ...es the carrier modulation function allowing carrier modulation waveforms to be output according to the UART3_nMOD PECAR bit setting Data transmit control is identical to that for normal interface even in this case Figure 13 5 5 1 Carrier Modulation Waveform UART3_nMOD CHLN 1 UART3_nMOD STPB 0 UART3_nMOD PREN 1 The carrier modulation output frequency is determined by the UART3_nCAWF CRPER 7 0 bit s...

Page 167: ...ill be set when the data that encountered an error is transferred to the receive data buffer When the receive data buffer has a one byte free space The interrupt flag will be set when the first data byte already loaded is read out after the data that encountered an error is transferred to the second byte entry of the receive data buffer 13 6 2 Parity Error If the parity function is enabled a parit...

Page 168: ...rrupt request is sent to the CPU core only when the interrupt flag of which interrupt has been enabled by the interrupt enable bit is set For more information on interrupt control refer to the Interrupt chapter 13 8 DMA Transfer Requests The UART3 has a function to generate DMA transfer requests from the causes shown in Table 13 8 1 Table 13 8 1 DMA Transfer Request Causes of UART3 Cause to reques...

Page 169: ...0 R W No clock supplied in DEBUG mode Bits 7 6 Reserved Bits 5 4 CLKDIV 1 0 These bits select the division ratio of the UART3 operating clock Bits 3 2 Reserved Bits 1 0 CLKSRC 1 0 These bits select the clock source of the UART3 Table 13 9 1 Clock Source and Division Ratio Settings UART3_nCLK CLKDIV 1 0 bits UART3_nCLK CLKSRC 1 0 bits 0x0 0x1 0x2 0x3 IOSC OSC1 OSC3 EXOSC 0x3 1 8 1 1 1 8 1 1 0x2 1 4...

Page 170: ...function 0 R W Disable carrier modulation function Bit 10 BRDIV This bit sets the UART3 operating clock division ratio for generating the transfer sampling clock using the baud rate generator 1 R W 1 4 0 R W 1 16 Bit 9 INVRX This bit enables the USINn input inverting function 1 R W Enable input inverting function 0 R W Disable input inverting function Bit 8 INVTX This bit enables the USOUTn output...

Page 171: ...e UART3_nMOD register settings can be altered only when the UART3_nCTL MODEN bit 0 Do not set both the UART3_nMOD IRMD and UART3_nMOD CAREN bits simultaneously UART3 Ch n Baud Rate Register Register name Bit Bit name Initial Reset R W Remarks UART3_nBR 15 12 0x0 R 11 8 FMD 3 0 0x0 H0 R W 7 0 BRT 7 0 0x00 H0 R W Bits 15 12 Reserved Bits 11 8 FMD 3 0 Bits 7 0 BRT 7 0 These bits set the UART3 transfe...

Page 172: ...RT3 operations The operating clock is stopped Note If the UART3_nCTL MODEN bit is altered from 1 to 0 while sending receiving data the data being sent received cannot be guaranteed When setting the UART3_nCTL MODEN bit to 1 again after that be sure to write 1 to the UART3_nCTL SFTRST bit as well UART3 Ch n Transmit Data Register Register name Bit Bit name Initial Reset R W Remarks UART3_nTXD 15 8 ...

Page 173: ...re 13 5 3 1 1 R During sending 0 R Idle Bit 8 TBSY This bit indicates the sending status See Figure 13 5 2 1 1 R During sending 0 R Idle Bit 7 Reserved Bit 6 TENDIF Bit 5 FEIF Bit 4 PEIF Bit 3 OEIF Bit 2 RB2FIF Bit 1 RB1FIF Bit 0 TBEIF These bits indicate the UART3 interrupt cause occurrence status 1 R Cause of interrupt occurred 0 R No cause of interrupt occurred 1 W Clear flag 0 W Ineffective Th...

Page 174: ...r Empty DMA Request Enable Register Register name Bit Bit name Initial Reset R W Remarks UART3_nT BEDMAEN 15 0 TBEDMAEN 15 0 0x0000 H0 R W Bits 15 0 TBEDMAEN 15 0 These bits enable the UART3 to issue a DMA transfer request to the corresponding DMA controller channel Ch 0 Ch 15 when a transmit buffer empty state has occurred 1 R W Enable DMA transfer request 0 R W Disable DMA transfer request Each ...

Page 175: ...on S1C31D50 TECHNICAL MANUAL Rev 1 00 UART3_nCAWF 15 8 0x00 R 7 0 CRPER 7 0 0x00 H0 R W Bits 15 8 Reserved Bits 7 0 CRPER 7 0 These bits set the carrier modulation output frequency For more information refer to Carrier Modulation ...

Page 176: ... being operated with the external input clock SPICLKn only Slave mode is capable of being operated in SLEEP mode allowing wake up by an SPIA interrupt Input pins can be pulled up down with an internal resistor Figure 14 1 1 shows the SPIA configuration Table 14 1 1 SPIA Channel Configuration of S1C31D50 Item S1C31D50 Number of channels 3 channels Ch 0 Ch 1 and Ch 2 Internal clock input Ch 0 16 bit...

Page 177: ...tput function must be assigned to the port before activating SPIA For more information refer to the I O Ports chapter 14 2 2 External Connections SPIA operates in master mode or slave mode Figures 14 2 2 1 and 14 2 2 2 show connection diagrams between SPIA in each mode and external SPI devices Figure 14 2 2 1 Connections between SPIA in Master Mode and External SPI Slave Devices Figure 14 2 2 2 Co...

Page 178: ... accord ing to the input clock SPISSn Not used This input function is not required to be assigned to the port To output the slave select signal in master mode use a general purpose I O port function Applying a low level to the SPISSn pin enables SPIA to transmit receive data While a high level is applied to this pin SPIA is not selected as a slave device Data input to the SDIn pin and the clock in...

Page 179: ... may be used for an other purpose Use the 16 bit timer as a baud rate generator By setting the SPIA_nMOD NOCLKDIV bit to 0 SPIA inputs the underflow signal generated by the corresponding 16 bit timer channel and converts it to the SPICLKn The 16 bit timer must be run with an appropriate reload data set The SPICLKn frequency baud rate and the 16 bit timer reload data are calculated by the equations...

Page 180: ...y Figure 14 3 3 1 shows the clock waveform and data input output timing in each setting Figure 14 3 3 1 SPI Clock Phase and Polarity SPIA_nMOD LSBFST bit 0 SPIA_nMOD CHLN 3 0 bits 0x7 14 4 Data Format The SPIA data length can be selected from 2 bits to 16 bits by setting the SPIA_nMOD CHLN 3 0 bits The input output permutation is configurable to MSB first or LSB first using the SPIA_nMOD LSBFST bi...

Page 181: ...er Mode A data sending procedure and operations in master mode are shown below Figures 14 5 2 1 and 14 5 2 2 show a timing chart and a flowchart respectively Data sending procedure 1 Assert the slave select signal by controlling the general purpose output port if necessary 2 Check to see if the SPIA_nINTF TBEIF bit is set to 1 transmit buffer empty 3 Write transmit data to the SPIA_nTXD register 4...

Page 182: ...DIF Data W SPIA_nTXD SPICLKn SDOn SPIA_nINTF TBEIF SPIA_nINTF TENDIF Software operations 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Data transmission Assert the slave select signal output from a general purpose port Read the SPIA_nINTF TBEIF bit End Negate the slave select signal output from a general purpose port Write transmit data to the SPIA_nTXD register SPIA_nINTF TBEIF 1 Transmit data ...

Page 183: ...rol data must be set for the DMA controller and the relevant DMA channel must be enabled to start a DMA transfer in advance so that transmit data will be transferred to the SPIA_nTXD register For more information on DMA refer to the DMA Controller chapter Table 14 5 2 1 DMA Data Structure Configuration Example for 16 bit Data Transmission Item Setting example End pointer Transfer source Memory add...

Page 184: ...ay be dummy data if data transmission is not required is written to the SPIA_nTXD register The SPICLKn pin outputs clocks of the number of the bits specified by the SPIA_nMOD CHLN 3 0 bits The transmit data bits are output in sequence from the SDOn pin in sync with these clocks and the receive data bits input from the SDIn pin are shifted into the shift register When the last clock is output from ...

Page 185: ... Writing 16 bit Dummy Transmit Data Item Setting example End pointer Transfer source Memory address in which dummy data is stored Transfer destination SPIA_nTXDregisteraddress Control data dst_inc 0x3 no increment dst_size 0x1 haflword src_inc 0x3 no increment src_size 0x1 halfword R_power 0x0 arbitrated for every transfer n_minus_1 Number of transfer data cycle_ctrl 0x1 basic transfer Table 14 5 ...

Page 186: ...time the sending SPIA_nTXD register data written is completed If no transmit data is written during this period the data bits input from the SDIn pin are shifted and output from the SDOn pin without being modified Data receiving procedure 1 Wait for a receive buffer full interrupt SPIA_nINTF RBFIF bit 1 2 Read the received data from the SPIA_nRXD register 3 Repeat Steps 1 and 2 until the end of da...

Page 187: ...5 5 2 Data Transfer Flowcharts in Slave Mode 14 5 6 Terminating Data Transfer in Slave Mode A procedure to terminate data transfer in slave mode is shown below 1 Wait for an end of transmission interrupt SPIA_nINTF TENDIF bit 1 Or determine end of transfer via the received data 2 Set the SPIA_nCTL MODEN bit to 0 to disable the SPIA Ch n operations 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Da...

Page 188: ...receive data buffer is full when the re ceived data has not been read at the point that receiving data to the shift register has completed Writing 1 SPIA provides interrupt enable bits corresponding to each interrupt flag An interrupt request is sent to the CPU core only when the interrupt flag of which interrupt has been enabled by the interrupt enable bit is set For more information on interrupt...

Page 189: ...hen transmit data written to the transmit data buffer is transferred to the shift register Writing to the SPIA_nTXD register The SPIA provides DMA transfer request enable bits corresponding to each DMA transfer request flag shown above for the number of DMA channels A DMA transfer request is sent to the pertinent channel of the DMA controller only when the DMA transfer request flag of which DMA tr...

Page 190: ...13 bits 0xb 12 bits 0xa 11 bits 0x9 10 bits 0x8 9 bits 0x7 8 bits 0x6 7 bits 0x5 6 bits 0x4 5 bits 0x3 4 bits 0x2 3 bits 0x1 2 bits 0x0 Setting prohibited Bits 7 6 Reserved Bit 5 PUEN This bit enables pull up down of the input pins 1 R W Enable pull up down 0 R W Disable pull up down For more information refer to Input Pin Pull Up Pull Down Function Bit 4 NOCLKDIV This bit selects SPICLKn in maste...

Page 191: ...se bits set the SPI clock phase and polarity For more information refer to SPI Clock SPICLKn Phase and Polarity Bit 0 MST This bit sets the SPIA operating mode master mode or slave mode 1 R W Master mode 0 R W Slave mode Note The SPIA_nMOD register settings can be altered only when the SPIA_nCTL MODEN bit 0 ...

Page 192: ...be sure to write 1 to the SPIA_nCTL SFTRST bit as well SPIA Ch n Transmit Data Register Register name Bit Bit name Initial Reset R W Remarks SPIA_nTXD 15 0 TXD 15 0 0x0000 H0 R W Bits 15 0 TXD 15 0 Data can be written to the transmit data buffer through these bits In master mode writing to these bits starts data transfer Transmit data can be written when the SPIA_nINTF TBEIF bit 1 regardless of wh...

Page 193: ...t indicates the SPIA operating status 1 R Transmit receive busy master mode SPISSn Low level slave mode 0 R Idle Bits 6 4 Reserved Bit 3 OEIF Bit 2 TENDIF Bit 1 RBFIF Bit 0 TBEIF These bits indicate the SPIA interrupt cause occurrence status 1 R Cause of interrupt occurred 0 R No cause of interrupt occurred 1 W Clear flag OEIF TENDIF 0 W Ineffective The following shows the correspondence between t...

Page 194: ... name Initial Reset R W Remarks SPIA_nTBEDMAEN 15 0 TBEDMAEN 15 0 0x0000 H0 R W Bits 15 0 TBEDMAEN 15 0 These bits enable the SPIA to issue a DMA transfer request to the corresponding DMA channel Ch 0 Ch 15 when a transmit buffer empty state has occurred 1 R W Enable DMA transfer request 0 R W Disable DMA transfer request Each bit corresponds to a DMA controller channel The high order bits for the...

Page 195: ...PICLKn only Slave mode is capable of being operated in SLEEP mode allowing wake up by a QSPI interrupt Input pins can be pulled up down with an internal resistor Low CPU overhead memory mapped access mode that can access the external Flash memory with XIP eXecute In Place mode in the same manner as the embedded system memory Memory mapped access size 8 16 and 32 bit access 1M byte external Flash m...

Page 196: ...ernal state machine In this case only one external QSPI device can be connected When QSPI Ch n is operating in register access master mode the QSPISSn output is directly controlled by a register bit In this case GPIO pins other than QSPISSn can also be used as the slave select output ports to connect the QSPI to more than one external QSPI device Figures 15 2 2 1 to 15 2 2 7 show connection diagra...

Page 197: ...de and External Dual I O SPI Slave Devices QSPISSn QSDIOn3 QSDIOn2 QSDIOn1 QSDIOn0 QSPICLKn QSPISS QSDIO3 QSDIO2 QSDIO1 QSDIO0 QSPICLK S1C31 QSPI memory mapped access mode External QSPI slave device QSPISSn Px1 Px2 QSDIOn1 QSDIOn0 QSPICLKn S1C31 QSPI register access master mode SPISS SDO SDI SPICK SPISS SDO SDI SPICK SPISS SDO SDI SPICK External single I O SPI slave devices QSPISSn Px1 Px2 QSDIOn1...

Page 198: ...y SPI Master Device QSPISSn Px1 Px2 QSDIOn3 QSDIOn2 QSDIOn1 S1C31 QSPI register access master mode QSPISS QSDIO3 QSDIO2 QSDIO1 External QSPI slave devices QSDIOn0 QSPICLKn QSDIO0 QSPICLK QSPISS QSDIO3 QSDIO2 QSDIO1 QSDIO0 QSPICLK QSPISS QSDIO3 QSDIO2 QSDIO1 QSDIO0 QSPICLK QSPISSn QSDIOn1 QSDIOn0 QSPICLKn S1C31 QSPI register access master mode External single I O SPI master device SPISS0 SPISS1 SPI...

Page 199: ...xternal dual I O SPI slave devices External dual I O SPI master device SPISS0 SPISS1 SPISS2 SDIO1 SDIO0 SPICK SPISS SDIO1 SDIO0 SPICK SPISS SDIO1 SDIO0 SPICK S1C31 QSPI slave mode QSPISSn QSDIOn3 QSDIOn2 QSDIOn1 QSDIOn0 QSPICLKn S1C31 QSPI register access master mode QSPISS0 QSPISS1 QSPISS2 QSDIO3 External QSPI master device QSPISSn QSDIOn3 QSDIOn2 QSDIOn1 QSDIOn0 QSPICLKn QSPISSn QSDIOn3 QSDIOn2 ...

Page 200: ...laced into output state This pin is placed into output state while a low level is applied to the QSPISSn pin or placed into Hi Z state while a high level is applied to the QSPISSn pin QSPICLKn Outputs the QSPI clock to external devices Output clock polarity and phase can be configured if nec essary Inputs an external QSPI clock Clock polarity and phase can be designated according to the input cloc...

Page 201: ...ns shown below 𝑓𝑄𝑆𝑃𝐼𝐶𝐿𝐾 𝑓𝐶𝐿𝐾_𝑄𝑆𝑃𝐼 2 𝑅𝐿𝐷 1 𝑅𝐿𝐷 𝑓𝐶𝐿𝐾_𝑄𝑆𝑃𝐼 𝑓𝐶𝐿𝐾_𝑄𝑆𝑃𝐼 2 1 𝐸𝑞 15 1 Where fQSPICLK QSPICLKn frequency Hz baud rate bps fCLK_QSPI QSPI operating clock frequency Hz RLD 16 bit timer reload data value For controlling the 16 bit timer refer to the 16 bit Timers chapter Operating clock in slave mode The QSPI set in slave mode operates with the clock supplied from the external SPI QSPI master ...

Page 202: ...es in different transfer modes QSPI_nMOD TMOD 1 0 when the QSPI_nMOD CPOL bit 0 and the QSPI_nMOD CPHA bit 0 Figure 15 4 1 Data Format Selection for Single Transfer Mode Using the QSPI_nMOD LSBFST Bit QSPI_nMOD TMOD 1 0 bits 0x0 QSPI_nMOD CHLN 3 0 bits 0x7 QSPI_nMOD CPOL bit 0 QSPI_nMOD CPHA bit 0 MSB LSB MSB LSB MSB LSB MSB LSB Writing data to the QSPI_nTXD register QSPI_nMOD register CPOL bit CP...

Page 203: ... Dr8 Dr10 Dr12 Dr14 Dr1 Dr3 Dr5 Dr7 Dr9 Dr11 Dr13 Dr15 Dr15 Dr13 Dr11 Dr9 Dr7 Dr5 Dr3 Dr1 Writing Dw 15 0 to the QSPI_nTXD register Loading Dr 15 0 to the QSPI_nRXD register QSPI_nMOD LSBFST bit 1 2 3 5 6 4 7 8 QSPICLKn QSDIOn1 QSDIOn0 QSDIOn1 Cycle No QSDIOn0 0 1 QSDIOn1 QSDIOn0 QSDIOn1 QSDIOn0 Dw15 Dw11 Dw7 Dw3 Dw1 Dw5 Dw9 Dw13 Dw14 Dw10 Dw6 Dw2 Dr14 Dr10 Dr6 Dr2 Dw0 Dw4 Dw8 Dw12 Dr0 Dr4 Dr8 Dr1...

Page 204: ...ed access mode is a low CPU overhead operation mode used with master mode to read data from an external Flash memory which supports XIP eXecute In Place mode Once the external Flash memory enters XIP mode and a read command is executed the same read command operation can be performed by controlling the slave select signal inactive to active and sending a new address to be accessed without the comm...

Page 205: ... including a mode byte that specifies to terminate XIP mode Memory mapped access mode supports 8 16 and 32 bit read accesses The 32 bit access is mainly used to read data in a large memory block sequentially In this access up to two 32 bit data are prefetched into the internal FIFO Therefore zero wait read access is possible if the desired data has already been fetched in the FIFO The 8 and 16 bit...

Page 206: ...r mode QSPI_nMMACFG2 DUMTMOD 1 0 bits Select dummy cycle transfer mode QSPI_nMMACFG2 ADRTMOD 1 0 bits Select address cycle transfer mode QSPI_nMMACFG2 ADRCYC bit Select 24 or 32 bit address cycle QSPI_nMB XIPACT 7 0 bits Set XIP activation mode byte QSPI_nMB XIPEXT 7 0 bits Set XIP termination mode byte 4 Assign the QSPI Ch n input output function to the ports Refer to the I O Ports chapter 5 Set ...

Page 207: ...ten into the QSPI_nTXD register The transmit data in the QSPI_nTXD register is automatically transferred to the shift register and the QSPI_ nINTF TBEIF bit is set to 1 If the QSPI_nINTE TBEIE bit 1 transmit buffer empty interrupt enabled a transmit buffer empty interrupt occurs at the same time The QSPICLKn pin outputs clocks for the number of cycles specified by the QSPI_nMOD CHLN 3 0 bits and t...

Page 208: ...nformation on DMA refer to the DMA Controller chapter Table 15 5 4 1 DMA Data Structure Configuration Example for 16 bit Data Transmission Item Setting example End pointer Transfer source Memory address in which the last transmit data is stored Transfer destination QSPI_nTXDregisteraddress Control data dst_inc 0x3 no increment dst_size 0x1 haflword src_inc 0x1 2 src_size 0x1 halfword R_power 0x0 a...

Page 209: ...ations In single transfer mode QSPI_nMOD TMOD 1 0 bits 0 QSPI Ch n operates similar to legacy SPI devices The data receiving operation starts simultaneously with a data sending operation when transmit data may be dummy data if data transmission is not required is written to the QSPI_nTXD register Transmit data are output from the QSDIOn0 pin and receive data are input from the QSDIOn1 pin In dual ...

Page 210: ...urpose port End Negate the slave select signal output from the QSPISSn pin QSPI_nCTL MSTSSO 1 or a general purpose port Set the transfer direction to input QSPI_nCTL DIR 1 Data reception Read the QSPI_nINTF TBEIF bit Write dummy data or transmit data to the QSPI_nTXD register QSPI_nINTF TBEIF 1 Read receive data from the QSPI_nRXD register Receive data remained Wait for an interrupt request QSPI_n...

Page 211: ..._ nTXD register via DMA Ch x1 when the QSPI_nINTF TBEIF bit is set to 1 transmit buffer empty By setting the QSPI_nRBFDMAEN RBFDMAENx2 bit to 1 DMA transfer request enabled a DMA transfer request is sent to the DMA controller and the received data is transferred from the QSPI_nRXD register to the specified memory via DMA Ch x2 when the QSPI_nINTF RBFIF bit is set to 1 receive buffer full This auto...

Page 212: ... register 5 Clear the channel request masks for both the DMA channels using the DMA controller register 6 Clear the DMA transfer completion interrupt flags using the DMA controller register 7 Enable only the DMA transfer completion interrupt of the DMA channel used for reading using the DMA controller register 8 Clear pending DMA interrupts in the CPU core 9 Enable pending DMA interrupts in the CP...

Page 213: ...low The address cycle can be configured for 24 or 32 bit addresses and it consists of two transfer cycles The state machine determines actual Flash memory address from the memory mapped access area start address the read address in that area and the external Flash memory remapping start address set using the QSPI_ nRMADRH 31 20 bits The first transfer cycle is an 8 bit transfer that sends the high...

Page 214: ...NS HCLK HSIZE HREADY HRDATA fifo_read_level QSPI_nMOD register CPOL bit CPHA bit 1 1 0 0 QSPICLKn QSDIOn 3 0 0 Address cycle high order 8 16 bits Address cycle low order 16 bits Dummy cycle HSEL HADDR HTRANS HCLK HSIZE HREADY HRDATA fifo_read_level QSPI_nMOD register CPOL bit CPHA bit 1 1 0 0 Dummy cycle Data cycle 1 Data cycle 3 prefetching Data cycle 2 prefetching QSPICLKn QSDIOn 3 0 ...

Page 215: ... 2 Data Receiving Operation in Memory Mapped Access Mode 32 bit Sequential Read n n 4 n 8 2 2 1 0 n n 8 1 2 n 4 0 HSEL HADDR HTRANS HCLK HSIZE HREADY HRDATA fifo_read_level QSPI_nMOD register CPOL bit CPHA bit 1 1 0 0 QSPICLKn QSDIOn 3 0 Data cycle for n 8 Data cycle prefetching ...

Page 216: ...ata are not prefetched into the FIFO n 2 2 2 0 1 0 n HSEL HADDR HTRANS HCLK HSIZE HREADY HRDATA fifo_read_level QSPI_nMOD register CPOL bit CPHA bit 1 1 0 0 QSPICLKn QSDIOn 3 0 QSPISSn inactive period TCSH Address cycle high order 8 16 bits Address cycle low order 16 bits QSPISSn HSEL HADDR HTRANS HCLK HSIZE HREADY HRDATA fifo_read_level Address cycle low order 16 bits Data cycle for n Data cycle ...

Page 217: ... 8 16 bit Read n 2 0 1 n HSEL HADDR HTRANS HCLK HSIZE HREADY HRDATA QSPI_nMOD register CPOL bit CPHA bit 1 1 0 0 QSPICLKn QSDIOn 3 0 HSEL HADDR HTRANS HCLK HSIZE HREADY HRDATA QSPI_nMOD register CPOL bit CPHA bit 1 1 0 0 QSPICLKn QSDIOn 3 0 Address cycle low order 16 bits Dummy cycle Data cycle Dummy cycle Address cycle high order 8 16 bits ...

Page 218: ...NICAL MANUAL Rev 1 00 Figure 15 5 6 5 Data Receiving Operation in Memory Mapped Access Mode 8 16 bit Sequential Read n n 2 0 1 HSEL HADDR HTRANS HCLK HSIZE HREADY HRDATA QSPI_nMOD register CPOL bit CPHA bit 1 1 0 0 QSPICLKn QSDIOn 3 0 Data cycle ...

Page 219: ... 1 n HSEL HADDR HTRANS HCLK HSIZE HREADY HRDATA QSPI_nMOD register CPOL bit CPHA bit 1 1 0 0 QSPICLKn QSDIOn 3 0 HSEL HADDR HTRANS HCLK HSIZE HREADY HRDATA QSPI_nMOD register CPOL bit CPHA bit 1 1 0 0 QSPICLKn QSDIOn 3 0 Address cycle high order 8 16 bits Address cycle low order 16 bits Data cycle Address cycle low order 16 bits QSPISSn inactive period TCSH Dummy cycle ...

Page 220: ...ck transfer as it does not need to execute read commands and uses the data pre fetched into the FIFO Note however that the first data read must be performed via software or a software triggered DMA The transfer source destination and control data must be set for the DMA controller and the relevant DMA channel must be enabled to start a DMA transfer in advance For more information on DMA refer to t...

Page 221: ... interrupts in the CPU core 8 Enable the QSPI to issue DMA transfer requests to the DMA channel using the QSPI_nFRLDMAEN FRLDMAENx bit 9 Issue a software DMA transfer request to the DMA channel by setting the DMA controller register This operation is required to kickstart the first data fetching 10 Wait for a DMA interrupt 11 Disable DMA requests to be sent to the DMA channel using the QSPI_nFRLDM...

Page 222: ...n pin The data transfer rate is determined by the QSPICLKn frequency It is not necessary to control the 16 bit timer QSPI can operate as a slave device only when the slave select signal input from the external QSPI master to the QSPISSn pin is set to the active low level If QSPISSn high the software transfer control the QSPICLKn pin input and the QSDIOn pins input are all ineffective If the QSPISS...

Page 223: ... transfer via the received data 2 Set the QSPI_nCTL MODEN bit to 0 to disable the QSPI Ch n operations Data W QSPI_nTXD QSPI_nRXD Data R Data W QSPI_nTXD Data W QSPI_nTXD QSPI_nRXD Data R 2 3 4 1 2 3 4 1 2 3 4 1 2 1 QSPICLKn QSDIOn 3 0 QSPI_nINTF TBEIF QSPISSn QSPI_nINTF RBFIF Software operations Data reception End Read receive data from the QSPI_nRXD register Receive data remained Wait for an int...

Page 224: ...When transmit data written to the transmit data buffer is transferred to the shift register Writing to the QSPI_nTXD register Overrun error QSPI_nINTF OEIF When the receive data buffer is full when the re ceived data has not been read at the point that receiving data to the shift register has completed Writing 1 The QSPI provides interrupt enable bits corresponding to each interrupt flag An interr...

Page 225: ..._nMMACFG2 MMAEN 2 3 4 1 2 3 4 1 QSPI_nMOD register CPOL bit CPHA bit 1 1 0 0 QSPICLKn QSDIOn 3 0 Register access master mode QSPI_nINTF BSY QSPI_nINTF TENDIF QSPI_nMOD register CPOL bit CPHA bit 1 1 0 0 QSPISSn QSPI_nINTF BSY Slave mode QSPICLKn QSDIOn 3 0 QSPICLKn QSDIOn 3 0 QSPI_nINTF TENDIF QSPI_nMOD register CPOL bit CPHA bit 1 1 0 0 QSPISSn QSDIOn 3 0 Memory mapped access mode QSPICLKn QSPI_n...

Page 226: ...Memory mapped access FIFO data ready Memory mapped access FIFO data ready flag internalsignal When a 32 bit data is prefetched into the FIFO in memory mapped access mode When the FIFO read level is cleared to 0 The QSPI provides DMA transfer request enable bits corresponding to each DMA transfer request flag shown above for the number of DMA channels A DMA transfer request is sent to the pertinent...

Page 227: ...g is required to output the XIP confirmation bit to Micron Flash memories or to output the mode byte to Spansion Flash memories Table 15 8 1 Data Line Drive Length Settings QSPI_nMOD CHDL 3 0 bits Data line drive length 0xf 16 clocks 0xe 15 clocks 0xd 14 clocks 0xc 13 clocks 0xb 12 clocks 0xa 11 clocks 0x9 10 clocks 0x8 9 clocks 0x7 8 clocks 0x6 7 clocks 0x5 6 clocks 0x4 5 clocks 0x3 4 clocks 0x2 ...

Page 228: ...1 Dual transfer mode The QSDIOn 1 0 pins are configured as input or out put pins according to the QSPI_nMOD DIR bit setting The QSDIOn 3 2 pins are not used 0x0 Single transfer mode The QSDIOn0 and QSDIOn1 pins are configured as an output pin and an input pin respectively The QSDIOn 3 2 pins are not used Bit 5 PUEN This bit enables pull up down of the pins that are configured as an input or are no...

Page 229: ... QSPISSn high The device is deselected 0 R W QSPISSn low The device is selected In memory mapped access mode the QSPISSn pin is automatically controlled by the internal state machine Reading this bit allows monitoring of the current QSPISSn pin output status at any time Bit 1 SFTRST This bit issues software reset to QSPI 1 W Issue software reset 0 W Ineffective 1 R Software reset is executing 0 R ...

Page 230: ...ts that exceed the data bit length configured by the QSPI_nMOD CHLN 3 0 bits will not be output from the QSDIOn pin Note Be sure to avoid writing to the QSPI_nTXD register when the QSPI_nINTF TBEIF bit 0 Other wise transfer data cannot be guaranteed QSPI Ch n Receive Data Register Register name Bit Bit name Initial Reset R W Remarks QSPI_nRXD 15 0 RXD 15 0 0x0000 H0 R Bits 15 0 RXD 15 0 The receiv...

Page 231: ...1 R Transmit receive busy 0 R Idle Bit 6 MMABSY This bit indicates the QSPI memory mapped access operating status 1 R Memory mapped access state machine busy 0 R Idle Bits 5 4 Reserved Bit 3 OEIF Bit 2 TENDIF Bit 1 RBFIF Bit 0 TBEIF These bits indicate the QSPI interrupt cause occurrence status 1 R Cause of interrupt occurred 0 R No cause of interrupt occurred 1 W Clear flag OEIF TENDIF 0 W Ineffe...

Page 232: ...it name Initial Reset R W Remarks QSPI_nTBEDMAEN 15 0 TBEDMAEN 15 0 0x0000 H0 R W Bits 15 0 TBEDMAEN 15 0 These bits enable the QSPI to issue a DMA transfer request to the corresponding DMA channel Ch 0 Ch 15 when a transmit buffer empty state has occurred 1 R W Enable DMA transfer request 0 R W Disable DMA transfer request Each bit corresponds to a DMA controller channel The high order bits for t...

Page 233: ...eset R W Remarks QSPI_nMMACFG1 15 8 0x00 R 7 4 0x0 R 3 0 TCSH 3 0 0x0 H0 R W Bits 15 4 Reserved Bits 3 0 TCSH 3 0 When non sequential reading from a Flash memory address which is not continuous to the previous read address occurs in memory mapped access mode the QSPISSn signal is reasserted after negated once Then the new address is sent to the Flash memory before reading data The QSPI_nMMACFG1 TC...

Page 234: ... memory mapped access mode When the external Flash memory is read using the memory mapped access function the value specified here is added as an offset to the relative address in the memory mapped access area to generate the external Flash memory address to actually be accessed Note Make sure the QSPI_nMMACFG2 MMAEN 0 when altering the QSPI_nRMADRH RMADR 31 20 bits Figure 15 8 1 External Flash Me...

Page 235: ...ummy cycle output when accessing the external Flash memory in the memory mapped access mode This setting is required to output the XIP confirmation bit to Micron Flash memories or to output the mode byte to Spansion Flash memories Table 15 8 5 Settings of Data Line Drive Length during Dummy Cycle QSPI_nMMACFG2 DUMDL 3 0 bits Data line drive length 0xf 16 clocks 0xe 15 clocks 0xd 14 clocks 0xc 13 c...

Page 236: ...xternal Flash memory in the memory mapped access mode Table 15 8 6 Dummy Cycle Length Settings QSPI_nMMACFG2 DUMLN 3 0 bits Dummy cycle length 0xf 16 clocks 0xe 15 clocks 0xd 14 clocks 0xc 13 clocks 0xb 12 clocks 0xa 11 clocks 0x9 10 clocks 0x8 9 clocks 0x7 8 clocks 0x6 7 clocks 0x5 6 clocks 0x4 5 clocks 0x3 4 clocks 0x2 3 clocks 0x1 2 clocks 0x0 Setting prohibited ...

Page 237: ...pped access mode Bit 1 ADRCYC This bit selects the address mode from 24 and 32 bits when accessing the external Flash memory in the memory mapped access mode 1 R W 32 bit address mode 4 byte address cycle 0 R W 24 bit address mode 3 byte address cycle Bit 0 MMAEN This bit enables memory mapped access mode for accessing the external Flash memory 1 R W Enable memory mapped access mode 0 R W Disable ...

Page 238: ...ting an XIP session of the external Flash memory to be accessed in memory mapped access mode Bits 7 0 XIPEXT 7 0 These bits configure the mode byte for terminating the XIP session of the external Flash memory being accessed in memory mapped access mode Note In memory mapped access mode the mode byte is always output from the LSB first When using a Flash memory that expects the mode byte to be outp...

Page 239: ...te receive buffer full transmit buffer empty and other interrupts Can issue a DMA transfer request when a receive buffer full or a transmit buffer empty occurs Figure 16 1 1 shows the I2C configuration Table 16 1 1 I2C Channel Configuration of S1C31D50 Item S1C31D50 Number of channels 3 channels Ch 0 Ch 1 and Ch 2 Figure 16 1 1 I2C Configuration Interrupt control circuit BYTEENDIE GCIE NACKIE STOP...

Page 240: ...st be pulled up with an external resistor When the I2C is set into master mode one or more slave devices that have a unique address may be connected to the I2C bus When the I2C is set into slave mode one or more master and slave devices that have a unique address may be connected to the I2C bus Figure 16 2 2 1 Connections between I2C and External I2 C Devices Notes The SDA and SCL lines must be pu...

Page 241: ... easily Slave mode operating clock The I2C set to slave mode uses the SCL supplied from the I2C master as its operating clock The clock setting by the I2C_nCLK register is ineffective The I2C keeps operating using the clock supplied from the external I2C master even if all the internal clocks halt during SLEEP mode so the I2C can receive data and can generate receive buffer full interrupts 16 3 2 ...

Page 242: ... 3 1 Note The I2C bus transfer rate is limited to 100 kbit s in Bold mode or 400 kbit s in fast mode Do not set a transfer rate exceeding the limit Baud rate generator clock output and operations for supporting clock stretching Figure 16 3 3 1 shows the clock generated by the baud rate generator and the clock waveform on the I2C bus Figure 16 3 3 1 Baud Rate Generator Output Clock and SCLn Output ...

Page 243: ...ble interrupts 5 Set the following I2C_nCTL register bits Set the I2C_nCTL MST bit to 0 Set slave mode Set the I2C_nCTL SFTRST bit to 1 Execute software reset Set the I2C_nCTL MODEN bit to 1 Enable I2C Ch n operations 16 4 2 Data Transmission in Master Mode A data sending procedure in master mode and the I2C Ch n operations are shown below Figures 16 4 2 1 and 16 4 2 2 show an operation example an...

Page 244: ...smit buffer empty or the I2C_nINTF NACKIF bit is set to 1 NACK received setting the I2C_nCTL TXSTOP bit to 1 generates a STOP condition When the bus free time tBUF defined in the I2C Specifications has elapsed after the STOP condition has been generated the I2C_nCTL TXSTOP bit is cleared to 0 and the I2C_nINTF STOPIF bit is set to 1 When setting the I2C_nCTL TXSTART bit to 1 while the I2C_nINTF TB...

Page 245: ...o the I2C_ nTXD register For more information on DMA refer to the DMA Controller chapter Table 16 4 2 1 DMA Data Structure Configuration Example for Data Transmission Item Setting example End pointer Transfer source Memory address in which the last transmit data is stored Transfer destination I2C_nTXD register address Control data dst_inc 0x3 no increment dst_size 0x0 byte src_inc 0x0 1 src_size 0...

Page 246: ...TL TXSTOP to 1 to generate a STOP condition Then go to Step 10 7 When DMA is not used Read the received data from the I2C_nRXD register 8 8 If a NACK reception interrupt I2C_nINTF NACKIF bit 1 has occurred clear the I2C_nINTF NACKIF bit and issue a STOP condition by setting the I2C_nCTL TXSTOP bit to 1 Then go to Step 10 or Step 1 if making a retry 9 When DMA is not used Repeat Steps 5 to 7 until ...

Page 247: ...Data N 1 TXSTOP 0 STOPIF 1 A Data N P A A TXSTART 0 STARTIF 1 TBEIF 1 S TXSTART 0 STARTIF 1 TBEIF 1 NACKIF 1 TXSTOP 0 STOPIF 1 TXSTART 1 TXSTOP 1 P A NACKIF 1 TXSTART 1 Sr A A S TXSTART 0 STARTIF 1 TBEIF 1 TXSTART 0 STARTIF 1 TBEIF 1 TXSTART 1 TXSTOP 1 RXD 7 0 Data N TXSTOP 0 STOPIF 1 P TXSTART 1 RXD 7 0 Data N Sr RBFIF 1 TXNACK 0 RBFIF 1 TXNACK 0 RBFIF 1 TXNACK 0 S START condition Sr Repeated STA...

Page 248: ...e for Data Reception Item Setting example End pointer Transfer source I2C_nRXD register address Transfer destination Memory address to which the last received data is stored Control data dst_inc 0x0 1 dst_size 0x0 byte src_inc 0x3 no increment src_size 0x0 byte R_power 0x0 arbitrated for every transfer n_minus_1 Number of receive data cycle_ctrl 0x1 basic transfer Data reception Write 1 to the I2C...

Page 249: ...he data transfer direction to the I2C_nTXD TXD0 bit 4 Wait for a transmit buffer empty interrupt I2C_nINTF TBEIF bit 1 5 Write the second address to the I2C_nTXD TXD 7 0 bits 6 Wait for a transmit buffer empty interrupt I2C_nINTF TBEIF bit 1 7 Perform data transmission Starting data reception in 10 bit address mode 1 to 6 These steps are the same as the data transmission starting procedure describ...

Page 250: ...TART condition interrupt has occurred 6 Clear the I2C_nINTF STOPIF bit and then terminate data sending operations Data sending operations START condition detection and slave address check While the I2C_nCTL MODEN bit 1 and the I2C_nCTL MST bit 0 slave mode the I2C Ch n monitors the I2C bus When the I2C Ch n detects a START condition it starts receiving of the slave address sent from the master If ...

Page 251: ... bit data when an ACK from the external master is received At the same time the I2C_nINTF BYTEENDIF bit is set to 1 If a NACK is received the I2C_nINTF NACKIF bit is set to 1 without sending data STOP repeated START condition detection While the I2C_nCTL MST bit 0 slave mode and the I2C_nINTF BSY 1 the I2C Ch n monitors the I2C bus When the I2C Ch n detects a STOP condition it terminates data send...

Page 252: ...l call address response enabled the I2C Ch n starts data receiving operations when the general call address is received Slave mode can be operated even in SLEEP mode it makes it possible to wake the CPU up using an interrupt when an address match is detected Receiving the first data byte After the valid slave address has been received the I2C Ch n sends an ACK and pulls down SCL to low until 1 is ...

Page 253: ... Data 1 S A Saddr W A Data 2 Sr A RXD 7 0 Data 1 RXD 7 0 Data N 1 RXD 7 0 Data N RBFIF 1 BYTEENDIF 1 RBFIF 1 BYTEENDIF 1 RBFIF 1 BYTEENDIF 1 P A Data N Sr TXNACK 1 RXD 7 0 Data N 1 RXD 7 0 Data N RBFIF 1 BYTEENDIF 1 RBFIF 1 BYTEENDIF 1 BSY 0 TXNACK 0 STOPIF 1 TR 0 STARTIF 1 BSY 1 TXNACK 0 S START condition Sr Repeated START condition P STOP condition A ACK A NACK Saddr W Slave address W 0 Data n 8...

Page 254: ... is set to a low level at this time the I2C Ch n automatically executes bus clearing operations that output up to ten clocks from the SCLn pin with SDA left free state When SDA goes high from low within nine clocks the I2C Ch n issues a START condition and starts normal operations If SDA does not change from low when the I2C Ch n outputs the ninth clock it is regarded as an automatic bus clearing ...

Page 255: ...on Notification method 1 While the I2C Ch n controls SDA to high for sending address data or a NACK SDA low I2C_nINTF ERRIF 1 2 Master mode only When 1 is written to the I2C_nCTL TX START bit while the I2C_nINTF BSY bit 0 SCL low I2C_nINTF ERRIF 1 I2C_nCTL TXSTART 0 I2C_nINTF STARTIF 1 3 Master mode only When 1 is written to the I2C_nCTL TX STOP bit while the I2C_nINTF BSY bit 0 SCL low I2C_nINTF ...

Page 256: ...y accessed Writing 1 software reset START condition I2C_nINTF STARTIF Master mode When a START condition is issued Slave mode When an address match is detected including general call Writing 1 software reset Error detection I2C_nINTF ERRIF Refer to Error Detection Writing 1 software reset Receive buffer full I2C_nINTF RBFIF When received data is loaded to the receive data buffer Reading received dat...

Page 257: ...16 5 1 START STOP Condition Interrupt Timings TXSTART 0 STARTIF 1 TXSTART 1 TR 0 1 STARTIF 1 BSY 1 SDA Master mode SCL BRT 3 fCLK_I2Cn SDA Slave mode SCL Address matching the I2C_nOADR register 1 2 7 8 9 R W ACK TXSTOP 0 STOPIF 1 TXSTOP 1 RXD 7 0 read during reception BSY 0 STOPIF 1 SDA Master mode SCL BRT 3 3 fCLK_I2Cn SDA Slave mode SCL ...

Page 258: ...e When transmit data written to the transmit data buffer is transferred to theshift register or when an address match is detected with R W bit set to 1 Writing transmit data The I2C provides DMA transfer request enable bits corresponding to each DMA transfer request flag shown above for the number of DMA channels A DMA transfer request is sent to the pertinent channel of the DMA controller only whe...

Page 259: ...ng 0 R W No clock supplied during debugging Bits 7 6 Reserved Bits 5 4 CLKDIV 1 0 These bits select the division ratio of the I2C operating clock Bits 3 2 Reserved Bits 1 0 CLKSRC 1 0 These bits select the clock source of the I2C Table 16 7 1 Clock Source and Division Ratio Settings I2C_nCLK CLKDIV 1 0 bits I2C_nCLK CLKSRC 1 0 bits 0x0 0x1 0x2 0x3 IOSC OSC1 OSC3 EXOSC 0x3 1 8 1 1 1 8 1 1 0x2 1 4 1...

Page 260: ...Bit Bit name Initial Reset R W Remarks I2C_nBR 15 8 0x00 R 7 0 R 6 0 BRT 6 0 0x7f H0 R W Bits 15 7 Reserved Bits 6 0 BRT 6 0 These bits set the I2C Ch n transfer rate for master mode For more information refer to Baud Rate Generator Notes The I2C_nBR register settings can be altered only when the I2C_nCTL MODEN bit 0 Be sure to avoid setting the I2C_nBR register to 0 I2C Ch n Own Address Register ...

Page 261: ... Issue a STOP condition 0 W Ineffective 1 R On standby or during generating a STOP condition 0 R STOP condition has been generated This bit is automatically cleared when the bus free time tBUF defined in the I2C Specifications has elapsed after the STOP condition has been generated Bit 2 TXSTART This bit issues a START condition in master mode This bit is ineffective in slave mode 1 W Issue a STAR...

Page 262: ...t to 1 before writing data Note Be sure to avoid writing to the I2C_nTXD register when the I2C_nINTF TBEIF bit 0 otherwise transmit data cannot be guaranteed I2C Ch n Receive Data Register Register name Bit Bit name Initial Reset R W Remarks I2C_nRXD 15 8 0x00 R 7 0 RXD 7 0 0x00 H0 R Bits 15 8 Reserved Bits 7 0 RXD 7 0 The receive data buffer can be read through these bits I2C Ch n Status and Inte...

Page 263: ...TARTIF Bit 2 ERRIF Bit 1 RBFIF Bit 0 TBEIF These bits indicate the I2C interrupt cause occurrence status 1 R Cause of interrupt occurred 0 R No cause of interrupt occurred 1 W Clear flag 0 W Ineffective The following shows the correspondence between the bit and interrupt I2C_nINTF BYTEENDIF bit End of transfer interrupt I2C_nINTF GCIF bit General call address reception interrupt I2C_nINTF NACKIF b...

Page 264: ...t General call address reception interrupt I2C_nINTE NACKIE bit NACK reception interrupt I2C_nINTE STOPIE bit STOP condition interrupt I2C_nINTE STARTIE bit START condition interrupt I2C_nINTE ERRIE bit Error detection interrupt I2C_nINTE RBFIE bit Receive buffer full interrupt I2C_nINTE TBEIE bit Transmit buffer empty interrupt I2C Ch n Transmit Buffer Empty DMA Request Enable Register Register n...

Page 265: ...RBFDMAEN 15 0 0x0000 H0 R W Bits 15 0 RBFDMAEN 15 0 These bits enable the I2C to issue a DMA transfer request to the corresponding DMA controller channel Ch 0 Ch 15 when a receive buffer full state has occurred 1 R W Enable DMA transfer request 0 R W Disable DMA transfer request Each bit corresponds to a DMA controller channel The high order bits for the unimplemented channels are ineffective ...

Page 266: ...re to generate interrupt or DMA request signals and a PWM waveform Can be used as an interval timer PWM waveform generator and external event counter The capture circuit captures counter values using external software trigger signals and generates interrupts or DMA requests Can be used to measure external event periods cycles Figure 17 1 1 shows the T16B configuration Table 17 1 1 T16B Channel Con...

Page 267: ...arator capture block Ch n CLKDIV 3 0 MODEN MAXBSY DBRUN CLKSRC 2 0 Clock generator EXCL00 EXCL01 EXCLn0 EXCLn1 UP_DOWN BSY RUN PRESET CNTMD 1 0 ONEST TOUT control circuit 1 TOUT control circuit 0 Compare Capture 1 data register CC 15 0 CAPTRG 1 0 CBUFMD 2 0 CCMD MZDMAENx CCmDMAENx Interrupt control circuit DMA request control circuit Capture circuit 1 Capture circuit 0 Compare buffer 0 Compare buf...

Page 268: ...ering SLEEP mode After the CPU returns to normal mode CLK_T16Bn is supplied and the T16B operation resumes 17 3 3 Clock Supply During Debugging The CLK_T16Bn supply during debugging should be controlled using the T16B_nCLK DBRUN bit The CLK_T16Bn supply to T16B Ch n is suspended when the CPU enters debug state if the T16B_nCLK DBRUN bit 0 After the CPU returns to normal operation the CLK_T16Bn sup...

Page 269: ... T16B control bits when using DMA transfer Write 1 to the DMA transfer request enable bits in the T16B_nMZDMAEN and T16B_nCCmDMAEN registers Enable DMA transfer requests 8 Set the following T16B_nCTL register bits T16B_nCTL CNTMD 1 0 bits Select count up down operation T16B_nCTL ONEST bit Select one shot repeat operation Set the T16B_nCTL PRESET bit to 1 Reset counter Set the T16B_nCTL RUN bit to ...

Page 270: ... counter is set to repeat mode the MAX value can be rewritten in the procedure shown below even if the counter is running 1 Check to see if the T16B_nCTL MAXBSY bit is set to 0 2 Write the MAX value to the T16B_nMC MC 15 0 bits Note When rewriting the MAX value the new MAX value should be written after the counter has been reset to the previously set MAX value Counter reset Setting the T16B_nCTL P...

Page 271: ...p to the new MAX value If the MAX value is altered to a value smaller than the current counter value the counter is cleared to 0x0000 and continues counting up to the new MAX value In one shot up count mode the counter returns to 0x0000 if it exceeds the MAX value and stops automatically at that point 1 Repeat up count mode 2 One shot up count mode Figure 17 4 2 1 Operations in Repeat Up Count and...

Page 272: ... counting down to 0x0000 and continues counting down from the new MAX value after a counter under flow occurs In one shot down count mode the counter returns to the MAX value if a counter underflow occurs and stops automatically at that point 1 Repeat down count mode 2 One shot down count mode Figure 17 4 2 2 Operations in Repeat Down Count and One shot Down Count Modes RUN 1 RUN 1 MODEN 1 PRESET ...

Page 273: ...up down count mode the counter stops automatically when it reaches 0x0000 during count down operation 1 Repeat up down count mode 2 One shot up down count mode Figure 17 4 2 3 Operations in Repeat Up Down Count and One shot Up Down Count Modes 17 4 3 Comparator Capture Block Operations The comparator capture block functions as a comparator to compare the counter value with the register value set o...

Page 274: ...he counter reaches 0x0000 the T16B_nINTF CNTZEROIF bit counter zero interrupt flag is set to 1 1 Repeat up count mode 2 Repeat down count mode 3 Repeat up down count mode Figure 17 4 3 1 Operation Examples in Comparator Mode RUN 1 RUN 1 CMPCAPmIF 1 CNTMAXIF 1 CMPCAPmIF 1 CNTMAXIF 1 CMPCAPmIF 1 CNTMAXIF 1 PRESET 1 RUN 0 Software operation Hardware operation 0xffff 0x0000 Count cycle Counter Compari...

Page 275: ...ntrol for more information Compare buffer The comparator loads the comparison value which has been written to the T16B_nCCRm register to the compare buffer before comparing it with the counter value For example when generating a PWM wave form the waveform with the desired duty ratio may not be generated if the comparison value is altered asynchronous to the count operation To avoid this problem th...

Page 276: ...are buffer value RUN 1 Count cycle Compare period CMPCAPmIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CNTMAXIF 1 CNTMAXIF 1 CNTMAXIF 1 Data W CC 15 0 Data W CC 15 0 MODEN 1 PRESET 1 Data W MC 15 0 0xffff 0x0000 Counter MAX value T16B_nMC register Time Data W CC 15 0 Compare buffer value RUN 1 Count cycle Compare period CMPCAPmIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CNTMAXIF 1 CNTMAXIF 1 C...

Page 277: ...r value RUN 1 Count cycle Compare period CMPCAPmIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CNTZEROIF 1 CNTZEROIF 1 Data W CC 15 0 Data W CC 15 0 MODEN 1 PRESET 1 Data W MC 15 0 0xffff 0x0000 Counter MAX value T16B_nMC register Time Data W CC 15 0 Compare buffer value RUN 1 Count cycle Compare period CNTZEROIF 1 Software operation Hardware operation CMPCAPmIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CNT...

Page 278: ...ue RUN 1 Count cycle Compare period CNTZEROIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CNTZEROIF 1 CNTZEROIF 1 Data W CC 15 0 Data W CC 15 0 MODEN 1 PRESET 1 Data W MC 15 0 0xffff 0x0000 Counter MAX value T16B_nMC register Time Data W CC 15 0 Compare buffer value RUN 1 Count cycle Compare period CNTZEROIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CNTZEROIF 1 Data W CC ...

Page 279: ...counting down CNTMAXIF 1 CNTMAXIF 1 CNTZEROIF 1 CNTZEROIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CNTZEROIF 1 Data W CC 15 0 Data W CC 15 0 MODEN 1 PRESET 1 Data W MC 15 0 0xffff 0x0000 Counter MAX value T16B_nMC register Time Data W CC 15 0 Compare buffer value Count cycle Compare period during counting up CNTZEROIF 1 RUN 1 Compare period during counting down CNTZEROIF 1 CNTZEROIF 1 CMP...

Page 280: ...16B_nINTF CNTZEROIF bit is set to 1 when the counter reaches zero in down count mode This automates the compare period and count cycle settings of the timer counter The transfer source destination and control data must be set for the DMA controller and the relevant DMA channel must be enabled to start a DMA transfer in advance so that the setting data will be transferred to the T16B_nCCRm or T16B_...

Page 281: ...ure the counter value are selected using the T16B_nCCCTLm CAPIS 1 0 bits and the T16B_nCCCTLm CAPTRG 1 0 bits respectively When a specified trigger edge is input during counting the current counter value is loaded to the T16B_nCCRm register At the same time the T16B_nINTF CMPCAPmIF bit is set The interrupt occurred by this bit can be used to read the captured data from the T16B_nCCRm register For ...

Page 282: ...Nx bit to 1 DMA transfer request enabled in capture mode a DMA transfer request is sent to the DMA controller and the T16B_nCCRm register value is transferred to the specified memory via DMA Ch x when the T16B_nINTF CMPCAPmIF bit is set to 1 when data has been captured This automates reading and saving of capture data The transfer source destination and control data must be set for the DMA control...

Page 283: ...OUT signal waveform is changed by the MATCH and MAX ZERO signals Furthermore when the T16B_nCCCTLm TOUTMT bit is set to 1 the TOUT circuit uses the MATCH signal output from another system in the circuit pair 0 and 1 2 and 3 4 and 5 This makes it possible to change the signal twice within a counter cycle TOUT signal polarity The TOUT signal polarity active level can be set using the T16B_nCCCTLm TO...

Page 284: ... Toggle set mode 0x6 Reset set mode 0x7 MAX value 5 Compare buffer value 2 T16B_nCCCTLm TOUTINV bit 0 indicates the T16B_nCCCTLm TOUTMD 2 0 bit setting value 4 5 3 2 1 0 5 4 3 2 1 0 5 4 3 2 RUN PRESET Count clock T16B_nTC TC 15 0 MATCH signal ZERO signal T16B_nCCCTLm TOUTO TOUT output Software control mode 0x0 Set mode 0x1 Toggle reset mode 0x2 Set reset mode 0x3 Toggle mode 0x4 Reset mode 0x5 Tog...

Page 285: ...1 0 1 2 3 4 5 RUN PRESET Count clock T16B_nTC TC 15 0 MATCH signal MAX signal T16B_nCCCTLm TOUTO TOUT output Software control mode 0x0 Set mode 0x1 Toggle reset mode 0x2 Set reset mode 0x3 Toggle mode 0x4 Reset mode 0x5 Toggle set mode 0x6 Reset set mode 0x7 MAX value 5 Compare buffer value 2 T16B_nCCCTLm TOUTINV bit 0 indicates the T16B_nCCCTLm TOUTMD 2 0 bit setting value ...

Page 286: ... output Software control mode 0x0 TOUTn0 TOUTn1 Set mode 0x1 TOUTn0 TOUTn1 Toggle reset mode 0x2 TOUTn0 TOUTn1 Set reset mode 0x3 TOUTn0 MAX value 5 Compare buffer 0 value 2 Compare buffer 1 value 3 T16B_nCCCTLm TOUTINV bit 0 indicates the T16B_nCCCTLm TOUTMD 2 0 bit setting value TOUTn1 Toggle mode 0x4 TOUTn0 TOUTn1 Reset mode 0x5 TOUTn0 TOUTn1 Toggle set mode 0x6 TOUTn0 TOUTn1 Reset set mode 0x7...

Page 287: ...T output Software control mode 0x0 TOUTn0 TOUTn1 Set mode 0x1 TOUTn0 TOUTn1 Toggle reset mode 0x2 TOUTn0 TOUTn1 Set reset mode 0x3 TOUTn0 MAX value 5 Compare buffer 0 value 2 Compare buffer 1 value 3 T16B_nCCCTLm TOUTINV bit 0 indicates the T16B_nCCCTLm TOUTMD 2 0 bit setting value TOUTn1 Toggle mode 0x4 TOUTn0 TOUTn1 Reset mode 0x5 TOUTn0 TOUTn1 Toggle set mode 0x6 TOUTn0 TOUTn1 Reset set mode 0x...

Page 288: ...0 signal MATCH 1 signal T16B_nCCCTLm TOUTO TOUT output Software control mode 0x0 TOUTn0 TOUTn1 Set mode 0x1 TOUTn0 TOUTn1 Toggle reset mode 0x2 TOUTn0 TOUTn1 Set reset mode 0x3 TOUTn0 MAX value 5 Compare buffer 0 value 2 Compare buffer 1 value 3 T16B_nCCCTLm TOUTINV bit 0 indicates the T16B_nCCCTLm TOUTMD 2 0 bit setting value TOUTn1 Toggle mode 0x4 TOUTn0 TOUTn1 Reset mode 0x5 TOUTn0 TOUTn1 Toggl...

Page 289: ...uses shown in Table 17 6 1 Table 17 6 1 DMA Transfer Request Causes of T16B Cause to request DMA transfer DMA transfer request flag Set condition Clear condition Compare capture Compare capture flag T16B_nINTF CMPCAPmIF When the counter value becomes equal to the com pare buffer value in comparator mode When the counter value is loaded to the T16B_nCCRm register by a capture trigger input in captur...

Page 290: ...counter clock Bit 3 Reserved Bits 2 0 CLKSRC 2 0 These bits select the clock source of T16B Ch n Table 17 7 1 Clock Source and Division Ratio Settings T16B_nCLK CLKDIV 3 0 bits T16B_nCLK CLKSRC 2 0 bits 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 IOSC OSC1 OSC3 EXOSC EXCLn0 EXCLn1 EXCLn0 inverted input EXCLn1 inverted input 0xf 1 32 768 1 1 1 32 768 1 1 1 1 1 1 1 1 1 1 0xe 1 16 384 1 16 384 0xd 1 8 192 1 8 19...

Page 291: ...d with this selection and the T16B_nCTL CNTMD 1 0 bit settings see Table 17 7 2 Table 17 7 2 Count Mode T16B_nCTL CNTMD 1 0 bits Count mode T16B_nCTL ONEST bit 1 T16B_nCTL ONEST bit 0 0x3 Reserved 0x2 One shot up down count mode Repeat up down count mode 0x1 One shot down count mode Repeat down count mode 0x0 One shot up count mode Repeat up count mode Bit 2 RUN This bit starts stops counting 1 W ...

Page 292: ...t take effect only when the T16B_nCTL MODEN bit 1 T16B Ch n Max Counter Data Register Register name Bit Bit name Initial Reset R W Remarks T16B_nMC 15 0 MC 15 0 0xffff H0 R W Bits 15 0 MC 15 0 These bits are used to set the MAX value to preset to the counter For more information refer to Counter Block Operations MAX counter data register Notes When one shot mode is selected do not alter the T16B_n...

Page 293: ...t 4 CAPI2 Bit 3 CAPI1 Bit 2 CAPI0 These bits indicate the signal level currently input to the CAPnm pin 1 R Input signal High level 0 R Input signal Low level The following shows the correspondence between the bit and the CAPnm pin T16B_nCS CAPI5 bit CAPn5 pin T16B_nCS CAPI4 bit CAPn4 pin T16B_nCS CAPI3 bit CAPn3 pin T16B_nCS CAPI2 bit CAPn2 pin T16B_nCS CAPI1 bit CAPn1 pin T16B_nCS CAPI0 bit CAPn...

Page 294: ...tatus 1 R Cause of interrupt occurred 0 R No cause of interrupt occurred 1 W Clear flag 0 W Ineffective The following shows the correspondence between the bit and interrupt T16B_nINTF CAPOW5IF bit Capture 5 overwrite interrupt T16B_nINTF CMPCAP5IF bit Compare capture 5 interrupt T16B_nINTF CAPOW4IF bit Capture 4 overwrite interrupt T16B_nINTF CMPCAP4IF bit Compare capture 4 interrupt T16B_nINTF CA...

Page 295: ...bits enable T16B Ch n interrupts 1 R W Enable interrupts 0 R W Disable interrupts 1 The following shows the correspondence between the bit and interrupt T16B_nINTE CAPOW5IE bit Capture 5 overwrite interrupt T16B_nINTE CMPCAP5IE bit Compare capture 5 interrupt T16B_nINTE CAPOW4IE bit Capture 4 overwrite interrupt T16B_nINTE CMPCAP4IE bit Compare capture 4 interrupt T16B_nINTE CAPOW3IE bit Capture 3...

Page 296: ...in capture mode Table 17 7 3 Timings to Load Comparison Value to Compare Buffer T16B_nCCCTLm CBUFMD 2 0 bits Count mode Comparison Value load timing 0x7 0x5 Reserved 0x4 Up mode When the counter becomes equal to the comparison value set previously Also the counter is reset to 0x0000 simultaneously Down mode When the counter becomes equal to the comparison value set previously Also the counter is r...

Page 297: ...ring the T16B_nCCCTLm CAPIS 1 0 bits from 0x2 to 0x3 0x0 Not triggered disable capture function Bit 7 Reserved Bit 6 TOUTMT This bit selects whether the comparator MATCH signal of another system is used for generating the TOUTnm signal or not 1 R W Generate TOUT using two comparator MATCH signals of the comparator circuit pair 0 and 1 2 and 3 4 and 5 0 R W Generate TOUT using one comparator MATCH ...

Page 298: ...TOUTnm 1 The signal becomes inactive by the MATCHm 1 signal and it becomes active by the MATCHm signal 0x6 Toggle set mode 0 Up count mode Up down count mode TOUTnm The signal is inverted by the MATCH signal and it be comes active by the MAX signal Down count mode TOUTnm The signal is inverted by the MATCH signal and it be comes active by the ZERO signal 1 All count modes TOUTnm The signal is inve...

Page 299: ...rted by the MATCH signal and it becomes inactive by the MAX signal Down count mode TOUTnm The signal is inverted by the MATCH signal and it becomes inactive by the ZERO signal 1 All count modes TOUTnm The signal is inverted by the MATCHm signal and it becomes inactive by the MATCHm 1 signal TOUTnm 1 The signal is inverted by the MATCHm 1 signal and it becomes inactive by the MATCHm signal 0x1 Set ...

Page 300: ...Remarks T16B_nCCRm 15 0 CC 15 0 0x0000 H0 R W Bits 15 0 CC 15 0 In comparator mode this register is configured as the compare data register and used to set the com parison value to be compared with the counter value In capture mode this register is configured as the capture register and the counter value captured by the capture trigger signal is loaded ...

Page 301: ...fer request Each bit corresponds to a DMA controller channel The high order bits for the unimplemented channels are ineffective T16B Ch n Compare Capture m DMA Request Enable Register Register name Bit Bit name Initial Reset R W Remarks T16B_nCCmDMAEN 15 0 CCmDMAEN 15 0 0x0000 H0 R W Bits 15 0 CCmDMAEN 15 0 These bits enable T16B to issue a DMA transfer request to the corresponding DMA controller ...

Page 302: ...g function for continuous data transmission Output signal inverting function supporting various formats EL lamp drive waveform can be generated for an application example Figure 18 1 1 shows the REMC3 configuration Table 18 1 1 REMC3 Channel Configuration of S1C31D50 Item S1C31D50 Number of channels 1 transmitter channel Figure 18 1 1 REMC3 Configuration Carrier signal generator Data signal genera...

Page 303: ...C3 the REMC3 operating clock CLK_REMC3 must be supplied to the REMC3 from the clock generator The CLK_REMC3 supply should be controlled as in the procedure shown below 1 Enable the clock source in the clock generator if it is stopped refer to Clock Generator in the Power Supply Reset and Clocks chapter 2 Set the following REMC3CLK register bits REMC3CLK CLKSRC 1 0 bits Clock source selection REMC3...

Page 304: ...al cycle REMC3CARR CRDTY 7 0 bit Set carrier signal duty 6 Configure the following REMC3CCTL register bits REMC3CCTL CARREN bit Enable disable carrier modulation REMC3CCTL OUTINVEN bit Configure output signal polarity 7 Set the following bits when using the interrupt Write 1 to the interrupt flags in the REMC3INTF register Clear interrupt flags Set the interrupt enable bits in the REMC3INTE regist...

Page 305: ...CARR CRDTY 7 0 bits 2 REMC3CARR CRPER 7 0 bits 8 Figure 18 4 3 2 Example of Carrier Signal Generated The carrier signal frequency and duty ratio can be calculated by the equations shown below Carrier frequency 𝑓𝐶𝐿𝐾_REMC3 𝐶𝑅𝑃𝐸𝑅 1 Duty ratio 𝐶𝑅𝐷𝑇𝑌 1 𝐶𝑅𝑃𝐸𝑅 1 𝐸𝑞 18 1 Where fCLK_REMC3 CLK_REMC3 frequency Hz CRPER REMC3CARR CRPER 7 0 bit setting value 1 255 CRDTY REMC3CARR CRDTY 7 0 bit setting value 0 ...

Page 306: ...l generation is reset by the REMC3DBCTL PRESET bit and is started stopped by the REMC3DBCTL PRUN bit When the counter value is matched with the REMC3APLEN APLEN 15 0 bits compare AP the data signal waveform is inverted When the counter value is matched with the REMC3DBLEN DBLEN 15 0 bits compare DB the data signal waveform is inverted and the counter is reset to 0x0000 A different interrupt can be...

Page 307: ...BLEN DBLEN 15 0 bit values are loaded into the compare buffers provided respectively REMC3A PLEN buffer and REMC3DBLEN buffer and the 16 bit counter value is compared with the compare buffers The comparison values are loaded into the compare buffers when the 16 bit counter is matched with the REMC3D BLEN buffer when the count for the data length has completed Therefore the next transmit data can b...

Page 308: ...has been enabled by the interrupt enable bit is set For more information on interrupt control refer to the Interrupt chapter 18 6 Application Example Driving EL Lamp The REMC3 can be used to simply drive an EL lamp as an application example Figures 18 6 1 and 18 6 2 show an example of an EL lamp drive circuit and an example of the drive waveform generated respectively For details of settings and a...

Page 309: ...ck Bits 3 2 Reserved Bits 1 0 CLKSRC 1 0 These bits select the clock source of the REMC3 Table 18 7 1 Clock Source and Division Ratio Settings REMC3CLK CLKDIV 3 0 bits REMC3CLK CLKSRC 1 0 bits 0x0 0x1 0x2 0x3 IOSC OSC1 OSC3 EXOSC 0xf 1 32 768 1 1 1 32 768 1 1 0xe 1 16 384 1 16 384 0xd 1 8 192 1 8 192 0xc 1 4 096 1 4 096 0xb 1 2 048 1 2 048 0xa 1 1 024 1 1 024 0x9 1 512 1 512 0x8 1 256 1 256 1 256 ...

Page 310: ...ed or when 1 is written to the REMC3DBCTL REMCRST bit Bit 8 PRUN This bit starts stops counting by the internal counters 16 bit counter for data signal generation and 8 bit counter for carrier generation 1 W Start counting 0 W Stop counting 1 R Counting 0 R Idle Before the counter can start counting by this bit the REMC3DBCTL MODEN bit must be set to 1 While the counter is running writing 0 to the...

Page 311: ...setting the REMC3DBCTL MODEN bit to 1 again after that be sure to write 1 to the REMC3DBCTL REMCRST bit as well REMC3 Data Bit Counter Register Register name Bit Bit name Initial Reset R W Remarks REMC3DBCNT 15 0 DBCNT 15 0 0x0000 H0 S0 R Cleared by writing 1 to the REMC3DBCTL REMCRSTbit Bits 15 0 DBCNT 15 0 The current value of the 16 bit counter for data signal generation can be read out through...

Page 312: ...ter for data signal generation is running or not See Figure 18 4 4 1 1 R Running Counting 0 R Idle Bit 9 DBLENBSY This bit indicates whether the value written to the REMC3DBLEN DBLEN 15 0 bits is transferred to the REMC3DBLEN buffer or not See Figure 18 4 4 1 1 R Transfer to the REMC3DBLEN buffer has not completed 0 R Transfer to the REMC3DBLEN buffer has completed While this bit is set to 1 writi...

Page 313: ... it is in verted to low level when the counter exceeds the REMC3CARR CRDTY 7 0 bit setting value The carrier signal duty ratio is determined by this setting and the REMC3CARR CRPER 7 0 bit setting See Figure 18 4 3 2 Bits 7 0 CRPER 7 0 These bits set the carrier signal cycle A carrier signal cycle begins with the 8 bit counter for carrier generation 0x00 and ends when the counter exceeds the REMC3...

Page 314: ...onfiguration Table 19 1 1 ADC12A Configuration of S1C31D50 Item S1C31D50 Number of channels 1 channel Ch 0 Number of analog signal inputs per channel Ch 0 8 inputs ADIN00 ADIN07 16 bit timer used as conversion clock and trigger sources Ch 0 16 bit timer Ch 7 VREFA pin reference voltage input Can be input externally Figure 19 1 1 ADC12A Configuration Note In this chapter n m and k refer to an ADC12...

Page 315: ... External Connections Figure 19 2 2 1 shows a connection diagram between the ADC12A and external devices Figure 19 2 2 1 Connections between ADC12A and External Devices 19 3 Clock Settings 19 3 1 ADC12A Operating Clock The 16 bit timer Ch k operating clock CLK_T16_k is also used as the ADC12A operating clock For more information on the CLK_T16_k settings and clock supply in SLEEP and DEBUG modes r...

Page 316: ...he ADC12A should be initialized with the procedure shown below 1 Assign the ADC12A input function to the ports Refer to the I O Ports chapter 2 Configure the 16 bit timer Ch k operating clock so that it will satisfy the sampling time 3 Set the ADC12A_nCTL MODEN bit to 1 Enable ADC12A operations 4 Configure the following ADC12A_nTRG register bits ADC12A_nTRG SMPCLK 2 0 bits Set sampling time ADC12A...

Page 317: ... The analog input signals within the specified range are A D converted successively in ascending order of the pin numbers One time conversion mode Once the ADC12A executes A D conversion for all the analog input signals within the specified range it is automatically stopped Continuous conversion mode The ADC12A repeatedly executes A D conversion within the specified range until 0 is written to the...

Page 318: ... 0 A D conversion for ADINn2 4 ADC12A_nTRG STAAIN 2 0 bits 0x2 ADC12A_nTRG ENDAIN 2 0 bits 0x4 Externaltrigger ADC12A_nTRG CNVTRG 1 0 bits 0x3 ADINn0 conversion result first ADINn0 conversion result second 0x0 ADINn0 0x1 ADINn1 0x0 ADINn0 0x1 ADINn1 0x0 ADINn0 ADC12A_nCTL ADST ADTRGn pin trigger ADC12A_nCTL BSYSTAT ADC12A_nCTL ADSTAT 2 0 A D conversion operations ADC12A_nADD ADD 15 0 ADC12A_nINTF ...

Page 319: ...annel must be enabled to start a DMA transfer in advance For more information on DMA refer to the DMA Controller chapter Table 19 4 4 1 DMA Data Structure Configuration Example Capture Data Transfer Item Setting example End pointer Transfer source ADC12A_nADD register address Transfer destination Memory address to which the last A D converted data is stored Control data dst_inc 0x1 2 dst_size 0x1 ...

Page 320: ...mation on interrupt control refer to the Interrupt chapter 19 6 DMA Transfer Requests The ADC12A has a function to generate DMA transfer requests from the causes shown in Table 19 6 1 Table 19 6 1 DMA Transfer Request Causes of ADC12A Cause to request DMA transfer DMA transfer request flag Set condition Clear condition Analog input signal m A D conversion completion A D conversion completion flag ...

Page 321: ... conversion is stopped after the maximum analog input pin number different in each model has been completed these bits indicate ADINn0 Bit 11 Reserved Bit 10 BSYSTAT This bit indicates whether the ADC12A is executing A D conversion or not 1 R W A D converting 0 R W Idle Bits 9 2 Reserved Bit 1 ADST This bit starts A D conversion or enables to accept triggers 1 R W Start sampling and conversion sof...

Page 322: ...C12A_nCTL BSYSTAT bit is set to 0 before altering the ADC12A_nTRG register Bits 15 14 Reserved Bits 13 11 ENDAIN 2 0 These bits set the analog input pin to be A D converted last See Table 19 7 1 for the relationship between analog input pins and bit setting values Note The analog input pin range to perform A D conversion must be set as ADC12A_nTRG ENDAIN 2 0 bits ADC12A_nTRG STAAIN 2 0 bits Bits 1...

Page 323: ... Table 19 7 2 Trigger Source Selection ADC12A_nTRG CNVTRG 1 0 bits Trigger source 0x3 ADTRGn pin external trigger 0x2 Reserved 0x1 16 bit timer Ch k underflow 0x0 ADC12A_nCTL ADST bit software trigger Bit 3 Reserved Bits 2 0 SMPCLK 2 0 These bits set the analog input signal sampling time Table 19 7 3 Sampling Time Settings ADC12A_nTRG SMPCLK 2 0 bits Sampling time Number of CLK_T16_k cycles 0x7 11...

Page 324: ...ccording to the operating voltage to perform A D conversion Be aware that ADC circuit current IADC flows if the ADC12_nCFG VRANGE 1 0 bits are set to a value other than 0x0 when the ADC12_nCTL BSYSTAT bit 1 ADC12A Ch n Interrupt Flag Register Register name Bit Bit name Initial Reset R W Remarks ADC12A_nINTF 15 9 0x00 R 8 OVIF 0 H0 R W Cleared by writing 1 7 AD7IF 0 H0 R W 6 AD6IF 0 H0 R W 5 AD5IF ...

Page 325: ...rrupt ADC12A_nINTE ADmCIE bit Analog input signal m A D conversion completion interrupt ADC12A Ch n DMA Request Enable Register m Register name Bit Bit name Initial Reset R W Remarks ADC12A_nDMAENm 15 0 ADCDMAEN 15 0 0x0000 H0 R W Bits 15 0 ADCDMAEN 15 0 These bits enable ADC12A to issue a DMA transfer request to the corresponding DMA controller channel Ch 0 Ch 15 when the A D conversion for each ...

Page 326: ...rmistor or a humidity sensor and a few passive elements resistor and capacitor Allows measurement counting by inputting external clocks Provides an output and continuous oscillation function for monitoring the oscillation frequency Can generate reference oscillation completion sensor A and B oscillation completion measurement counter overflow error and time base counter overflow error interrupts F...

Page 327: ... must be assigned to the port before activating the RFC For more information refer to the I O Ports chapter Note The RFINn pin goes to VSS level when the port is switched Be aware that large current may flow if the pin is biased by an external circuit 20 2 2 External Connections The figures below show connection examples between the RFC and external sensors For the oscillation mode and external cl...

Page 328: ... accuracy note however that the frequency should be determined so that the time base counter will not over flow during reference oscillation 20 3 2 Clock Supply in SLEEP Mode When using RFC during SLEEP mode the RFC operating clock TCCLK must be configured so that it will keep supplying by writing 0 to the CLGOSC xxxxSLPC bit for the TCCLK clock source 20 3 3 Clock Supply in DEBUG Mode The TCCLK s...

Page 329: ...nection of two resistive sensors to a channel AC oscillation mode for resistive sensor measurements This mode performs measurements by AC driving the reference resistor and the resistive sensor to oscillate Set the RFC into this mode when an AC bias resistive sensor is connected One resistive sensor only can be connected to a channel External clock input mode event counter mode This mode enables i...

Page 330: ...ounter is running read the counter value twice or more and check to see if the same value is read 20 4 4 Converting Operations and Control Procedure An R F conversion procedure and the RFC operations are shown below Although the following descriptions assume that the internal oscillation circuit is used external clock input mode can be controlled with the same procedure R F control procedure 1 Set...

Page 331: ...0 or the measurement counter overflows 0xffffff 0x000000 the RFC_nTRG SSENA bit or the RFC_nTRG SSENB bit that started oscillation is cleared to 0 and the sensor oscillation stops automatically The time base counter reaching 0x000000 sets the RFC_nINTF ESENAIF bit sensor A or the RFC_ nINTF ESENBIF bit sensor B to 1 indicating that the sensor oscillation has been terminated normally If the RFC_nIN...

Page 332: ...rances Large Power supply voltage fluctuations Large Parasitic capacitance and resistance of the board Middle Temperature Small Unevenness of IC quality Small 20 4 5 CR Oscillation Frequency Monitoring Function The CR oscillation clock RFCLK generated during converting operation can be output from the RFCLKOn pin for monitoring By setting the RFC_nCTL CONEN bit to 1 the RFC Ch n enters continuous o...

Page 333: ...nsor B oscillation completion RFC_nINTF ESENBIF When sensor B oscillation has been completed normally due to the time base counter reaching 0x000000 Writing 1 Measurement counter overflow error RFC_nINTF OVMCIF When sensor oscillation has been terminated abnormally due to a measurement counter overflow Writing 1 Time base counter overflow error RFC_nINTF OVTCIF When reference oscillation has been ...

Page 334: ...e 0 R W No clock supplied in DEBUG mode Bits 7 6 Reserved Bits 5 4 CLKDIV 1 0 These bits select the division ratio of the RFC operating clock Bits 3 2 Reserved Bits 1 0 CLKSRC 1 0 These bits select the clock source of the RFC Table 20 6 1 Clock Source and Division Ratio Settings RFC_nCLK CLKDIV 1 0 bits RFC_nCLK CLKSRC 1 0 bits 0x0 0x1 0x2 0x3 IOSC OSC1 OSC3 EXOSC 0x3 1 8 1 1 1 8 1 1 0x2 1 4 1 4 0...

Page 335: ...continuous oscillation 0 R W Disable continuous oscillation For more information refer to CR Oscillation Frequency Monitoring Function Bit 6 EVTEN This bit enables external clock input mode event counter mode 1 R W External clock input mode 0 R W Normal mode For more information refer to Operating Modes Note Do not input an external clock before the RFC_nCTL EVTEN bit is set to 1 The RFINn pin is ...

Page 336: ... This bit also indicates the CR oscillation status 1 W Start oscillation 0 W Stop oscillation 1 R Being oscillated 0 R Stopped Bit 0 SREF This bit controls CR oscillation for the reference resistor This bit also indicates the CR oscillation status 1 W Start oscillation 0 W Stop oscillation 1 R Being oscillated 0 R Stopped Notes Settings in this register are all ineffective when the RFC_nCTL MODEN ...

Page 337: ...6 bit access instruction The counter may not be set to the correct value if the high order value RFC_nMCH MC 23 16 bits is written first RFC Ch n Time Base Counter Low and High Registers Register name Bit Bit name Initial Reset R W Remarks RFC_nTCL 15 0 TC 15 0 0x0000 H0 R W RFC_nTCH 15 8 0x00 R 7 0 TC 23 16 0x00 H0 R W Or Register name Bit Bit name Initial Reset R W Remarks RFC_nTCL RFC_nTCH 31 2...

Page 338: ...ESENBIF bit Sensor B oscillation completion interrupt RFC_nINTF ESENAIF bit Sensor A oscillation completion interrupt RFC_nINTF EREFIF bit Reference oscillation completion interrupt RFC Ch n Interrupt Enable Register Register name Bit Bit name Initial Reset R W Remarks RFC_nINTE 15 8 0x00 R 7 5 0x0 R 4 OVTCIE 0 H0 R W 3 OVMCIE 0 H0 R W 2 ESENBIE 0 H0 R W 1 ESENAIE 0 H0 R W 0 EREFIE 0 H0 R W Bits 1...

Page 339: ...channel 0 75 125 5 step Sequential play of multiple sound files The features of the Memory Check functions are listed below On Chip RAM Check read write check algorithm or March C algorithm On Chip Flash Check CHECKSUM or CRC algorithm External QSPI Flash Check CHECKSUM or CRC algorithm the external flash memory with XIP eXecute In Place mode Figure 21 1 1 shows the HW Processor configuration Figu...

Page 340: ...2 2 show the reference circuit between the SDAC and the external Audio AMP Please check and follow Audio AMP specification Single Figure 21 2 2 1 Single Mode Connection Differential Figure 21 2 2 2 Differential Mode Connection Audio AMP Enable IN IN Cin Rin 39uF 510Ω 39uF 510Ω Cin Rin S1C31D50 PORT Enable Control SDACOUT_N Low Pass Filter cutoff 8kHz pull down if AMP Enable is Sleep Please check A...

Page 341: ...n Sound Play or Memory Check is changed Sound ROM Data Start Address and Sound ROM Data Size is changed Target Sound ROM Data is changed from internal Flash to external QSPI Flash Target Sound ROM Data is changed from external QSPI Flash to internal Flash KEYCODE is changed INTMASK is changed Figure 21 3 1 shows Function Configuration Flow Figure 21 3 1 Function Configuration Flow SLEEP MCU Start ...

Page 342: ... mode flow Figure 21 4 1 1 Standard Sound Play Function Mode Flow Clock Setting Clock Generator CLG Control Sound DAC External Audio AMP Setting Start up External AMP Enable Control Sound DAC Control Sound Play Operation Sound Play Configuration Sound Play Command Control Sound DAC External Audio AMP Setting Close Sound DAC Control External AMP Enable Control ...

Page 343: ... Wait refer to the Audio AMP specification 3 Set the SDAC_0 CLK register to 0x0102 4 Set the SDAC_0 DAT register to 0x0000 5 Set the SDAC_0 INTE register to 0x0000 6 Set the SDAC_0 INTF register to 0x0003 7 Set the SDAC_0 CTL register to 0x0001 8 Set the SDAC_0 MODE register to 0x0100 Sound Play Close 1 Check whether ch0 ch1 state are sp_state_idle 2 Set the SDAC_0 MODE register to 0x0000 3 Set th...

Page 344: ...p_state_idle This sp_state_idle means idle mode to set Sound Start command the state should be sp_state_idle clock is provided sp_state_play To set Sound Start command the state should be sp_state_idle After setting Sound Play command the state is moved to sp_state_play after finishing the play or setting Sound Stop command the state is moved to sp_state_idle sp_state_pause To set Pause command th...

Page 345: ...ate_play sp_state_mute sp_state_pause Command Pause Command Release Pause Command Mute Command Release Mute Command Sound Start Command Sound Stop Complete the playing HWPEN 0 in HW Processor Control Register HWPEN 1 in HW Processor Control Register sp_state_init MCU Start up SLEEP Set FUNCTION to Sound Play Sound Play Function ...

Page 346: ...t the following parameters FUNCTION Sound Play INTMASK ROMADDR ROMSIZE KEYCODE in Sound Play Function Registers See Table 21 4 14 1 Enable HWPCTL HWPEN Wait HWPINTF HWP0IF 1 Cortex Enable HW Processor HW Processor interrupts to cortex Sound Play Configuration Check STATE_0 sp_state_idle Check STATE_1 sp_state_idle Sound Play Function Set the priority of HW Processor interrupt Clear the pending of ...

Page 347: ...oved to sp_state_idle on default When state transition is occurred HW Processor makes an interrupt on default the interrupt can be masked by INTMASK on 21 4 14 1 Sound Play Function Registers Figure 21 4 6 1 shows Sound Start command flow Figure 21 4 6 1 Sound Start Command Flow Sound Completion Check STATE_x sp_state_idle Sound Start command Set HWPCMDTRG HWP0TRG Wait STATE_x sp_state_idle Set So...

Page 348: ...ng Sound Stop after current phrases command the playing stops after finishing a current phrase Figure 21 4 7 2 shows the stop timing after Sound Stop after current phrase command Figure 21 4 7 2 Stop Timing after Sound Stop after current phrase Command Figure 21 4 7 3 shows Sound Stop command flow Figure 21 4 7 3 Sound Stop Command Flow Smooth function Stop immediately command Sentence The tempera...

Page 349: ...sample value smooth function avoids the noise Figure 21 4 8 1 shows smooth function after Mute immediately command Figure 21 4 8 1 Smooth Function after Mute immediately Command Mute after current phrase After getting Mute after current phrase command Voice Audio Play mutes after finishing current phrase Figure 21 4 8 2 shows the mute timing after Mute after current phrase command Figure 21 4 8 2 ...

Page 350: ...laying releases mute immediately Even release muting at big sample value smooth function avoids the noise Figure 21 4 9 1 shows smooth function after Release Mute command Figure 21 4 9 1 Smooth Function after Release Mute Command Figure 21 4 9 2 shows Release Mute command flow Mute command check STATE_x sp_state_mute if necessary Set Sound Play COMMAND COMMAND_x MUTE_xxx in Sound Play Function Reg...

Page 351: ... Mute command check STATE_x sp_state_play if necessary Set Sound Play COMMAND COMMAND_x Release_Mute in Sound Play Function Registers See Table 21 4 14 1 Set HWPCMDTRG HWP0TRG Cortex Set HW Processor Wait HWPINTF HWP0IF 1 HW Processor interrupts to cortex Wait STATE_x sp_state_mute Wait STATUS READY sp_status_ready ...

Page 352: ...hrases command Voice Audio Play pauses after finishing current phrase Figure 21 4 10 2 shows the pause timing after Pause after current phrase command Figure 21 4 10 2 Pause Timing after Pause after current phrase Command Figure 21 4 10 3 shows Pause command flow Figure 21 4 10 3 Pause Command Flow Pause command check STATE_x sp_state_pause if necessary Set Sound Play COMMAND COMMAND_x PAUSE_xxx i...

Page 353: ...he noise Figure 21 4 11 1 shows smooth function after Release Pause command Figure 21 4 11 1 Smooth Function after Release Pause Command Figure 21 4 11 2 shows Release Pause command flow Figure 21 4 11 2 Release Pause command flow Release Pause command check STATE_x sp_state_play if necessary Set Sound Play COMMAND COMMAND_x Release_PAUSE in Sound Play Function Registers See Table 21 4 14 1 Set HW...

Page 354: ...w INTMASK TO_IDLE bit When this bit is enabled the interrupt generated when the state moves to sp_state_idle is masked INTMASK TO_PLAY bit When this bit is enabled the interrupt generated when the state moves to sp_state_play is masked INTMASK TO_PAUSE bit When this bit is enabled the interrupt generated when the state moves to sp_state_pause is masked INTMASK TO_MUTE bit When this bit is enabled ...

Page 355: ...rtex sets Ch0 Sentence Number to play SENTENCE_1 W cortex sets Ch1 Sentence Number to play Please set SENTENCE Number to play listed on EPSON Voice Data Creation PC Tool ESPER2 VOLUME_0 W cortex sets Ch0 Volume VOLUME_1 W cortex sets Ch1 Volume REPEAT_0 W cortex sets Ch0 Repeat time REPEAT_1 W cortex sets Ch1 Repeat time Please set VOLUME REPEAT for Ch0 and Ch1 SPEED_0 W cortex sets Voice Speed Pe...

Page 356: ... 0x03 Sound Stop after current phrase 0x04 Pause immediately 0x05 Pause after current phrase 0x06 Release Pause UNPAUSE 0x07 Mute immediately 0x08 Mute after current phrase 0x09 Release Mute immediately UNMUTE COMMAND_1 0x12 15 8 Reserved set to 0 W COMMAND 7 0 0x00 No Effect 0x01 Sound Start 0x02 Sound Stop Immediately 0x03 Sound Stop after current phrase 0x04 Pause immediately 0x05 Pause after c...

Page 357: ...te R STATE_1 0x42 STATE 15 0 R ERROR 0x44 ERROR 15 0 0000_0000_0000_0000 error_no_error non fatal error xxxx_xxxx_xxxx_xxx1 error_ch0_command xxxx_xxxx_xxxx_xx1x error_ch1_command xxxx_xxxx_xxxx_x1xx error_ch0_sentence_no xxxx_xxxx_xxxx_1xxx error_ch1_sentence_no xxxx_xxxx_1xxx_xxxx error_sdac_overflow fatal error xxxx_xxx1_xxxx_xxxx error_ch0_decode xxxx_xx1x_xxxx_xxxx error_ch1_decode xxx1_xxxx_...

Page 358: ...TATE_x sp_state_idle Sound Start command Set HWPCMDTRG HWP0TRG Set Sound Start command COMMAND_x Sound Start SENTENCE_x VOLUME_x REPEAT_x SPEED_0 only CH0 in Sound Function Register See Table 21 4 14 1 Check STATE_x sp_state_play if necessary Cortex Set HW Processor Wait HWPINTF HWP0IF 1 HW Processor interrupts to cortex Wait HWPINTF HWP0IF 1 HW Processor interrupts to cortex Wait STATE_x sp_state...

Page 359: ...gister See Table 21 4 14 1 Check STATE_x sp_state_play if necessary Cortex Set HW Processor Wait HWPINTF HWP0IF 1 HW Processor interrupts to cortex Wait STATE_x sp_state_idle Wait STATUS READY sp_status_ready Sound Stop command Wait HWPINTF HWP0IF 1 HW Processor interrupts to cortex Check STATE_x sp_state_idle Set Sound Stop COMMAND COMMAND_x STOP_xxx in Sound Play Function Registers See Table 21 ...

Page 360: ...rs See Table 21 4 14 1 Set HWPCMDTRG HWP0TRG Cortex Set HW Processor Wait HWPINTF HWP0IF 1 HW Processor interrupts to cortex Wait STATE_x sp_state_play Wait STATUS READY sp_status_ready Release Mute command check STATE_x sp_state_play if necessary Set Sound Play COMMAND COMMAND_x Release_Mute in Sound Play Function Registers See Table 21 4 14 1 Set HWPCMDTRG HWP0TRG Cortex Set HW Processor Wait HW...

Page 361: ...sters See Table 21 4 14 1 Set HWPCMDTRG HWP0TRG Cortex Set HW Processor Wait HWPINTF HWP0IF 1 HW Processor interrupts to cortex Wait STATE_x sp_state_play Wait STATUS READY sp_status_ready Release Pause command check STATE_x sp_state_play if necessary Set Sound Play COMMAND COMMAND_x Release_PAUSE in Sound Play Function Registers See Table 21 4 14 1 Set HWPCMDTRG HWP0TRG Cortex Set HW Processor Wa...

Page 362: ...ssary Cortex Set HW Processor Wait HWPINTF HWP0IF 1 HW Processor interrupts to cortex Sound Start command Set HWPCMDTRG HWP0TRG Wait STATE_CH0 sp_state_idle Set Sound Start command COMMAND_x Sound Start SENTENCE_x VOLUME_x REPEAT_x SPEED_0 only CH0 in Sound Function Register See Table 21 4 14 1 Check STATE_CH0 sp_state_play if necessary Cortex Set HW Processor Wait HWPINTF HWP0IF 1 HW Processor in...

Page 363: ... Check Function Mode Flow 21 5 2 Clock Setting On Memory Check Function any operating clock can be supplied For detail of the system clock settings refer to 2 Clock Generator in the Power Supply Reset and Clocks chapter Memory Check Operation Memory Check Configuration Memory Check Command Control Error Check Check Memory Check Result RAM Check Compare CHECKSUM or CRC Result FLASH Check ...

Page 364: ...am_rw To go to functional operation the state should be mc_state_idle After setting RAM Check R W Start command the state is moved to mc_state_ram_rw after finishing the RAM check or setting Memory Check Stop command the state is moved to mc_state_idle mc_state_ram_march_c To go to functional operation the state should be mc_state_idle After setting RAM Check MARCH C Start the state is moved to mc...

Page 365: ...Memory Check State Transition mc_state _idle mc_state _ram_march_c mc_state _checksum HWPEN 0 in HW Processor Control Register mc_state _init MCU Start up SLEEP mc_state _crc mc_state _ram_rw Set FUNCTION to Memory Check HWPEN 1 in HW Processor Control Register Memory Check Function ...

Page 366: ...heck Configuration Set the following parameters FUNCTION Memory Check Set Interrupt MASK in Memory Check Function Registers See Table 21 5 11 1 Enable HWPCTL HWPEN Wait HWPINTF HWP0IF 1 Cortex Enable HW Processor HW Processor interrupts to cortex Memory Check Configuration Check STATE mc_state_idle Memory Check Function Set the priority of HW Processor interrupt Clear the pending of HW Processor i...

Page 367: ... a state transition is occurred HW Processor makes an interrupt on default the interrupt can be masked by INTMASK on 21 5 11 Memory Check Function Registers Table 21 5 5 1 shows RAM Check R W Start command flow Figure 21 5 5 1 RAM Check R W Start Command Flow Check Completion Check STATE mc_state_idle RAM Check R W Start command Set HWPCMDTRG HWP0TRG Set Memory Check COMMAND COMMAND RAM Check RW S...

Page 368: ... HW Processor makes an interrupt on default the interrupt can be masked by INTMASK on 21 5 11 Memory Check Function Registers Table 21 5 6 1 shows RAM Check MARCH C Start command flow Figure 21 5 6 1 RAM Check March C Start Command Flow Check Completion Check STATE mc_state_idle RAM Check MARCH C Start command Set HWPCMDTRG HWP0TRG Set Memory Check COMMAND COMMAND RAM Check MARCH C Start MEMADDR M...

Page 369: ...checksum value When state transition is occurred HW Processor makes an interrupt on default the interrupt can be masked by INTMASK on 21 5 11 Memory Check Function Registers Table 21 5 7 1 shows FLASH CHECKSUM Start command flow Figure 21 5 7 1 FLASH CHECKSUM Start Command Flow Check Completion Check STATE mc_state_idle FLASH CHECKSUM Start command Set HWPCMDTRG HWP0TRG Set Memory Check COMMAND CO...

Page 370: ...are with original CRC value When a state transition is occurred HW Processor makes an interrupt on default the interrupt can be masked by INTMASK on 21 5 11 Memory Check Function Registers Table 21 5 8 1 shows FLASH CRC Start command flow Figure 21 5 8 1 FLASH CRC Start Command Flow Check Completion Check STATE mc_state_idle FLASH CRC Start command Set HWPCMDTRG HWP0TRG Set Memory Check COMMAND CO...

Page 371: ...ister in 21 5 11 Memory Check Function Registers The mask bits are listed below INTMASK TO_IDLE bit When this bit is enabled the interrupt is generated when the state moves to mc_state_idle is masked INTMASK TO_PROCESSING bit When this bit is enabled the interrupt is generated when the state moves to mc_state_ram_rw mc_state_ram_march_c mc_state_checksum or mc_state_crc is masked Figure 21 5 10 1 ...

Page 372: ...E W cortex sets Target Memory Size to check INITVALUE W cortex sets Initialization Value for Checksum or CRC Please set 0x00000000 before start FLASH CHECKSUM or FLASH CRC COMMAND W cortex sets command Please set Memory Check command STATE R cortex reads State Please check State to set next command ERROR R cortex reads HW Processor Error STATUS R cortex reads HW Processor Status PROCESSING cortex ...

Page 373: ...rt 0xFF Memory Check Stop STATE 0x40 STATE 15 0 0x0000 mc_state_init 0x0001 mc_state_idle 0x0002 mc_state_ram_rw 0x0003 mc_state_ram_march_c 0x0004 mc_state_checksum 0x0005 mc_state_crc R ERROR 0x44 ERROR 15 0 0000_0000_0000_0000 no_error non fatal error xxxx_xxxx_xxxx_xxx1 error_command fatal error x1xx_xxxx_xxxx_xxxx error_function_id 1xxx_xxxx_xxxx_xxxx error_others R STATUS 0x46 15 10 Reserved...

Page 374: ... HWP0IF STIF 0x0 H0 R W Bits 15 2 Reserved Bit 1 HWP1IF ERRIF This bit indicates the HW Processor interrupt cause occurrence status 1 R Cause of interrupt occurred 0 R No cause of interrupt occurred 1 W Setting prohibited 0 W Clear flag This interrupt shows error Bit 0 HWP0IF STIF This bit indicates the HW Processor interrupt cause occurrence status 1 R Cause of interrupt occurred 0 R No cause of ...

Page 375: ...ister Register name Bit Bit name Initial Reset R W Remarks HWPCMDTRG 15 1 0x00 R 0 HWP0TRG 0x0 H0 R W Bits 15 1 Reserved Bit 0 HWP0TRG This bit indicates the HW Processor command trigger 1 R Setting in progress 0 R Ready to set the command trigger 1 W Set the command trigger 0 W Setting prohibited ...

Page 376: ...he SDAC operating clock is supplied in DEBUG mode or not 1 R W Clock supplied in DEBUG mode 0 R W No clock supplied in DEBUG mode Bits 7 6 Reserved Bits 5 4 CLKDIV 1 0 These bits select the division ratio of the SDAC operating clock Bits 3 2 Reserved Bits 1 0 CLKSRC 1 0 These bits select the clock source of SDAC SDACCLK CLKDIV 1 0 SDACCLK CLKSRC 1 0 0x0 0x1 0x2 0x3 IOSC reserved OSC3 EXOSC 0x3 res...

Page 377: ...me Bit Bit name Initial Reset R W Remarks SDACMODE 15 9 0x00 R 8 PWMOUTEN 0x0 H0 R W 7 1 0x0 R 0 MODE 0x0 H0 R W Bits 15 9 Reserved Bit 8 PWMOUTEN This bit enables the PWM signal output 1 R W Enable PWM signal output 0 R W Disable PWM signal output Bits 7 1 Reserved Bit 0 MODE This bit always must be set to 0 SDAC Data Register Register name Bit Bit name Initial Reset R W Remarks SDACDAT 15 10 0x0...

Page 378: ...ause occurrence status 1 R Cause of interrupt occurred 0 R No cause of interrupt occurred 1 W Clear flag 0 W Ineffective This register is used by the HW Processor This register should not be written while the HW Processor is enabled SDAC Interrupt Enable Register Register name Bit Bit name Initial Reset R W Remarks SDACINTE 15 2 0x00 R 1 ERRIE 0x0 H0 R W 0 DATREQIE 0x0 H0 R W Bits 15 2 Reserved Bi...

Page 379: ...0 0x0020 043c 16 bit PWM Timer T16B Ch 0 0x0020 0440 0x0020 047c 16 bit PWM Timer T16B Ch 1 0x0020 0480 0x0020 048c 16 bit Timer T16 Ch 3 0x0020 04a0 0x0020 04ac 16 bit Timer T16 Ch 4 0x0020 04c0 0x0020 04cc 16 bit Timer T16 Ch 5 0x0020 04d0 0x0020 04de Synchronous Serial Interface SPIA Ch 2 0x0020 0600 0x0020 0614 UART UART3 Ch 1 0x0020 0620 0x0020 0634 UART UART3 Ch 2 0x0020 0660 0x0020 066c 16 ...

Page 380: ...GSCLK CLG System Clock Control Register 15 WUPMD 0 H0 R WP 14 0 R 13 12 WUPDIV 1 0 0x0 H0 R WP 11 10 0x0 R 9 8 WUPSRC 1 0 0x0 H0 R WP 7 6 0x0 R 5 4 CLKDIV 1 0 0x2 H0 R WP 3 2 0x0 R 1 0 CLKSRC 1 0 0x0 H0 R WP 0x0020 0042 CLGOSC CLG Oscillation Control Register 15 12 0x0 R 11 EXOSCSLPC 1 H0 R W 10 OSC3SLPC 1 H0 R W 9 OSC1SLPC 1 H0 R W 8 IOSCSLPC 1 H0 R W 7 4 0x0 R 3 EXOSCEN 0 H0 R W 2 OSC3EN 0 H0 R ...

Page 381: ...R W 3 0 R 2 OSC3STAIF 0 H0 R W Cleared by writing 1 1 OSC1STAIF 0 H0 R W 0 IOSCSTAIF 0 H0 R W 0x0020 004e CLGINTE CLG Interrupt Enable Register 15 9 0x00 R 8 OSC3TERIE 0 H0 R W 7 0 R 6 0 R 5 OSC1STPIE 0 H0 R W 4 OSC3TEDIE 0 H0 R W 3 0 R 2 OSC3STAIE 0 H0 R W 1 OSC1STAIE 0 H0 R W 0 IOSCSTAIE 0 H0 R W 0x0020 0050 CLGFOUT CLG FOUT Control Register 15 8 0x00 R 7 0 R 6 4 FOUTDIV 2 0 0x0 H0 R W 3 2 FOUTS...

Page 382: ...e Clock RTCA Address Register name Bit Bit name Initial Reset R W Remarks 0x0020 00c0 RTCACTLL RTCA Control Register Low Byte 7 0 R 6 RTCBSY 0 H0 R 5 RTCHLD 0 H0 R W Cleared by setting the RTCACTLL RTCRST bit to 1 4 RTC24H 0 H0 R W 3 0 R 2 RTCADJ 0 H0 R W Cleared by setting the RTCACTLL RTCRST bit to 1 1 RTCRST 0 H0 R W 0 RTCRUN 0 H0 R W 0x0020 00c2 RTCAALM1 RTCA Second Alarm Register 15 0 R 14 12...

Page 383: ...0 0x0 H0 R W 3 0 RTCMIL 3 0 0x0 H0 R W 0x0020 00cc RTCAMON RTCA Month Day Register 15 13 0x0 R 12 RTCMOH 0 H0 R W 11 8 RTCMOL 3 0 0x1 H0 R W 7 6 0x0 R 5 4 RTCDH 1 0 0x0 H0 R W 3 0 RTCDL 3 0 0x1 H0 R W 0x0020 00ce RTCAYAR RTCA Year Week Register 15 11 0x00 R 10 8 RTCWK 2 0 0x0 H0 R W 7 4 RTCYH 3 0 0x0 H0 R W 3 0 RTCYL 3 0 0x0 H0 R W 0x0020 00d0 RTCAINTF RTCA Interrupt Flag Register 15 RTCTRMIF 0 H0...

Page 384: ...e Initial Reset R W Remarks 0x0020 0100 SVD3CLK SVD3 Clock Control Register 15 9 0x00 R 8 DBRUN 1 H0 R WP 7 0 R 6 4 CLKDIV 2 0 0x0 H0 R WP 3 2 0x0 R 1 0 CLKSRC 1 0 0x0 H0 R WP 0x0020 0102 SVD3CTL SVD3 Control Register 15 VDSEL 0 H1 R WP 14 13 SVDSC 1 0 0x0 H0 R WP Writing takes effect when the SVD3CTL SVDMD 1 0 bits are not 0x0 12 8 SVDC 4 0 0x1e H1 R WP 7 4 SVDRE 3 0 0x0 H1 R WP 3 EXSEL 0 H1 R WP...

Page 385: ...0 R 8 PRUN 0 H0 R W 7 2 0x00 R 1 PRESET 0 H0 R W 0 MODEN 0 H0 R W 0x0020 0166 T16_0TR T16 Ch 0 Reload Data Register 15 0 TR 15 0 0xffff H0 R W 0x0020 0168 T16_0TC T16 Ch 0 Counter Data Register 15 0 TC 15 0 0xffff H0 R 0x0020 016a T16_0INTF T16 Ch 0 Interrupt Flag Register 15 8 0x00 R 7 1 0x00 R 0 UFIF 0 H0 R W Cleared by writing 1 0x0020 016c T16_0INTE T16 Ch 0 Interrupt Enable Register 15 8 0x00...

Page 386: ...PPORTP0INTF P0 Port Interrupt Flag Register 15 8 0x00 R 7 0 P0IF 7 0 0x00 H0 R W Cleared by writing 1 0x0020 0208 PPORTP0INTCTL P0 Port Interrupt Control Register 15 8 P0EDGE 7 0 0x00 H0 R W 7 0 P0IE 7 0 0x00 H0 R W 0x0020 020a PPORTP0CHATEN P0 Port Chattering Filter Enable Register 15 8 0x00 R 7 0 P0CHATEN 7 0 0x00 H0 R W 0x0020 020c PPORTP0MODSEL P0 Port Mode Select Register 15 8 0x00 R 7 0 P0SE...

Page 387: ...Interrupt Flag Register 15 8 0x00 R 7 0 P1IF 7 0 0x00 H0 R W Cleared by writing 1 0x0020 0218 PPORTP1INTCTL P1 Port Interrupt Control Register 15 8 P1EDGE 7 0 0x00 H0 R W 7 0 P1IE 7 0 0x00 H0 R W 0x0020 021a PPORTP1CHATEN P1 Port Chattering Filter Enable Register 15 8 0x00 R 7 0 P1CHATEN 7 0 0x00 H0 R W 0x0020 021c PPORTP1MODSEL P1 Port Mode Select Register 15 8 0x00 R 7 0 P1SEL 7 0 0x00 H0 R W 0x...

Page 388: ...Interrupt Flag Register 15 8 0x00 R 7 0 P2IF 7 0 0x00 H0 R W Cleared by writing 1 0x0020 0228 PPORTP2INTCTL P2 Port Interrupt Control Register 15 8 P2EDGE 7 0 0x00 H0 R W 7 0 P2IE 7 0 0x00 H0 R W 0x0020 022a PPORTP2CHATEN P2 Port Chattering Filter Enable Register 15 8 0x00 R 7 0 P2CHATEN 7 0 0x00 H0 R W 0x0020 022c PPORTP2MODSEL P2 Port Mode Select Register 15 8 0x00 R 7 0 P2SEL 7 0 0x00 H0 R W 0x...

Page 389: ...Interrupt Flag Register 15 8 0x00 R 7 0 P3IF 7 0 0x00 H0 R W Cleared by writing 1 0x0020 0238 PPORTP3INTCTL P3 Port Interrupt Control Register 15 8 P3EDGE 7 0 0x00 H0 R W 7 0 P3IE 7 0 0x00 H0 R W 0x0020 023a PPORTP3CHATEN P3 Port Chattering Filter Enable Register 15 8 0x00 R 7 0 P3CHATEN 7 0 0x00 H0 R W 0x0020 023c PPORTP3MODSEL P3 Port Mode Select Register 15 8 0x00 R 7 0 P3SEL 7 0 0x00 H0 R W 0x...

Page 390: ...Interrupt Flag Register 15 8 0x00 R 7 0 P4IF 7 0 0x00 H0 R W Cleared by writing 1 0x0020 0248 PPORTP4INTCTL P4 Port Interrupt Control Register 15 8 P4EDGE 7 0 0x00 H0 R W 7 0 P4IE 7 0 0x00 H0 R W 0x0020 024a PPORTP4CHATEN P4 Port Chattering Filter Enable Register 15 8 0x00 R 7 0 P4CHATEN 7 0 0x00 H0 R W 0x0020 024c PPORTP4MODSEL P4 Port Mode Select Register 15 8 0x00 R 7 0 P4SEL 7 0 0x00 H0 R W 0x...

Page 391: ...t Interrupt Flag Register 15 8 0x00 R 7 0 P5IF 7 0 0x00 H0 R W Cleared by writing 1 0x0020 0258 PPORTP5INTCTL P5 Port Interrupt Control Register 15 8 P5EDGE 7 0 0x00 H0 R W 7 0 P5IE 7 0 0x00 H0 R W 0x0020 025a PPORTP5CHATEN P5 Port Chattering Filter Enable Register 15 8 0x00 R 7 0 P5CHATEN 7 0 0x00 H0 R W 0x0020 025c PPORTP5MODSEL P5 Port Mode Select Register 15 8 0x00 R 7 0 P5SEL 7 0 0x03 H0 R W ...

Page 392: ...Interrupt Flag Register 15 8 0x00 R 7 0 P6IF 7 0 0x00 H0 R W Cleared by writing 1 0x0020 0268 PPORTP6INTCTL P6 Port Interrupt Control Register 15 8 P6EDGE 7 0 0x00 H0 R W 7 0 P6IE 7 0 0x00 H0 R W 0x0020 026a PPORTP6CHATEN P6 Port Chattering Filter Enable Register 15 8 0x00 R 7 0 P6CHATEN 7 0 0x00 H0 R W 0x0020 026c PPORTP6MODSEL P6 Port Mode Select Register 15 8 0x00 R 7 0 P6SEL 7 0 0x00 H0 R W 0x...

Page 393: ...Interrupt Flag Register 15 8 0x00 R 7 0 P7IF 7 0 0x00 H0 R W Cleared by writing 1 0x0020 0278 PPORTP7INTCTL P7 Port Interrupt Control Register 15 8 P7EDGE 7 0 0x00 H0 R W 7 0 P7IE 7 0 0x00 H0 R W 0x0020 027a PPORTP7CHATEN P7 Port Chattering Filter Enable Register 15 8 0x00 R 7 0 P7CHATEN 7 0 0x00 H0 R W 0x0020 027c PPORTP7MODSEL P7 Port Mode Select Register 15 8 0x00 R 7 0 P7SEL 7 0 0x00 H0 R W 0x...

Page 394: ...Interrupt Flag Register 15 8 0x00 R 7 0 P8IF 7 0 0x00 H0 R W Cleared by writing 1 0x0020 0288 PPORTP8INTCTL P8 Port Interrupt Control Register 15 8 P8EDGE 7 0 0x00 H0 R W 7 0 P8IE 7 0 0x00 H0 R W 0x0020 028a PPORTP8CHATEN P8 Port Chattering Filter Enable Register 15 8 0x00 R 7 0 P8CHATEN 7 0 0x00 H0 R W 0x0020 028c PPORTP8MODSEL P8 Port Mode Select Register 15 8 0x00 R 7 0 P8SEL 7 0 0x00 H0 R W 0x...

Page 395: ...6 PPORTP9INTF P9 Port Interrupt Flag Register 15 8 0x00 R 7 6 0 R 5 0 P9IF 5 0 0x00 H0 R W Cleared by writing 1 0x0020 0298 PPORTP9INTCTL P9 Port Interrupt Control Register 15 14 0 R 13 8 P9EDGE 5 0 0x00 H0 R W 7 6 0 R 5 0 P9IE 5 0 0x00 H0 R W 0x0020 029a PPORTP9CHATEN P9 Port Chattering Filter Enable Register 15 8 0x00 R 7 6 0 R 5 0 P9CHATEN 5 0 0x00 H0 R W 0x0020 029c PPORTP9MODSEL P9 Port Mode ...

Page 396: ...NTF PA Port Interrupt Flag Register 15 8 0x00 R 7 0 R 6 0 PAIF 6 0 0x00 H0 R W Cleared by writing 1 0x0020 02a8 PPORTPAINTCTL PA Port Interrupt Control Register 15 0 R 14 8 PAEDGE 6 0 0x00 H0 R W 7 0 R 6 0 PAIE 6 0 0x00 H0 R W 0x0020 02aa PPORTPACHATEN PA Port Chattering Filter Enable Register 15 8 0x00 R 7 0 R 6 0 PACHATEN 6 0 0x00 H0 R W 0x0020 02ac PPORTPAMODSEL PA Port Mode Select Register 15 ...

Page 397: ... 0 0x0 H0 R W 7 6 0x0 R 5 0 PDOEN 5 0 0x0 H0 R W 0x0020 02d4 PPORTPDRCTL Pd Port Pull up down Control Register 15 14 0x0 R 13 8 PDPDPU 5 0 0x0 H0 R W 7 6 0x0 R 5 0 PDREN 5 0 0x0 H0 R W 0x0020 02dc PPORTPDMODSEL Pd Port Mode Select Register 15 8 0x00 R 7 6 0x0 R 5 0 PDSEL 5 0 0x3 H0 R W 0x0020 02de PPORTPDFNCSEL Pd Port Function Select Register 15 12 0x00 R 11 10 PD5MUX 1 0 0x0 H0 R W 9 8 PD4MUX 1 ...

Page 398: ...rol Register 15 9 0x00 R 8 DBRUN 0 H0 R WP 7 4 CLKDIV 3 0 0x0 H0 R WP 3 2 KRSTCFG 1 0 0x0 H0 R WP 1 0 CLKSRC 1 0 0x0 H0 R WP 0x0020 02e2 PPORTINTFGRP P Port Interrupt Flag Group Register 15 11 0x00 R 10 PAINT 0 H0 R 9 P9INT 0 H0 R 8 P8INT 0 H0 R 7 P7INT 0 H0 R 6 P6INT 0 H0 R 5 P5INT 0 H0 R 4 P4INT 0 H0 R 3 P3INT 0 H0 R 2 P2INT 0 H0 R 1 P1INT 0 H0 R 0 P0INT 0 H0 R ...

Page 399: ...ing Register 15 13 P05PPFNC 2 0 0x0 H0 R W 12 11 P05PERICH 1 0 0x0 H0 R W 10 8 P05PERISEL 2 0 0x0 H0 R W 7 5 P04PPFNC 2 0 0x0 H0 R W 4 3 P04PERICH 1 0 0x0 H0 R W 2 0 P04PERISEL 2 0 0x0 H0 R W 0x0020 0306 UPMUXP0MUX3 P06 07 Universal Port Multiplexer Setting Register 15 13 P07PPFNC 2 0 0x0 H0 R W 12 11 P07PERICH 1 0 0x0 H0 R W 10 8 P07PERISEL 2 0 0x0 H0 R W 7 5 P06PPFNC 2 0 0x0 H0 R W 4 3 P06PERICH...

Page 400: ...2 0 0x0 H0 R W 12 11 P23PERICH 1 0 0x0 H0 R W 10 8 P23PERISEL 2 0 0x0 H0 R W 7 5 P22PPFNC 2 0 0x0 H0 R W 4 3 P22PERICH 1 0 0x0 H0 R W 2 0 P22PERISEL 2 0 0x0 H0 R W 0x0020 0314 UPMUXP2MUX2 P24 25 Universal Port Multiplexer Setting Register 15 13 P25PPFNC 2 0 0x0 H0 R W 12 11 P25PERICH 1 0 0x0 H0 R W 10 8 P25PERISEL 2 0 0x0 H0 R W 7 5 P24PPFNC 2 0 0x0 H0 R W 4 3 P24PERICH 1 0 0x0 H0 R W 2 0 P24PERIS...

Page 401: ...1 0 0x0 H0 R W 10 8 P35PERISEL 2 0 0x0 H0 R W 7 5 P34PPFNC 2 0 0x0 H0 R W 4 3 P34PERICH 1 0 0x0 H0 R W 2 0 P34PERISEL 2 0 0x0 H0 R W 0x0020 031e UPMUXP3MUX3 P36 37 Universal Port Multiplexer Setting Register 15 13 P37PPFNC 2 0 0x0 H0 R W 12 11 P37PERICH 1 0 0x0 H0 R W 10 8 P37PERISEL 2 0 0x0 H0 R W 7 5 P36PPFNC 2 0 0x0 H0 R W 4 3 P36PERICH 1 0 0x0 H0 R W 2 0 P36PERISEL 2 0 0x0 H0 R W ...

Page 402: ...Ch 0 Baud Rate Register 15 12 0x0 R 11 8 FMD 3 0 0x0 H0 R W 7 0 BRT 7 0 0x00 H0 R W 0x0020 0386 UART3_0CTL UART3 Ch 0 Control Register 15 8 0x00 R 7 2 0x00 R 1 SFTRST 0 H0 R W 0 MODEN 0 H0 R W 0x0020 0388 UART3_0TXD UART3 Ch 0 Trans mit Data Register 15 8 0x00 R 7 0 TXD 7 0 0x00 H0 R W 0x0020 038a UART3_0RXD UART3 Ch 0 Receive Data Register 15 8 0x00 R 7 0 RXD 7 0 0x00 H0 R 0x0020 038c UART3_0INTF...

Page 403: ... W 1 RB1FIE 0 H0 R W 0 TBEIE 0 H0 R W 0x0020 0390 UART3_0 TBEDMAEN UART3 Ch 0 Transmit Buffer Empty DMA Request Enable Register 15 8 0x00 R 7 4 0x0 R 3 0 TBEDMAEN 3 0 0x0 H0 R W 0x0020 0392 UART3_0 RB1FDMAEN UART3 Ch 0 Receive Buffer One Byte Full DMA Request Enable Register 15 8 0x00 R 7 4 0x0 R 3 0 RB1FDMAEN 3 0 0x0 H0 R W 0x0020 0394 UART3_0CAWF UART3 Ch 0 Carrier Waveform Register 15 8 0x00 R ...

Page 404: ...Ch 1 Mode Register 15 8 0x00 R 7 1 0x00 R 0 TRMD 0 H0 R W 0x0020 03a4 T16_1CTL T16 Ch 1 Control Register 15 9 0x00 R 8 PRUN 0 H0 R W 7 2 0x00 R 1 PRESET 0 H0 R W 0 MODEN 0 H0 R W 0x0020 03a6 T16_1TR T16 Ch 1 Reload Data Register 15 0 TR 15 0 0xffff H0 R W 0x0020 03a8 T16_1TC T16 Ch 1 Counter Data Register 15 0 TC 15 0 0xffff H0 R 0x0020 03aa T16_1INTF T16 Ch 1 Interrupt Flag Register 15 8 0x00 R 7...

Page 405: ...x0020 03b6 SPIA_0RXD SPIA Ch 0 Receive Data Register 15 0 RXD 15 0 0x0000 H0 R 0x0020 03b8 SPIA_0INTF SPIA Ch 0 Interrupt Flag Register 15 8 0x00 R 7 BSY 0 H0 R 6 4 0x0 R 3 OEIF 0 H0 S0 R W Cleared by writing 1 2 TENDIF 0 H0 S0 R W 1 RBFIF 0 H0 S0 R Cleared by reading the SPIA_0RXD register 0 TBEIF 1 H0 S0 R Cleared by writing to the SPIA_0TXD register 0x0020 03ba SPIA_0INTE SPIA Ch 0 Interrupt En...

Page 406: ... 0 0x000 H0 R W 0x0020 03ca I2C_0CTL I2C Ch 0 Control Register 15 8 0x00 R 7 6 0x0 R 5 MST 0 H0 R W 4 TXNACK 0 H0 S0 R W 3 TXSTOP 0 H0 S0 R W 2 TXSTART 0 H0 S0 R W 1 SFTRST 0 H0 R W 0 MODEN 0 H0 R W 0x0020 03cc I2C_0TXD I2C Ch 0 Transmit Data Register 15 8 0x00 R 7 0 TXD 7 0 0x00 H0 R W 0x0020 03ce I2C_0RXD I2C Ch 0 Receive Data Register 15 8 0x00 R 7 0 RXD 7 0 0x00 H0 R 0x0020 03d0 I2C_0INTF I2C ...

Page 407: ... NACKIE 0 H0 R W 4 STOPIE 0 H0 R W 3 STARTIE 0 H0 R W 2 ERRIE 0 H0 R W 1 RBFIE 0 H0 R W 0 TBEIE 0 H0 R W 0x0020 03d4 I2C_0TBEDMAEN I2C Ch 0 Transmit Buffer Empty DMA Request Enable Register 15 8 0x00 R 7 4 0x0 R 3 0 TBEDMAEN 3 0 0x0 H0 R W 0x0020 03d6 I2C_0RBFDMAEN I2C Ch 0 Receive Buffer Full DMA Request Enable Register 15 8 0x00 R 7 4 0x0 R 3 0 RBFDMAEN 3 0 0x0 H0 R W ...

Page 408: ...H0 R W 0 MODEN 0 H0 R W 0x0020 0404 T16B_0MC T16B Ch 0 Max Counter Data Register 15 0 MC 15 0 0xffff H0 R W 0x0020 0406 T16B_0TC T16B Ch 0 Timer Counter Data Register 15 0 TC 15 0 0x0000 H0 R 0x0020 0408 T16B_0CS T16B Ch 0 Counter Status Register 15 8 0x00 R 7 0 R 6 0 R 5 CAPI3 0 H0 R 4 CAPI2 0 H0 R 3 CAPI1 0 H0 R 2 CAPI0 0 H0 R 1 UP_DOWN 1 H0 R 0 BSY 0 H0 R 0x0020 040a T16B_0INTF T16B Ch 0 Interr...

Page 409: ...0 H0 R W 14 12 CBUFMD 2 0 0x0 H0 R W 11 10 CAPIS 1 0 0x0 H0 R W 9 8 CAPTRG 1 0 0x0 H0 R W 7 0 R 6 TOUTMT 0 H0 R W 5 TOUTO 0 H0 R W 4 2 TOUTMD 2 0 0x0 H0 R W 1 TOUTINV 0 H0 R W 0 CCMD 0 H0 R W 0x0020 0412 T16B_0CCR0 T16B Ch 0 Compare Capture 0 Data Register 15 0 CC 15 0 0x0000 H0 R W 0x0020 0414 T16B_0CC0DMAEN T16B Ch 0 Compare Capture 0 DMA Request Enable Register 15 8 0x00 R 7 4 0x0 R 3 0 CC0DMAE...

Page 410: ...6B Ch 0 Compare Capture 2 Data Register 15 0 CC 15 0 0x0000 H0 R W 0x0020 0424 T16B_0CC2DMAEN T16B Ch 0 Compare Capture 2 DMA Request Enable Register 15 8 0x00 R 7 4 0x0 R 3 0 CC2DMAEN 3 0 0x0 H0 R W 0x0020 0428 T16B_0CCCTL3 T16B Ch 0 Compare Capture 3 Control Register 15 SCS 0 H0 R W 14 12 CBUFMD 2 0 0x0 H0 R W 11 10 CAPIS 1 0 0x0 H0 R W 9 8 CAPTRG 1 0 0x0 H0 R W 7 0 R 6 TOUTMT 0 H0 R W 5 TOUTO 0...

Page 411: ...6B_1MC T16B Ch 1 Max Counter Data Register 15 0 MC 15 0 0xffff H0 R W 0x0020 0446 T16B_1TC T16B Ch 1 Timer Counter Data Register 15 0 TC 15 0 0x0000 H0 R 0x0020 0448 T16B_1CS T16B Ch 1 Counter Status Register 15 8 0x00 R 7 CAPI5 0 H0 R 6 CAPI4 0 H0 R 5 CAPI3 0 H0 R 4 CAPI2 0 H0 R 3 CAPI1 0 H0 R 2 CAPI0 0 H0 R 1 UP_DOWN 1 H0 R 0 BSY 0 H0 R 0x0020 044a T16B_1INTF T16B Ch 1 Interrupt Flag Register 15...

Page 412: ...SCS 0 H0 R W 14 12 CBUFMD 2 0 0x0 H0 R W 11 10 CAPIS 1 0 0x0 H0 R W 9 8 CAPTRG 1 0 0x0 H0 R W 7 0 R 6 TOUTMT 0 H0 R W 5 TOUTO 0 H0 R W 4 2 TOUTMD 2 0 0x0 H0 R W 1 TOUTINV 0 H0 R W 0 CCMD 0 H0 R W 0x0020 0452 T16B_1CCR0 T16B Ch 1 Compare Capture 0 Data Register 15 0 CC 15 0 0x0000 H0 R W 0x0020 0454 T16B_1CC0DMAEN T16B Ch 1 Compare Capture 0 DMA Request Enable Register 15 8 0x00 R 7 4 0x0 R 3 0 CC0...

Page 413: ... Data Register 15 0 CC 15 0 0x0000 H0 R W 0x0020 0464 T16B_1CC2DMAEN T16B Ch 1 Compare Capture 2 DMA Request Enable Register 15 8 0x00 R 7 4 0x0 R 3 0 CC2DMAEN 3 0 0x0 H0 R W 0x0020 0468 T16B_1CCCTL3 T16B Ch 1 Compare Capture 3 Control Register 15 SCS 0 H0 R W 14 12 CBUFMD 2 0 0x0 H0 R W 11 10 CAPIS 1 0 0x0 H0 R W 9 8 CAPTRG 1 0 0x0 H0 R W 7 0 R 6 TOUTMT 0 H0 R W 5 TOUTO 0 H0 R W 4 2 TOUTMD 2 0 0x...

Page 414: ...Ch 3 Mode Register 15 8 0x00 R 7 1 0x00 R 0 TRMD 0 H0 R W 0x0020 0484 T16_3CTL T16 Ch 3 Control Register 15 9 0x00 R 8 PRUN 0 H0 R W 7 2 0x00 R 1 PRESET 0 H0 R W 0 MODEN 0 H0 R W 0x0020 0486 T16_3TR T16 Ch 3 Reload Data Register 15 0 TR 15 0 0xffff H0 R W 0x0020 0488 T16_3TC T16 Ch 3 Counter Data Register 15 0 TC 15 0 0xffff H0 R 0x0020 048a T16_3INTF T16 Ch 3 Interrupt Flag Register 15 8 0x00 R 7...

Page 415: ...Ch 4 Mode Register 15 8 0x00 R 7 1 0x00 R 0 TRMD 0 H0 R W 0x0020 04a4 T16_4CTL T16 Ch 4 Control Register 15 9 0x00 R 8 PRUN 0 H0 R W 7 2 0x00 R 1 PRESET 0 H0 R W 0 MODEN 0 H0 R W 0x0020 04a6 T16_4TR T16 Ch 4 Reload Data Register 15 0 TR 15 0 0xffff H0 R W 0x0020 04a8 T16_4TC T16 Ch 4 Counter Data Register 15 0 TC 15 0 0xffff H0 R 0x0020 04aa T16_4INTF T16 Ch 4 Interrupt Flag Register 15 8 0x00 R 7...

Page 416: ...Ch 5 Mode Register 15 8 0x00 R 7 1 0x00 R 0 TRMD 0 H0 R W 0x0020 04c4 T16_5CTL T16 Ch 5 Control Register 15 9 0x00 R 8 PRUN 0 H0 R W 7 2 0x00 R 1 PRESET 0 H0 R W 0 MODEN 0 H0 R W 0x0020 04c6 T16_5TR T16 Ch 5 Reload Data Register 15 0 TR 15 0 0xffff H0 R W 0x0020 04c8 T16_5TC T16 Ch 5 Counter Data Register 15 0 TC 15 0 0xffff H0 R 0x0020 04ca T16_5INTF T16 Ch 5 Interrupt Flag Register 15 8 0x00 R 7...

Page 417: ...x0020 04d6 SPIA_2RXD SPIA Ch 2 Receive Data Register 15 0 RXD 15 0 0x0000 H0 R 0x0020 04d8 SPIA_2INTF SPIA Ch 2 Interrupt Flag Register 15 8 0x00 R 7 BSY 0 H0 R 6 4 0x0 R 3 OEIF 0 H0 S0 R W Cleared by writing 1 2 TENDIF 0 H0 S0 R W 1 RBFIF 0 H0 S0 R Cleared by reading the SPIA_2RXD register 0 TBEIF 1 H0 S0 R Cleared by writing to the SPIA_2TXD register 0x0020 04da SPIA_2INTE SPIA Ch 2 Interrupt En...

Page 418: ... R W 11 CAREN 0 H0 R W 10 BRDIV 0 H0 R W 9 INVRX 0 H0 R W 8 INVTX 0 H0 R W 7 0 R 6 PUEN 0 H0 R W 5 OUTMD 0 H0 R W 4 IRMD 0 H0 R W 3 CHLN 0 H0 R W 2 PREN 0 H0 R W 1 PRMD 0 H0 R W 0 STPB 0 H0 R W 0x0020 0604 UART3_1BR UART3 Ch 1 Baud Rate Register 15 12 0x0 R 11 8 FMD 3 0 0x0 H0 R W 7 0 BRT 7 0 0x00 H0 R W 0x0020 0606 UART3_1CTL UART3 Ch 1 Control Register 15 8 0x00 R 7 2 0x00 R 1 SFTRST 0 H0 R W 0 ...

Page 419: ...TBEIF 1 H0 S0 R Cleared by writing to the UART3_1TXD register 0x0020 060e UART3_1INTE UART3 Ch 1 Interrupt Enable Register 15 8 0x00 R 7 0 R 6 TENDIE 0 H0 R W 5 FEIE 0 H0 R W 4 PEIE 0 H0 R W 3 OEIE 0 H0 R W 2 RB2FIE 0 H0 R W 1 RB1FIE 0 H0 R W 0 TBEIE 0 H0 R W 0x0020 0610 UART3_1 TBEDMAEN UART3 Ch 1 Transmit Buffer Empty DMA Request Enable Register 15 8 0x00 R 7 4 0x0 R 3 0 TBEDMAEN 3 0 0x0 H0 R W ...

Page 420: ... R W 11 CAREN 0 H0 R W 10 BRDIV 0 H0 R W 9 INVRX 0 H0 R W 8 INVTX 0 H0 R W 7 0 R 6 PUEN 0 H0 R W 5 OUTMD 0 H0 R W 4 IRMD 0 H0 R W 3 CHLN 0 H0 R W 2 PREN 0 H0 R W 1 PRMD 0 H0 R W 0 STPB 0 H0 R W 0x0020 0624 UART3_2BR UART3 Ch 2 Baud Rate Register 15 12 0x0 R 11 8 FMD 3 0 0x0 H0 R W 7 0 BRT 7 0 0x00 H0 R W 0x0020 0626 UART3_2CTL UART3 Ch 2 Control Register 15 8 0x00 R 7 2 0x00 R 1 SFTRST 0 H0 R W 0 ...

Page 421: ...TBEIF 1 H0 S0 R Cleared by writing to the UART3_2TXD register 0x0020 062e UART3_2INTE UART3 Ch 2 Interrupt Enable Register 15 8 0x00 R 7 0 R 6 TENDIE 0 H0 R W 5 FEIE 0 H0 R W 4 PEIE 0 H0 R W 3 OEIE 0 H0 R W 2 RB2FIE 0 H0 R W 1 RB1FIE 0 H0 R W 0 TBEIE 0 H0 R W 0x0020 0630 UART3_2 TBEDMAEN UART3 Ch 2 Transmit Buffer Empty DMA Request Enable Register 15 8 0x00 R 7 4 0x0 R 3 0 TBEDMAEN 3 0 0x0 H0 R W ...

Page 422: ...Ch 6 Mode Register 15 8 0x00 R 7 1 0x00 R 0 TRMD 0 H0 R W 0x0020 0664 T16_6CTL T16 Ch 6 Control Register 15 9 0x00 R 8 PRUN 0 H0 R W 7 2 0x00 R 1 PRESET 0 H0 R W 0 MODEN 0 H0 R W 0x0020 0666 T16_6TR T16 Ch 6 Reload Data Register T16_6TC T16 Ch 6 Counter Data Register 15 0 TR 15 0 0xffff H0 R W 0x0020 0668 15 0 TC 15 0 0xffff H0 R 0x0020 066a T16_6INTF T16 Ch 6 Interrupt Flag Register 15 8 0x00 R 7...

Page 423: ...ata Register 15 0 TXD 15 0 0x0000 H0 R W 0x0020 0676 15 0 RXD 15 0 0x0000 H0 R 0x0020 0678 SPIA_1INTF SPIA Ch 1 Interrupt Flag Register 15 8 0x00 R 7 BSY 0 H0 R 6 4 0x0 R 3 OEIF 0 H0 S0 R W Cleared by writing 1 2 TENDIF 0 H0 S0 R W 1 RBFIF 0 H0 S0 R Cleared by reading the SPIA_1RXD register 0 TBEIF 1 H0 S0 R Cleared by writing to the SPIA_1TXD register 0x0020 067a SPIA_1INTE SPIA Ch 1 Interrupt En...

Page 424: ...Ch 2 Mode Register 15 8 0x00 R 7 1 0x00 R 0 TRMD 0 H0 R W 0x0020 0684 T16_2CTL T16 Ch 2 Control Register 15 9 0x00 R 8 PRUN 0 H0 R W 7 2 0x00 R 1 PRESET 0 H0 R W 0 MODEN 0 H0 R W 0x0020 0686 T16_2TR T16 Ch 2 Reload Data Register 15 0 TR 15 0 0xffff H0 R W 0x0020 0688 T16_2TC T16 Ch 2 Counter Data Register 15 0 TC 15 0 0xffff H0 R 0x0020 068a T16_2INTF T16 Ch 2 Interrupt Flag Register 15 8 0x00 R 7...

Page 425: ... H0 R W 0x0020 0694 QSPI_0TXD QSPI Ch 0 Transmit Data Register 15 0 TXD 15 0 0x0000 H0 R W 0x0020 0696 QSPI_0RXD QSPI Ch 0 Receive Data Register 15 0 RXD 15 0 0x0000 H0 R 0x0020 0698 QSPI_0INTF QSPI Ch 0 Interrupt Flag Register 15 8 0x00 R 7 BSY 0 H0 R 6 MMABSY 0 H0 R 5 4 0x0 R 3 OEIF 0 H0 S0 R W Cleared by writing 1 2 TENDIF 0 H0 S0 R W 1 RBFIF 0 H0 S0 R Cleared by reading the QSPI_0RXD register ...

Page 426: ...0 Memory Mapped Access Con figuration Register 1 15 8 0x00 R 7 4 0x0 R 3 0 TCSH 3 0 0x0 H0 R W 0x0020 06a4 QSPI_0RMADRH QSPI Ch 0 Remap ping Start Address High Register 15 4 RMADR 31 20 0x000 H0 R W 3 0 0x0 R 0x0020 06a6 QSPI_0MMACFG2 QSPI Ch 0 Memory Mapped Access Con figuration Register 2 15 12 DUMDL 3 0 0x0 H0 R W 11 8 DUMLN 3 0 0x0 H0 R W 7 6 DATTMOD 1 0 0x0 H0 R W 5 4 DUMTMOD 1 0 0x0 H0 R W 3...

Page 427: ... 0 0x000 H0 R W 0x0020 06ca I2C_1CTL I2C Ch 1 Control Register 15 8 0x00 R 7 6 0x0 R 5 MST 0 H0 R W 4 TXNACK 0 H0 S0 R W 3 TXSTOP 0 H0 S0 R W 2 TXSTART 0 H0 S0 R W 1 SFTRST 0 H0 R W 0 MODEN 0 H0 R W 0x0020 06cc I2C_1TXD I2C Ch 1 Transmit Data Register 15 8 0x00 R 7 0 TXD 7 0 0x00 H0 R W 0x0020 06ce I2C_1RXD I2C Ch 1 Receive Data Register 15 8 0x00 R 7 0 RXD 7 0 0x00 H0 R 0x0020 06d0 I2C_1INTF I2C ...

Page 428: ... NACKIE 0 H0 R W 4 STOPIE 0 H0 R W 3 STARTIE 0 H0 R W 2 ERRIE 0 H0 R W 1 RBFIE 0 H0 R W 0 TBEIE 0 H0 R W 0x0020 06d4 I2C_1TBEDMAEN I2C Ch 1 Transmit Buffer Empty DMA Request Enable Register 15 8 0x00 R 7 4 0x0 R 3 0 TBEDMAEN 3 0 0x0 H0 R W 0x0020 06d6 I2C_1RBFDMAEN I2C Ch 1 Receive Buffer Full DMA Request Enable Register 15 8 0x00 R 7 4 0x0 R 3 0 RBFDMAEN 3 0 0x0 H0 R W ...

Page 429: ... 0 0x000 H0 R W 0x0020 06ea I2C_2CTL I2C Ch 2 Control Register 15 8 0x00 R 7 6 0x0 R 5 MST 0 H0 R W 4 TXNACK 0 H0 S0 R W 3 TXSTOP 0 H0 S0 R W 2 TXSTART 0 H0 S0 R W 1 SFTRST 0 H0 R W 0 MODEN 0 H0 R W 0x0020 06ec I2C_2TXD I2C Ch 2 Transmit Data Register 15 8 0x00 R 7 0 TXD 7 0 0x00 H0 R W 0x0020 06ee I2C_2RXD I2C Ch 2 Receive Data Register 15 8 0x00 R 7 0 RXD 7 0 0x00 H0 R 0x0020 06f0 I2C_2INTF I2C ...

Page 430: ... NACKIE 0 H0 R W 4 STOPIE 0 H0 R W 3 STARTIE 0 H0 R W 2 ERRIE 0 H0 R W 1 RBFIE 0 H0 R W 0 TBEIE 0 H0 R W 0x0020 06f4 I2C_2TBEDMAEN I2C Ch 2 Transmit Buffer Empty DMA Request Enable Register 15 8 0x00 R 7 4 0x0 R 3 0 TBEDMAEN 3 0 0x0 H0 R W 0x0020 06f6 I2C_2RBFDMAEN I2C Ch 2 Receive Buffer Full DMA Request Enable Register 15 8 0x00 R 7 4 0x0 R 3 0 RBFDMAEN 3 0 0x0 H0 R W ...

Page 431: ...MC3APLEN REMC3 Data Bit Active Pulse Length Register 15 0 APLEN 15 0 0x0000 H0 R W Writing enabled when REMC3DBCTL MODEN bit 1 0x0020 0728 REMC3DBLEN REMC3 Data Bit Length Register 15 0 DBLEN 15 0 0x0000 H0 R W Writing enabled when REMC3DBCTL MODEN bit 1 0x0020 072a REMC3INTF REMC3 Status and Interrupt Flag Register 15 11 0x00 R 10 DBCNTRUN 0 H0 S0 R Cleared by writing 1 to the REMC3DBCTL REMCRST ...

Page 432: ...Ch 7 Mode Register 15 8 0x00 R 7 1 0x00 R 0 TRMD 0 H0 R W 0x0020 0784 T16_7CTL T16 Ch 7 Control Register 15 9 0x00 R 8 PRUN 0 H0 R W 7 2 0x00 R 1 PRESET 0 H0 R W 0 MODEN 0 H0 R W 0x0020 0786 T16_7TR T16 Ch 7 Reload Data Register 15 0 TR 15 0 0xffff H0 R W 0x0020 0788 T16_7TC T16 Ch 7 Counter Data Register 15 0 TC 15 0 0xffff H0 R 0x0020 078a T16_7INTF T16 Ch 7 Interrupt Flag Register 15 8 0x00 R 7...

Page 433: ...2A Ch 0 Con figuration Register 15 8 0x00 R 7 2 0x00 R 1 0 VRANGE 1 0 0x0 H0 R W 0x0020 07a8 ADC12A_0INTF ADC12A Ch 0 Interrupt Flag Register 15 9 0x00 R 8 OVIF 0 H0 R W Cleared by writing 1 7 AD7CIF 0 H0 R W 6 AD6CIF 0 H0 R W 5 AD5CIF 0 H0 R W 4 AD4CIF 0 H0 R W 3 AD3CIF 0 H0 R W 2 AD2CIF 0 H0 R W 1 AD1CIF 0 H0 R W 0 AD0CIF 0 H0 R W 0x0020 07aa ADC12A_0INTE ADC12A Ch 0 Interrupt Enable Register 15...

Page 434: ...4 ADC12A Ch 0 DMA Request Enable Register 4 15 8 0x00 R 7 4 0x0 R 3 0 ADCDMAEN 3 0 0x0 H0 R W 0x0020 07b6 ADC12A_0DMAEN5 ADC12A Ch 0 DMA Request Enable Register 5 15 8 0x00 R 7 4 0x0 R 3 0 ADCDMAEN 3 0 0x0 H0 R W 0x0020 07b8 ADC12A_0DMAEN6 ADC12A Ch 0 DMA Request Enable Register 6 15 8 0x00 R 7 4 0x0 R 3 0 ADCDMAEN 3 0 0x0 H0 R W 0x0020 07ba ADC12A_0DMAEN7 ADC12A Ch 0 DMA Request Enable Register 7...

Page 435: ... R W 0 SREF 0 H0 R W 0x0020 0846 RFC_0MCL RFC Ch 0 Measurement Counter Low Register 15 0 MC 15 0 0x0000 H0 R W 0x0020 0848 RFC_0MCH RFC Ch 0 Measurement Counter High Register 15 8 0x00 R 7 0 MC 23 16 0x00 H0 R W 0x0020 084a RFC_0TCL RFC Ch 0 Time Base Counter Low Register 15 0 TC 15 0 0x0000 H0 R W 0x0020 084c RFC_0TCH RFC Ch 0 Time Base Counter High Register 15 8 0x00 R 7 0 TC 23 16 0x00 H0 R W 0...

Page 436: ...IV 1 0 0x0 H0 R W 3 2 0x0 1 0 CLKSRC 1 0 0x0 H0 R W 0x0020 0862 SDACCTL 15 1 0x00 R 0 SDACEN 0x0 H0 R W 0x0020 0864 SDAC Mode Register 15 9 0x00 R 8 PWMOUTEN 0x0 H0 R W 7 1 0x0 R 0 MODE 0x0 H0 R W 0x0020 0866 SDAC Data Register 15 10 0x00 R 9 0 DAT 0x0 H0 R W 0x0020 0868 SDAC Interrupt Flag Register 15 2 0x00 R 1 ERRIF 0x0 H0 R W 0 DATREQIF 0x0 H0 R W 0x0020 086a SDAC Interrupt Enable Register 15 ...

Page 437: ...Remarks 0x0020 08a2 HW Processor Control Register 15 1 0x0000 R 0 HWPEN 0 H0 R W 0x0020 08a4 HW Processor Interrupt Flag Register 15 2 0x0000 R 1 HWP1IF ERRIF 0 H0 R W 0 HWP0IF STIF 0 H0 R W 0x0020 08a6 HW Processor Interrupt Enable Register 15 1 0x00 R 0 HWPIE 0x0 H0 R W 0x0020 08a8 HW Processor Command Trigger Register 15 1 0x00 R 0 HWP0TRG 0x0 H0 R W ...

Page 438: ...se Pointer Register 31 7 CPTR 31 7 0x000 H0 R W 0 6 0 CPTR 6 0 0x00 H0 R 0x0020 100c DMACACPTR DMAC Alternate Control Data Base Pointer Register 31 0 ACPTR 31 0 H0 R 0x0020 1014 DMACSWREQ DMAC Software Request Register 31 24 R 23 16 R 15 8 R 7 4 R 3 0 SWREQ 3 0 W 0x0020 1020 DMACRMSET DMAC Request Mask Set Register 31 24 0x00 R 23 16 0x00 R 15 8 0x00 R 7 4 0x0 R 3 0 RMSET 3 0 0x0 H0 R W 0x0020 102...

Page 439: ...23 16 0x00 R 15 8 0x00 R 7 1 0x00 R 0 ERRIF 0 H0 R W Cleared by writing 1 0x0020 2000 DMACENDIF DMAC Transfer Completion Interrupt Flag Register 31 24 0x00 R 23 16 0x00 R 15 8 0x00 R 7 4 0x0 R 3 0 ENDIF 3 0 0x0 H0 R W Cleared by writing 1 0x0020 2008 DMACENDIESET DMAC Transfer Completion Interrupt Enable Set Register 31 24 0x00 R 23 16 0x00 R 15 8 0x00 R 7 4 0x0 R 3 0 ENDIESET 3 0 0x0 H0 R W 0x002...

Page 440: ...y voltage VDDQSPI For P9 port groups for QSPI 3 0 3 6 V Flash programming voltage VPP 7 3 7 5 7 7 V OSC1 oscillator oscillation frequency fOSC1 Crystal oscillator 32 768 kHz OSC3 oscillator oscillation frequency fOSC3 Crystal ceramic oscillator 0 2 16 8 MHz EXOSC external clock frequency fEXOSC When supplied from an external oscillator 0 016 16 8 MHz Bypass capacitor between VSS and VDD CPW1 3 3 µ...

Page 441: ...SC3 16 MHz CR SYSCLK OSC3 850 1060 µA current consumption in RUN mode IRUN1 4 IOSC 8 MHz OSC1 32 768 kHz 1 OSC3 OFF SYSCLK IOSC 2 100 2 580 µA IRUN2 4 IOSC 2 MHz OSC1 32 768 kHz 1 OSC3 OFF SYSCLK IOSC 520 650 µA IRUN3 4 IOSC 2 MHz OSC1 32 768 kHz 1 OSC3 OFF SYSCLK IOSC PWGACTL REGSEL bit 0 mode1 310 390 µA IRUN4 4 IOSC OFF OSC1 32 768 kHz 1 OSC3 OFF SYSCLK OSC1 8 14 µA IOSC OFF OSC1 32 kHz 2 OSC3 ...

Page 442: ...FF OSC3 OFF Typ value IOSC OFF OSC1 OFF OSC3 OFF Typ value Current consumption temperature characteristic Current consumption temperature characteristic in HALT mode IOSC operation in HALT mode OSC1 operation IOSC ON OSC1 32 768 kHz OSC3 OFF Typ value IOSC OFF OSC1 32 768 kHz OSC3 OFF Typ value Current consumption temperature characteristic In HALT mode OSC3 operation OSC3 ON OSC1 32 768kHz IOSC O...

Page 443: ...OSC operation IOSC ON OSC1 32 768 kHz OSC3 OFF IOSC ON OSC1 32 768 kHz OSC3 OFF PWGACTL REGSEL bit 1 mode0 Typ Value PWGACTL REGSEL bit 0 mode1 Typ value Current consumption temperature characteristic Current consumption frequency characteristic in RUN mode OSC1 operation in RUN mode OSC3 operation IOSC OFF OSC1 32 768 kHz OSC3 OFF Typ value IOSC OFF OSC1 32 768 kHz OSC3 ON CR oscillator Typ Value...

Page 444: ...t POR BOR canceling voltage VRST 1 41 1 75 V POR BOR detection voltage VRST 1 25 1 55 V POR BOR hysteresis voltage DVRST 40 60 mV POR BOR detection response time tRST 20 µs POR BOR operating limit voltage VRSTOP 0 5 0 95 V POR BOR reset request hold time tRRQ 0 01 4 ms Note When performing a power on reset again after the power is turned off decrease the VDD voltage to VRSTOP or less Reset hold ci...

Page 445: ...DD 1 8 to 5 5 V VSS 0 V Ta 40 to 85 C Item Symbol Condition Min Typ Max Unit Oscillation start time tstaI 3 µs Oscillation frequency fIOSC CLGIOSC IOSCFQ 1 0 bits 0x2 PWGACTL REGSEL bit 1 7 2 8 8 4 MHz CLGIOSC IOSCFQ 1 0 bits 0x1 PWGACTL REGSEL bit 1 1 8 2 2 1 MHz CLGIOSC IOSCFQ 1 0 bits 0x0 PWGACTL REGSEL bit 1 0 9 1 1 05 MHz CLGIOSC IOSCFQ 1 0 bits 0x1 PWGACTL REGSEL bit 0 1 62 1 8 1 89 MHz CLGI...

Page 446: ... CLGOSC1 OSC1SELCR bit 0 CLGOSC1 CGI1 2 0 bits 0x6 23 pF CLGOSC1 OSC1SELCR bit 0 CLGOSC1 CGI1 2 0 bits 0x7 24 pF Crystal oscillator internal drain capacitance CDI1C CLGOSC1 OSC1SELCR bit 0 6 pF Crystal oscillator oscillator circuit current oscillation inverter drivability ratio 1 IOSC1C CLGOSC1 OSC1SELCR bit 0 CLGOSC1 INV1N INV1B 1 0 bits 0x0 70 CLGOSC1 OSC1SELCR bit 0 CLGOSC1 INV1N INV1B 1 0 bits...

Page 447: ...0 to 50 15 68 16 16 32 MHz CLGOSC3 OSC3FQ 1 0 bits 0x3 20 to 60 15 60 16 16 40 MHz CLGOSC3 OSC3FQ 1 0 bits 0x3 40 to 85 15 44 16 16 56 MHz CLGOSC3 OSC3FQ 1 0 bits 0x1 40 to 85 7 7 8 3 8 9 MHz CLGOSC3 OSC3FQ 1 0 bits 0x0 40 to 85 3 8 4 2 4 6 MHz CLGOSC3 OSC3FQ 1 0 bits 0x3 Right after auto trimming 15 84 16 16 16 MHz OSC3 oscillation frequency temperature characteristic EXOSC external clock input c...

Page 448: ...programmed 23 7 Input Output Port PPORT Characteristics Unless otherwise specified VDD 1 8 to 5 5 V VSS 0 V Ta 40 to 85 C Item Symbol Condition Min Typ Max Unit High level Schmitt input threshold voltage VT 0 5 VDD 0 8 VDD V Low level Schmitt input threshold voltage VT 0 2 VDD 0 5 VDD V Schmitt input hysteresis voltage DVT 180 mV High level output current IOH VOH 0 9 VDD 0 5 mA Low level output cu...

Page 449: ...D3CTL SVDC 4 0 bits 0x1b 982 1 063 1 145 kΩ SVD3CTL SVDC 4 0 bits 0x1c 1 001 1 086 1 171 kΩ SVD3CTL SVDC 4 0 bits 0x1d 1 022 1 110 1 198 kΩ SVD3CTL SVDC 4 0 bits 0x1e 1 054 1 129 1 204 kΩ SVD3CTL SVDC 4 0 bits 0x1f 1 072 1 154 1 237 kΩ EXSVDn detection voltage VSVD_EXT SVD3CTL SVDC 4 0 bits 0x00 1 17 1 2 1 23 V SVD3CTL SVDC 4 0 bits 0x01 1 27 1 3 1 33 V SVD3CTL SVDC 4 0 bits 0x02 1 46 1 5 1 54 V S...

Page 450: ... 0x16 3 90 4 0 4 10 V SVD3CTL SVDC 4 0 bits 0x17 4 00 4 1 4 20 V SVD3CTL SVDC 4 0 bits 0x18 4 10 4 2 4 31 V SVD3CTL SVDC 4 0 bits 0x19 4 19 4 3 4 41 V SVD3CTL SVDC 4 0 bits 0x1a 4 39 4 5 4 61 V SVD3CTL SVDC 4 0 bits 0x1b 4 49 4 6 4 72 V SVD3CTL SVDC 4 0 bits 0x1c 4 58 4 7 4 82 V SVD3CTL SVDC 4 0 bits 0x1d 4 68 4 8 4 92 V SVD3CTL SVDC 4 0 bits 0x1e 4 78 4 9 5 02 V SVD3CTL SVDC 4 0 bits 0x1f 4 88 5 ...

Page 451: ...tage characteristic Ta 25 C SVD3CTL SVDC 4 0 bits 0x04 CLK_SVD3 32 kHz Typ value 23 9 UART UART3 Characteristics Unless otherwise specified VDD 1 8 to 5 5 V VSS 0 V Ta 40 to 85 C Item Symbol Condition Min Typ Max Unit Transfer baud rate UBRT1 Normal mode 150 460 800 bps UBRT2 IrDA mode 150 115 200 bps ...

Page 452: ...l Condition VDD VD1 output Min Typ Max 単位 SPICLK0 cycle time tSCYC 1 8 to 5 5 V mode0 250 ns 1 8 to 3 6 V mode1 1000 ns SPICLK0 High pulse width tSCKH 1 8 to 5 5 V mode0 100 ns 1 8 to 3 6 V mode1 400 ns SPICLK0 Low pulse width tSCKL 1 8 to 5 5 V mode0 100 ns 1 8 to 3 6 V mode1 400 ns SDI0 setup time tSDS 1 8 to 5 5 V mode0 20 ns 1 8 to 3 6 V mode1 60 ns SDI0 hold time tSDH 1 8 to 5 5 V mode0 20 ns...

Page 453: ...Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL Rev 1 00 23 14 SPICLKn CPOL CPHA 0 1 SPICLKn CPOL CPHA 1 0 SDIn SDOn SPISSn tSSS tSSH tSDD tSDZ Hi Z ...

Page 454: ...C Item Symbol Condition VDD VD1 output Min Typ Max 単位 QSPICLKn cycle time tSCYC 3 0 to 5 5 V mode0 150 ns 1 8 to 3 0 V mode0 250 ns 1 8 to 3 6 V mode1 500 ns QSPICLKn High pulse width tSCKH 3 0 to 5 5 V mode0 60 ns 1 8 to 3 0 V mode0 100 ns 1 8 to 3 6 V mode1 200 ns QSPICLKn Low pulse width tSCKL 3 0 to 5 5 V mode0 60 ns 1 8 to 3 0 V mode0 100 ns 1 8 to 3 6 V mode1 200 ns QSDIOn 3 0 setup time tSD...

Page 455: ...ow pulse width tLOW 4 7 1 3 µs SCLn High pulse width tHIGH 4 0 0 6 µs Repeated START condition setup time tSU STA 4 7 0 6 µs Data hold time tHD DAT 0 0 µs Data setup time tSU DAT 250 100 ns SDAn SCLn rise time tr 1 000 300 ns SDAn SCLn fall time tf 300 300 ns STOP condition setup time tSU STO 4 0 0 6 µs Bus free time tBUF 4 7 1 3 µs SDIn SDOn tf tr tSU DAT tBUF tSU DAT tf S tHD STA 1 fSCL 1st cloc...

Page 456: ... VREFAn 3 5 LSB Analog input resistance RADIN 4 kW Analog input capacitance CADIN 30 pF A D converter circuit current IADC ADC12A_nCFG VRANGE 1 0 bits 0x3 VDD VREFA ADIN VREFA 2 fSMP 100 ksps Ta 25 C 3 6 V 400 700 µA ADC12A_nCFG VRANGE 1 0 bits 0x2 VDD VREFA ADIN VREFA 2 fSMP 100 ksps Ta 25 C 4 8 V 230 470 µA ADC12A_nCFG VRANGE 1 0 bits 0x1 VDD VREFA ADIN VREFA 2 fSMP 100 ksps Ta 25 C 5 5 V 210 39...

Page 457: ...e base counter clock frequency fTCCLK 4 2 MHz High level Schmitt input threshold voltage VT 0 5 VDD 0 8 VDD V Low level Schmitt input threshold voltage VT 0 2 VDD 0 5 VDD V Schmitt input hysteresis voltage DVT 120 mV R F converter operating current IRFC CREF 1 000 pF RREF RSEN 100 kW Ta 25 C VDD 3 6 V 200 350 µA 1 In this characteristic unevenness between production lots and variations in measurem...

Page 458: ...erence sensor oscillation current temperature characteristic consumption frequency characteristic RREF RSEN 100 kW CREF 1 000 pF Typ value CREF 1 000 pF Ta 25 C Typ value 18 16 VDD 3 6 V 14 1 8 V 12 10 8 6 4 2 1 800 1 600 1 400 1 200 1 000 800 600 400 200 VDD 3 6 V 1 8 V 0 50 25 0 25 50 75 100 Ta C 0 0 1 1 10 100 fRFCLK kHz 1 000 10 000 ...

Page 459: ...2 RDBG1 Debugging tool CVPP SWCLK SWD VPP VDD VD1 OSC1 OSC2 OSC3 OSC4 RESET TEST VSS EXSVDn SENB0 SENA0 REF0 RFIN0 External voltage CREF VDD AMP Speaker X tal1 X tal3 Ceramic CG1 CD1 CG3 CD3 CPW1 CPW2 1 8 5 5v 2 4 5 5v 1 or 2 7 5 5v 2 3 1 For Flash programming when VPP is supplied externally 2 For Flash programming when VPP is generated internally 3 When OSC1 crystal oscillator is selected 4 When ...

Page 460: ...or Ceramic capacitor CD3 OSC3 drain capacitor Ceramic capacitor CPW1 Bypass capacitor between VSS and VDD Ceramic capacitor or electrolytic capacitor CPW2 Capacitor between VSS and VD1 Ceramic capacitor RDBG1 2 Debug pin pull up resistor Thick film chip resistor CVREFA Capacitor between VSS and VREFA Ceramic capacitor CVPP Capacitor between VSS and VPP Ceramic capacitor CREF RFC reference capacito...

Page 461: ...25 1 Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL Rev 1 00 25 Package TQFP12 48PIN ...

Page 462: ...25 2 Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL Rev 1 00 QFP13 64PIN ...

Page 463: ...25 3 Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL Rev 1 00 TQFP14 80PIN ...

Page 464: ...25 4 Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL Rev 1 00 QFP15 100PIN ...

Page 465: ...g status configuration shown in Table A 1 1 is different from one that is listed in Electrical Characteristics check the settings shown below PWGACTL REGMODE 1 0 bits of the power generator If the PWGACTL REGMODE 1 0 bits of the power generator are 0x2 normal mode when the CPU enters SLEEP mode current consumption in SLEEP mode will be larger than ISLP that is listed in Electrical Characteristics ...

Page 466: ...aluation using the actual printed circuit board OSC3 crystal ceramic oscillator circuit configurations The OSC3 crystal ceramic oscillator circuit provides some configuration items to support various crystal and ceramic resonators These configurations trade off current consumption for performance as shown below The lower oscillation inverter gain setting CLGOSC3 OSC3INV 1 0 bits decreases current ...

Page 467: ...nal lines alongside such components or wiring even if more than 3 mm distance or located on other layers Avoid crossing wires 3 Use VSS to shield the OSC1 OSC3 and OSC2 OSC4 pins and related wiring including wiring for adjacent circuit board layers Layers wired should be adequately shielded as shown to the right Fully ground adjacent layers where possible At minimum shield the area at least 5 mm a...

Page 468: ...e shortest thickest patterns possible 2 If a bypass capacitor is connected between VDD and VSS connections between the VDD and VSS pins should be as short as possible Signal line location To prevent electromagnetically induced noise arising from mutual induction large current signal lines should not be positioned close to pins susceptible to noise such as oscillator and analog measurement pins Loc...

Page 469: ...itial status 2 OSC1 OSC2 OSC3 OSC4 and EXOSC pins If the OSC1 oscillator circuit OSC3 oscillator circuit or EXOSC input circuit is not used the OSC1 and OSC2 pins the OSC3 and OSC4 pins or the EXOSC pin should be left open The control registers should be fixed at the initial status disabled 3 Memory display controller pins If the memory display controller is not used the memory display controller ...

Page 470: ...mmended patterns on the circuit board see Mounting Precautions in Appendix Noise Measures for Interrupt Input Pins This product is able to generate a port input interrupt when the input signal changes The interrupt is generated when an input signal edge is detected therefore an interrupt may occur if the signal changes due to extraneous noise To prevent occurrence of unexpected interrupts due to e...

Page 471: ...26 1 Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL Rev 1 00 Revision History Code No Page Contents 413699400 All New establishment ...

Page 472: ...II 562 Dong An Road Xu Hui District Shanghai China Phone 86 21 5330 4888 FAX 86 21 5423 4677 Shenzhen Branch Room 804 805 8 Floor Tower 2 Ali Center No 3331 Keyuan South RD Shenzhen bay Nanshan District Shenzhen 518054 China Phone 86 10 3299 0588 FAX 86 10 3299 0560 Epson Taiwan Technology Trading Ltd 15F No 100 Songren Rd Sinyi Dist Taipei City 110 Taiwan Phone 886 2 8786 6688 Epson Singapore Pte...

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