Epson S1C31D50, Technical Instructions

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4-5
Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
4.8. Control Registers
System Protect Register
Register name Bit Bit name Initial Reset R/W Remarks
SYSPROT 15 – 0 PROT[15:0] 0x0000 H0 R/W –
Bits 15 – 0 PROT[15:0]
These bits protect the control registers related to the system against writings.
0x0096 (R/W): Disable system protection
Other than 0x0096 (R/W): Enable system protection
While the system protection is enabled, any data will not be written to the affected
control bits
(bits with “WP” or “R/WP” appearing in the R/W column).
CACHE Control Register
Register name Bit Bit name Initial Reset R/W Remarks
CACHECTL 15 – 8 – 0x00 – R –
7 – 2 – 0x00 – R
1 reserved 1 – R
0 CACHEEN 0 H0 R/W
Bits 15 – 1 Reserved
Bit 0 CACHEEN
This bit enables the instruction cache function.
1 (R/W): Enable instruction cache
0 (R/W): Disable instruction cache
FLASHC Flash Read Cycle Register
Register name Bit Bit name Initial Reset R/W Remarks
FLASHCWAIT 15 – 9 – 0x00 – R –
8 (reserved) 0 H0 R/WP
7 – 2 – 0x00 – R
1 – 0 RDWAIT[1:0] 0x1 H0 R/WP
Bits 15 – 2 Reserved
Bits 1 – 0 RDWAIT[1:0]
These bits set the number of bus access cycles for reading from the Flash memory.
Table 4.8.1 Setting Number of Bus Access Cycles for Flash Read
FLASHCWAIT.
RDWAIT[1:0] bits
Number of bus
access cycles
System clock frequency
PWGACTL.
REGSEL bit = 0
PWGACTL.
REGSEL bit = 1
0x3 4
2.1 MHz (max.)
16.6 MHz (max.) 0x2 3
0x1 2
0x0 1 1.05 MHz (max.) 8.4 MHz (max.)
Note:
Be sure to set the FLASHCWAIT.RDWAIT[1:0] bits before the system clock is configured.