Epson S1C31D50, Technical Instructions

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19-12
Seiko Epson Corporation
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
ADC12A Ch. n Interrupt Enable Register
Register name Bit Bit name Initial Reset R/W Remarks
ADC12A_ n INTE 15 – 9 – 0x00 – R –
8 OVIE 0 H0 R/W
7 AD7IE 0 H0 R/W
6 AD6IE 0 H0 R/W
5 AD5IE 0 H0 R/W
4 AD4IE 0 H0 R/W
3 AD3IE 0 H0 R/W
2 AD2IE 0 H0 R/W
1 AD1IE 0 H0 R/W
0 AD0IE 0 H0 R/W
Bits 15 – 9 Reserved
Bit 8 OVIE
Bits 7 – 0 AD m IE
These bits enable ADC12A interrupts.
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
The following shows the correspondence between the bit and interrupt:
ADC12A_nINTE.OVIE bit:
A/D conversion result overwrite error interrupt
ADC12A_nINTE.ADmCIE bit: Analog input signal m A/D conversion completion interrupt
ADC12A Ch. n DMA Request Enable Register m
Register name Bit Bit name Initial Reset R/W Remarks
ADC12A_ n DMAEN m 15 – 0 ADCDMAEN[15:0] 0x0000 H0 R/W –
Bits 15 – 0 ADCDMAEN[15:0]
These bits enable ADC12A to issue a DMA transfer request to the corresponding DMA
controller channel (Ch.0
– Ch.15) when the A/D conversion for each analog input has
completed.
1 (R/W): Enable DMA transfer request
0 (R/W): Disable DMA transfer request
Each bit corresponds to a DMA controller channel. The high-order bits for the
unimplemented channels are ineffective.
ADC12A Ch. n Result Register
Register name Bit Bit name Initial Reset R/W Remarks
ADC12A_ n ADD 15 – 0 ADD[15:0] 0x0000 H0 R –
Bits 15 – 0 ADD[15:0]
The A/D conversion results are set to these bits.