Epson S1C31D50, Technical Instructions

Page: 275 / 472

17-10
Seiko Epson Corporation
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
The time from counter = 0x0000 or MAX value to occurrence of a compare interrupt (compare
period) and the time to occurrence of a counter MAX or counter zero interrupt (count cycle) can be
calculated as follows:
During counting up
Compare period =
(𝐶𝐶 + 1)
𝑓
𝐶𝐿𝐾_T16B
[s] Count cycle =
(𝑀𝐴𝑋 + 1)
𝑓
𝐶𝐿𝐾_T16B
[s] (𝐸𝑞. 17.1)
During counting down
Compare period =
(𝐶𝐶 + 1)
𝑓
𝐶𝐿𝐾_T16B
[s] Count cycle =
(𝑀𝐴𝑋 + 1)
𝑓
𝐶𝐿𝐾_T16B
[s] (𝐸𝑞. 17.2)
Where
CC: T16B_ n CCRm register setting value (0 to 65,535)
MAX: T16B_ n MC register setting value (0 to 65,535)
f
CLK_T16B
: Count clock frequency [Hz]
The comparator MATCH signal and counter MAX/ZERO signals are also used to generate a timer
output wave- form (T
OUT). Refer to “ T OUT Output Control” for more information.
Compare buffer
The comparator loads the comparison value, which has been written to the T16B_ n CCR m register,
to the compare buffer before comparing it with the counter value. For example, when generating a
PWM wave- form, the waveform with the desired duty ratio may not be generated if the
comparison value is altered asynchronous to the count operation. To avoid this problem, the timing
to load the comparison value to the compare buffer can be configured using the
T16B_
n CCCTL m .CBUFMD[2:0] bits for synchronization with the count operation.
(1)
Repeat up count mode
1.1)
T16B_ n CCCTL m .CBUFMD[2:0] bits = 0x0
Data (W) → CC[15:0] Data (W) → CC[15:0]
CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1
CNTMAXIF = 1 CNTMAXIF = 1 CNTMAXIF = 1
RUN = 1
MODEN = 1 PRESET = 1
Data (W) → MC[15:0]
Software operation
Hardware operation
0xffff
0x0000
Count cycle
Counter
MAX value
(T16B_nMC register)
Time
Compare period
Data (W) → CC[15:0]
Compare buffer
value