Epson S1C31D50, Technical Instructions

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Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
DMAC Error Interrupt Flag Register
Register name Bit Bit name Initial Reset R/W Remarks
DMACERRIF 31 – 24 – 0x00 – R –
23 – 16 – 0x00 – R
15 – 8 – 0x00 – R
7 – 1 – 0x00 – R
0 ERRIF 0 H0 R/W Cleared by writing 1.
Bits 31 – 1 Reserved
Bit 0 ERRIF
This bit indicates the DMAC error interrupt cause occurrence status.
1 (R): Cause of interrupt occurred
0 (R): No cause of interrupt occurred
1 (W): Clear flag
0 (W): Ineffective
DMAC Transfer Completion Interrupt Flag Register
Register name Bit Bit name Initial Reset R/W Remarks
DMACENDIF 31 – 0 ENDIF[31:0] 0x0000
0000
H0 R/W Cleared by writing 1.
Bits 31 – 0 ENDIF[31:0]
These bits indicate the DMA transfer completion interrupt cause occurrence status of
each DMAC channel.
1 (R): Cause of interrupt occurred
0 (R): No cause of interrupt occurred
1 (W): Clear flag
0 (W): Ineffective
Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented
channels are ineffective.
DMAC Transfer Completion Interrupt Enable Set Register
Register name Bit Bit name Initial Reset R/W Remarks
DMACENDIESET 31 – 0 ENDIESET[31:0] 0x0000
0000
H0 R/W –
Bits 31 – 0 ENDIESET[31:0]
These bits enable DMA transfer completion interrupts to be generated from each DMAC
channel.
1 (W): Enable interrupt
0 (W): Ineffective
1 (R): Interrupt has been enabled.
0 (R): Interrupt has been disabled.
Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented
channels are ineffective.