11-10
Seiko Epson Corporation
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
SVD3 Status and Interrupt Flag Register
Register name
Bit
Bit name
Initial
Reset
R/W
Remarks
SVD3INTF
15
–
9
–
0x00
–
R
–
8
SVDDT
x
–
R
7
–
1
–
0x00
–
R
0
SVDIF
0
H1
R/W
Cleared by writing 1.
Bits 15
–
9
Reserved
Bit 8
SVDDT
The power supply voltage detection results can be read out from this bit.
1 (R): Power supply voltage (VDD, EXSVDn) < SVD detection voltage VSVD
or EXSVD detection voltage VSVD_EXT
0 (R):
Power supply voltage (VDD, EXSVDn) ≥ SVD detection vol
tage VSVD
or EXSVD detection voltage VSVD_EXT
Bits 7
–
1
Reserved
Bit 0
SVDIF
This bit indicates the low power supply voltage detection interrupt cause occurrence status.
1 (R): Cause of interrupt occurred
0 (R): No cause of interrupt occurred
1 (W): Clear flag
0 (W): Ineffective
Note:
The SVD3 internal circuit is initialized if the interrupt flag is cleared while SVD3 is in
operation after 1 is written to the SVD3CTL.MODEN bit.
SVD3 Interrupt Enable Register
Register name
Bit
Bit name
Initial
Reset
R/W
Remarks
SVD3INTE
15
–
8
–
0x00
–
R
–
7
–
1
–
0x00
–
R
0
SVDIE
0
H0
R/W
Bits 15
–
1 Reserved
Bit 0
SVDIE
This bit enables low power supply voltage detection interrupts.
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
Notes:
•
If the SVD3CTL.SVDRE[3:0] bits are set to 0xa, no low power supply voltage detection
interrupt will occur, as a reset is issued at the same timing as an interrupt.
•
To prevent generating unnecessary interrupts, the corresponding interrupt flag should be
cleared before enabling interrupts.
Summary of Contents for S1C31D50
Page 461: ...25 1 Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL Rev 1 00 25 Package TQFP12 48PIN ...
Page 462: ...25 2 Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL Rev 1 00 QFP13 64PIN ...
Page 463: ...25 3 Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL Rev 1 00 TQFP14 80PIN ...
Page 464: ...25 4 Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL Rev 1 00 QFP15 100PIN ...