Epson S1C31D50, Technical Instructions

Page: 328 / 472

20-3
Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Figure 21.2.2.3 External Clock Input in External Clock Input Mode
20.3. Clock Settings
20.3.1. RFC Operating Clock
When using the RFC, the RFC operating clock TCCLK must be supplied to the RFC from the clock
generator. The TCCLK supply should be controlled as in the procedure shown below.
1.
Enable the clock source in the clock generator if it is stopped (refer to “Clock Generator” in the
“P
ower Supply , Reset, and Clocks” chapter).
2. Set the following RFC_ n CLK register bits:
-
RFC_ n CLK.CLKSRC[1:0] bits (Clock source selection)
-
RFC_ n CLK.CLKDIV[1:0] bits (Clock division ratio selection = Clock frequency setting)
The time base counter performs counting with TCCLK set here. Selecting a higher clock results in
higher conversion accuracy, note, however, that the frequency should be determined so that the time
base counter will not over- flow during reference oscillation.
20.3.2. Clock Supply in SLEEP Mode
When using RFC during SLEEP mode, the RFC operating clock TCCLK must be configured so that it will
keep supplying by writing 0 to the CLGOSC.
xxxx SLPC bit for the TCCLK clock source.
20.3.3. Clock Supply in DEBUG Mode
The TCCLK supply during DEBUG mode should be controlled using the RFC_ n CLK.DBRUN bit.
The TCCLK supply to the RFC is suspended when the CPU enters DEBUG mode if the RFC_ n CLK.DBRUN
bit= 0. After the CPU returns to normal mode, the TCCLK supply resumes. Although the RFC stops
operating when the TCCLK supply is suspended, the output pin and registers retain the status before
DEBUG mode was entered. If the RFC_
n CLK.DBRUN bit = 1, the TCCLK supply is not suspended and the
RFC will keep operating in DEBUG mode.
SENB n
SENA n
REF n
RFIN n
S1C31 RFC
Square wave
Sine wave
* Leave the unused pins open.