Epson S1C31D50, Technical Instructions

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6-15
Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
DMAC Request Mask Set Register
Register name Bit Bit name Initial Reset R/W Remarks
DMACRMSET 31 – 0 RMSET[31:0] 0x0000
0000
H0 R/W –
Bits 31 – 0 RMSET[31:0]
These bits mask DMA transfer requests from peripheral circuits.
1 (W): Mask DMA transfer requests from peripheral circuits
0 (W): Ineffective
1 (R): DMA transfer requests from peripheral circuits have been disabled.
0 (R): DMA transfer requests from peripheral circuits have been enabled.
Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented
channels are ineffective.
DMAC Request Mask Clear Register
Register name Bit Bit name Initial Reset R/W Remarks
DMACRMCLR 31 – 0 RMCLR[31:0] – – W –
Bits 31 – 0 RMCLR[31:0]
These bits cancel the mask state of DMA transfer requests from peripheral circuits
1 (W): Cancel mask state of DMA transfer requests from peripheral circuits
(The DMACRMSET register is cleared to 0.)
0 (W): Ineffective
Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented
channels are ineffective.
DMAC Enable Set Register
Register name Bit Bit name Initial Reset R/W Remarks
DMACENSET 31 – 0 ENSET[31:0] 0x0000
0000
H0 R/W –
Bits 31 – 0 ENSET[31:0]
These bits enable each DMAC channel.
1 (W): Enable DMAC channel
0 (W): Ineffective
1 (R): Enabled
0 (R): Disabled
These bits are cleared after the DMA transfer has completed.
Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented
channels are ineffective.
DMAC Enable Clear Register
Register name Bit Bit name Initial Reset R/W Remarks
DMACENCLR 31 – 0 ENCLR[31:0] – – W –
Bits 31 – 0 ENCLR[31:0]
These bits disable each DMAC channel.
1 (W): Disable DMAC channel (The DMACENSET register is cleared to 0.)
0 (W): Ineffective
Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented
channels are ineffective.