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17-32
Seiko Epson Corporation
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Bits 9
–
8
CAPTRG[1:0]
These bits select the trigger edge(s) of the trigger signal at which the counter value is
captured in the T16B_
n
CCR
m
register in capture mode (see Table 17.7.4). The
T16B_
n
CCCTL
m
.CAPTRG[1:0] bits are control bits for capture mode and are ineffective in
comparator mode.
Table 17.7.4 Trigger Signal/Edge for Capturing Counter Value
T16B_
n
CCCTL
m
.
CAPTRG[1:0] bits
(Trigger edge)
Trigger condition
T16B_
n
CCCTL
m
.CAPIS[1:0] bits (Trigger signal)
0x0 (External trigger signal)
0x2 (Software trigger
signal = L)
0x3 (Software trigger
signal = H)
0x3 (
↑
&
↓
)
Rising or falling edge of the CAP
nm
pin input signal
Altering the T16B_
n
CCCTL
m
.CAPIS[1:0] bits from 0x2
to 0x3, or from 0x3 to 0x2
0x2 (
↓
)
Falling edge of the CAP
nm
pin input
signal
Altering the T16B_
n
CCCTL
m
.CAPIS[1:0] bits from 0x3
to 0x2
0x1 (
↑
)
Rising edge of the CAP
nm
pin input
signal
Altering the T16B_
n
CCCTL
m
.CAPIS[1:0] bits from 0x2
to 0x3
0x0
Not triggered (disable capture function)
Bit 7
Reserved
Bit 6
TOUTMT
This bit selects whether the comparator MATCH signal of another system is used for
generating the TOUT
nm
signal or not.
1 (R/W): Generate TOUT using two comparator MATCH signals of the comparator
circuit pair (0 and 1, 2 and 3, 4 and 5)
0 (R/W): Generate TOUT using one comparator MATCH signal of comparator
m
and the counter MAX or ZERO signals
The T16B_
n
CCCTL
m
.TOUTMT bit is control bit for comparator mode and is ineffective in
capture mode.
Bit 5
TOUTO
This bit sets the TOUT
nm
signal output level when software control mode
(T16B_
n
CCCTL
m
.TOUT- MD[2:0] = 0x0) is selected for the TOUT
nm
output.
1 (R/W): High level output
0 (R/W): Low level output
The T16B_
n
CCCTL
m
.TOUTO bit is control bit for comparator mode and is ineffective in
capture mode.
Bits 4
–
2
TOUTMD[2:0]
These bits configure how the TOUT
nm
signal waveform is changed by the comparator
MATCH and counter MAX/ZERO signals.
The T16B_
n
CCCTL
m
.TOUTMD[2:0] bits are control bits for comparator mode and are
ineffective in capture mode.
Summary of Contents for S1C31D50
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