Epson S1C31D50, Technical Instructions

Page: 233 / 472

15-39
Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
QSPI Ch.n FIFO Data Ready DMA Request Enable Register
Register name Bit Bit name Initial Reset R/W Remarks
QSPI_ n FRLDMAEN 15 – 8 FRLDMAEN[15:0] 0x0000 H0 R/W –
Bits 15 – 0 FRLDMAEN[15:0]
These bits enable the QSPI to issue a DMA transfer request to the corresponding DMA
channel (Ch.0
– Ch.15) when data is prefetched into the FIFO (FIFO data ready).
1 (R/W): Enable DMA transfer request
0 (R/W): Disable DMA transfer request
Each bit corresponds to a DMA controller channel. The high-order bits for the
unimplemented channels are ineffective.
QSPI Ch. n Memory Mapped Access Configuration Register 1
Register name Bit Bit name Initial Reset R/W Remarks
QSPI_ n MMACFG1 15 – 8 – 0x00 – R –
7 – 4 – 0x0 – R
3 – 0 TCSH[3:0] 0x0 H0 R/W
Bits 15 – 4 Reserved
Bits 3 – 0 TCSH[3:0]
When non-sequential reading from a Flash memory address, which is not continuous to
the previous read address, occurs in memory mapped access mode, the #QSPISS
n signal is
reasserted after negated once. Then the new address is sent to the Flash memory before
reading data.
The QSPI_
n MMACFG1.TCSH[3:0] bits specify the period to negate the #QSPISS n signal at
this time in a number of clocks.
Table 15.8.4 #QSPISS n Inactive Period between Non-Sequential Readings
QSPI_ n MMACFG1.TCSH[3:0] bits #QSPISS n Inactive Period
0xf 16 clocks
0xe 15 clocks
0xd 14 clocks
0xc 13 clocks
0xb 12 clocks
0xa 11 clocks
0x9 10 clocks
0x8 9 clocks
0x7 8 clocks
0x6 7 clocks
0x5 6 clocks
0x4 5 clocks
0x3 4 clocks
0x2 3 clocks
0x1 2 clocks
0x0 1 clock
Note:
These bits specify a number of system clocks.