Epson S1C31D50, Technical Instructions

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20-10
Seiko Epson Corporation
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
RFC Ch. n Control Register
Register name Bit Bit name Initial Reset R/W Remarks
RFC_ n CTL 15 – 9 – 0x00 – R –
8 RFCLKMD 0 H0 R/W
7 CONEN 0 H0 R/W
6 EVTEN 0 H0 R/W
5 – 4 SMODE[1:0] 0x0 H0 R/W
3 – 1 – 0x0 – R
0 MODEN 0 H0 R/W
Bits 15 – 9 Reserved
Bit 8 RFCLKMD
This bit sets the RFCLKO n pin to output the divided-by-two oscillation clock.
1 (R/W): Divided-by-two clock output
0 (R/W): Oscillation clock output
F or more information, refer to “CR Oscillation Frequen cy Monitoring Function. ”
Bit 7 CONEN
This bit disables the automatic CR oscillation stop function to enable continuous oscillation
function.
1 (R/W): Enable continuous oscillation
0 (R/W): Disable continuous oscillation
F or more information, refer to “CR Oscillation Frequen cy Monitoring Function. ”
Bit 6 EVTEN
This bit enables external clock input mode (event counter mode).
1 (R/W): External clock input mode
0 (R/W): Normal mode
F or more information, refer to “Operating Modes . ”
Note:
Do not input an external clock before the RFC_ n CTL.EVTEN bit is set to 1. The RFIN n pin is
pulled down to V
SS
level when the port function is switched for the R/F converter.
Bits 5 – 4 Reserved
Bits 3 – 1 Reserved
Bit 0 MODEN
This bit enables the RFC operations.
1 (R/W): Enable RFC operations (The operating clock is supplied.)
0 (R/W): Disable RFC operations (The operating clock is stopped.)
Note:
If the RFC_ n CTL.MODEN bit is altered from 1 to 0 during R/F conversion, the counter value
being converted cannot be guaranteed. R/F conversion cannot be resumed.