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13-13
Seiko Epson Corporation
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
13.9.
Control Registers
UART3 Ch.
n
Clock Control Register
Register name
Bit
Bit name
Initial
Reset
R/W
Remarks
UART3_
n
CLK
15
–
9
–
0x00
–
R
–
8
DBRUN
0
H0
R/W
7
–
6
–
0x0
–
R
5
–
4
CLKDIV[1:0]
0x0
H0
R/W
3
–
2
–
0x0
–
R
1
–
0
CLKSRC[1:0]
0x0
H0
R/W
Bits 15
–
9
Reserved
Bit 8
DBRUN
This bit sets whether the UART3 operating clock is supplied in DEBUG mode or not.
1 (R/W): Clock supplied in DEBUG mode
0 (R/W): No clock supplied in DEBUG mode
Bits 7
–
6
Reserved
Bits 5
–
4
CLKDIV[1:0]
These bits select the division ratio of the UART3 operating clock.
Bits 3
–
2
Reserved
Bits 1
–
0
CLKSRC[1:0]
These bits select the clock source of the UART3.
Table 13.9.1 Clock Source and Division Ratio Settings
UART3_
n
CLK.
CLKDIV[1:0] bits
UART3_
n
CLK.CLKSRC[1:0] bits
0x0
0x1
0x2
0x3
IOSC
OSC1
OSC3
EXOSC
0x3
1/8
1/1
1/8
1/1
0x2
1/4
1/4
0x1
1/2
1/2
0x0
1/1
1/1
(Note) The oscillation circuits/external input that are not supported in this IC cannot be
selected as the clock source.
Note:
The UART3_
n
CLK register settings can be altered only when the UART3_
n
CTL.MODEN bit = 0.
Summary of Contents for S1C31D50
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