![background image](http://html.mh-extra.com/html/epson/s1c31d50/s1c31d50_technical-instructions_107789293.webp)
17-28
Seiko Epson Corporation
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
T16B Ch.
n
Timer Counter Data Register
Register name
Bit
Bit name
Initial
Reset
R/W
Remarks
T16B_
n
TC
15
–
0
TC[15:0]
0x0000
H0
R
–
Bits 15
–
0
TC[15:0]
The current counter value can be read out through these bits.
T16B Ch.
n
Counter Status Register
Register name
Bit
Bit name
Initial
Reset
R/W
Remarks
T16B_
n
CS
15
–
8
–
0x00
–
R
–
7
CAPI5
0
H0
R
6
CAPI4
0
H0
R
5
CAPI3
0
H0
R
4
CAPI2
0
H0
R
3
CAPI1
0
H0
R
2
CAPI0
0
H0
R
1
UP_DOWN
1
H0
R
0
BSY
0
H0
R
Bits 15
–
8
Reserved
Bit 7
CAPI5
Bit 6
CAPI4
Bit 5
CAPI3
Bit 4
CAPI2
Bit 3
CAPI1
Bit 2
CAPI0
These bits indicate the signal level currently input to the CAP
nm
pin.
1 (R): Input signal = High level
0 (R): Input signal = Low level
The following shows the correspondence between the bit and the CAP
nm
pin:
T16B_
n
CS.CAPI5 bit: CAP
n
5 pin
T16B_
n
CS.CAPI4 bit: CAP
n
4 pin
T16B_
n
CS.CAPI3 bit: CAP
n
3 pin
T16B_
n
CS.CAPI2 bit: CAP
n
2 pin
T16B_
n
CS.CAPI1 bit: CAP
n
1 pin
T16B_
n
CS.CAPI0 bit: CAP
n
0 pin
Note:
The configuration of the T16B_
n
CS.CAPI
m
bits depends on the model. The bits corre-
sponding to the CAP
nm
pins that do not exist are read-only bits and are always fixed at 0.
Bit 1
UP_DOWN
This bit indicates the currently set count direction.
1 (R): Count up
0 (R): Count down
Bit 0
BSY
This bit indicates the counter operating status.
1 (R): Running
0 (R): Idle
Summary of Contents for S1C31D50
Page 461: ...25 1 Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL Rev 1 00 25 Package TQFP12 48PIN ...
Page 462: ...25 2 Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL Rev 1 00 QFP13 64PIN ...
Page 463: ...25 3 Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL Rev 1 00 TQFP14 80PIN ...
Page 464: ...25 4 Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL Rev 1 00 QFP15 100PIN ...