Agilent Technologies 4284A, Operation Manual

Page: 221 / 460

T able 7-4. Status Byte Assignments
Bit No. Bit W eigh t Description
7 128 Op eration Status Ev en t Register Summary Bit
This bit is set to \1" when one or more enabled bits of the op eration
status ev en t register (discussed later in this c hapter) has b een set to
\1". This bit is cleared when all bits of the op eration status register
are set to 0. (This bit isn't cleared b y serial-p olling.)
6 64 Bit 6 serv es t w o functions RQS/MSS dep ending on ho w it is read.
RQS (Request Service) Bit
If bit 6 is read in the serial p olling pro cess, it is treated as the RQS
bit and is reset during the serial p olling pro cess.
MSS (Master Summary) Bit
If bit 6 is read using the *STB? (status b yte) query , it is treated as the
MSS bit, and its v alue is not c hanged b y the executing the *STB?
query .
T o understand this op eration think of the RQS and MSS bits as t w o
inputs to a multiplexer (mux ) and the output of the MUX b eing bit 6
of the status b yte register.
During the serial p olling op eration the MUX path selected is from the
service request generation circuit to bit 6, so bit 6 represen ts the RQS
bit.
During execution of the *STB? query the MUX path selected is from
the master summary bit generation circuit to bit 6, so bit 6 represen ts
the MSS bit.
T o clear the MSS bit, all bits of the original registers corresp onding to
the enabled summary bit in the status b yte and the output buer of
the 4284A must b e cleared. When y ou read the status b yte including
the MSS bit instead of the RQS bit, the *STB? query must b e used.
*STB? query clears neither the MSS bit nor the RQS bit.
5 32 Standard Ev en t Status Register Summary Bit
This bit is set to \1" when an y enabled bits of the standard ev en t
status register (discussed later in this section) has b een set to \1".
This bit is cleared when all bits of the standard ev en t status register
are set to 0. (This bit isn't cleared b y serial-p olling.)
4 16 MA V (Message Av ailable) Bit
This bit is set to \1" whenev er the 4284A has data a v ailable to
output. This bit is cleared when the a v ailable data is read.
(This bit isn't cleared b y serial-p olling.)
3 8 alwa ys 0 (zero)
2 4 alwa ys 0 (zero)
1 2 alwa ys 0 (zero)
0 1 alwa ys 0 (zero)
Remote Control 7-21