78
Function Description
WAGO-I/O-SYSTEM 750
750-806 Fieldbus Controller DeviceNet
TM
Manual
Version 2.0.0
Output process image:
Standard process data, output image (Assembly Class, Instance 1)
Table 33: Output Process Image
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte 0
Low byte channel 1
Byte 1
High byte channel 1
Byte 2
Low byte channel 2
Byte 3
High byte channel 2
Byte 4
unused
DO04
1)
DO03
1)
DO02
1)
DO01
1)
1)
DO = Digital output
7.3.3.2
Absolute Addressing
The internal CPU of the fieldbus controller has direct access to the data via
absolute addresses. The addressing starts with address 0 for both inputs and
outputs. The respective addresses for bits, bytes and double words (DWord) are
derived from the word addresses.
The structure of the process image is described in section "Functional
Description" > … > "Standard Design".
Addressing occurs according to the following structure:
Input data
%IW0
…
word-oriented data
%IW
n
%I
n+1
…
bit-oriented data
%I
n+m
Output data
%QW0
…
word-oriented data
%QW
n
%Q
n+1
…
bit-oriented data
%Q
n+m
