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Clock Input Mode
・
If double buffers are disabled. (SCxMOD2<WBUF> = "0")
When receiving data, double buffer is always enabled regardless of the SCxMOD2
<WBUF> settings.
A data written in the transmit buffer is outputted from the TXDx pin and a data is shif-
ted into the receive buffer when the clock input becomes active. The INTTXx is generated
upon completion of data transmission. The INTRXx is generated when the data is moved
from shift register to receive buffer after completion of data reception.
Note that transmit data must be written into the transmit buffer before the clock input
for the next data (data must be written before the point A in Figure 12-20). Data must be
read before completing reception of the next data.
・
If double buffers are enabled. (SCxMOD2<WBUF> = "1")
The INTTXx is generated at the timing the transmit buffer data is moved to the transmit
shift register after completing data transmission from the transmit shift register. At the
same time, data received is shifted to the shift register, it is moved to the receive buffer,
and the INTRXx is generated.
Note that transmit data must be written into the transmit buffer before the clock input
for the next data (data must be written before the point A in Figure 12-20). Data must be
read before completing reception of the next data.
Upon the clock input for the next data, transmission from transmit shift register (in
which data has been moved from transmit buffer) is started while receive data is shifted in-
to receive shift register simultaneously.
If data in receive buffer has not been read when the last bit of the data is received, an over-
run error occurs.
If there is no data written to transmit buffer when clock for the next data is input, an under-
run error occurs. The level which is specified by SCxCR<TXDEMP> is output to TXDx
pin.
TMPM3V6/M3V4
12. Serial Channel with 4bytes FIFO (SIO/UART)
12.14 Operation in Each Mode
Page 264
2019-02-06
Summary of Contents for TMPM3V4
Page 1: ...32 Bit RISC Microcontroller TX03 Series TMPM3V6 M3V4 ...
Page 2: ... 2019 Toshiba Electronic Devices Storage Corporation ...
Page 7: ...Revision History Date Revision Comment 2019 02 06 1 First Release ...
Page 8: ......
Page 22: ...xiv ...
Page 52: ...TMPM3V6 M3V4 3 Processor Core 3 6 Exclusive access Page 30 2019 02 06 ...
Page 148: ...TMPM3V6 M3V4 7 Exceptions 7 6 Exception Interrupt Related Registers Page 126 2019 02 06 ...
Page 178: ...TMPM3V6 M3V4 9 Input Output port 9 2 Block Diagrams of Ports Page 156 2019 02 06 ...
Page 354: ...TMPM3V6 M3V4 14 Synchronous Serial Port SSP 14 6 Frame Format Page 332 2019 02 06 ...
Page 419: ...TMPM3V6 M3V4 Page 397 2019 02 06 ...
Page 462: ...TMPM3V6 M3V4 21 Watchdog Timer WDT 21 5 Control register Page 440 2019 02 06 ...
Page 544: ......