Toshiba TMPM3V4, Manual

Page: 266 / 544

12.9.3.4 Read Received Data
In spite of enabling or disabling FIFO, read the received data from the receive buffer (SCxBUF).
When receive FIFO is disabled, the buffer full flag SCxMOD2<RBFLL> is cleared to "0" by this read-
ing. The next data can be received in the receive shift register before reading a data from the receive buf-
fer. The parity bit to be added in the 8-bit UART mode as well as the most significant bit in the 9-bit
UART mode will be stored in SCxCR<RB8>.
When the receive FIFO is enabled, the 9-bit UART mode is prohibited because up to 8-bit data can be stor-
ed in receive FIFO. In the 8-bit UART mode, the parity bit is lost but parity error is determined and the re-
sult is stored in SCxCR<PERR>.
12.9.3.5 Wake-up Function
In the 9-bit UART mode, the slave controller can be operated in the wake-up mode by setting the wake-
up function SCxMOD0 <WU> to "1". In this case, the interrupt INTRXx will be generated only when
SCxCR <RB8> is set to "1".
12.9.3.6 Overrun Error
When receive FIFO is disabled, the overrun error occurs without completing reading data before receiv-
ing the next data. When an overrun error occurs, a content of receive buffer and SCxCR<RB8> is not
lost, but a content of receive shift register is lost.
When receive FIFO is enabled, overrun error is occurred and set overrun flag by no reading receive
FIFO before moving the next data into received buffer when receive FIFO is full. In this case, the con-
tents of receive FIFO are not lost.
In the I/O interface mode with clock output mode, the clock output automatically stops, so this flag
has no meaning.
Note: When the mode is changed from I/O interface mode with clock output mode to the other modes,
read SCxCR and clear overrun flag.
TMPM3V6/M3V4
12. Serial Channel with 4bytes FIFO (SIO/UART)
12.9 Receive
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2019-02-06