Toshiba TMPM3V4, Manual

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11.4 Operation Description
11.4.1 Transmit FIFO and Receive FIFO
11.4.1.1 Transmit FIFO
The transmit FIFO is an 8-bit width and 32-deep memory buffer. The CPU data written via APB inter-
face is stacked to this FIFO until the data is read by the transmit. When the transmit FIFO is disabled, it
can be served as a 1-byte hold register.
11.4.1.2 Receive FIFO
The receive FIFO is a 12-bit width and 32-deep memory buffer. Error bits corresponding to receive da-
ta are stacked into the receive FIFO using receive logic until the data is read by the CPU via APB inter-
face. When the receive FIFO is disabled, it can serve as a 1-byte hold register.
Bit 11 10 9 8 7 6 5 4 3 2 1 0
Receive FIFO
Overrun
Error
Break
Error
Parity
Error
Framing
Error
Receive data
Receive data 8 bits
Overrun
Error
Break
Error
Parity
Error
Framing
Error
Receive data
Receive data 7 bits
Overrun
Error
Break
Error
Parity
Error
Framing
Error
Receive data
Receive data 6 bits
Overrun
Error
Break
Error
Parity
Error
Framing
Error
Receive data
Receive data 5 bits
Overrun
Error
Break
Error
Parity
Error
Framing
Error
Receive data
Note: Empty bits in the receive data are undefined.
11.4.2 Transmit Data and Receive data
Data written in UARTDR is stacked into the transmit FIFO when the FIFO is enabled.
If the FIFO is disabled, the data is transferred to the transmit hold register.
Transfer is started by writing data. The data includes a start bit. If a parity bit is enabled, the data is transfer-
red with a parity and stop bit.
Received data is a 12-bit width including 4-bit status bits (break error, framing error, parity error, and over-
run error) and is stacked into the receive FIFO. If the FIFO is disabled, received data and the status are trans-
ferred to the receive hold register.
TMPM3V6/M3V4
Page 203
2019-02-06