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11.3.3  UARTxRSR (Receive Status Register)

Both UARTxRSR and UARTxECR registers are mapped on the same address.

31

30

29

28

27

26

25

24

Bit symbol

-

-

-

-

-

-

-

-

After reset

0

0

0

0

0

0

0

0

23

22

21

20

19

18

17

16

Bit symbol

-

-

-

-

-

-

-

-

After reset

0

0

0

0

0

0

0

0

15

14

13

12

11

10

9

8

Bit symbol

-

-

-

-

-

-

-

-

After reset

0

0

0

0

0

0

0

0

7

6

5

4

3

2

1

0

Bit symbol

-

-

-

-

OE

BE

PE

FE

After reset

0

0

0

0

0

0

0

0

Bit

Bit symbol

Type

Function

31-4

−

R

Read as "0".

3

OE

R

Overrun error
0: No error
1: Error
When data is received, if FIFO has already been full, this bit is set to "1".
This bit is cleared to "0" by writing data to UARTxECR.
If FIFO is full, further data cannot be written. Thus, the content of FIFO is valid and only the content of

shift register is overwritten. CPU must be read data in order to empty FIFO.

2

BE

R

Break error
0: No error
1: Error
If break condition (UTxRXD input is held "Low" for longer than a full-word transmission time defined as

start, data, parity, and stop bits) is detected, this bit is set to "1".
This bit is cleared to "0" by writing data to UARTxECR.
If FIFO is enabled, this error is input to the top of the FIFO. If a break error occurs, "0" is input to FIFO as

data.
In the next data reception, UTxRXD input is set to "1" (marking status), this bit is enabled after a start bit

is received.

1

PE

R

Parity error
0: No error
1: Error
When this bit is "1", this indicates that the parity of received data does not match the parity set in

UARTxLCR_H<EPS> and <SPS>.
This bit is cleared to "0" by writing data to UARTxECR.
If the FIFO is enabled, this error is input to the top of the FIFO.

0

FE

R

Framing error
0: No error
1: Error
When this bit is set to "1", this indicates that a valid stop bit is not included in the received data. (A valid

stop bit length is "1".)
This bit is cleared to "0" by writing data to UARTxECR.
If the FIFO is enabled, this error is input to the top of FIFO.

Note 1: An overrun error is immediately set when the error occurs.
Note 2: UARTxRSR is updated when data is read from UARTxDR. Therefore, received data must be read from

UARTxDR before error status is read from UARTxRSR. This read sequence cannot be reversed. In addition, er-

ror status can be read by reading UARTxDR.

TMPM3V6/M3V4

Page 189

2019-02-06

Summary of Contents for TMPM3V4

Page 1: ...32 Bit RISC Microcontroller TX03 Series TMPM3V6 M3V4 ...

Page 2: ... 2019 Toshiba Electronic Devices Storage Corporation ...

Page 3: ...TMPM3V6 M3V4 Arm Cortex and Thumb are registered trademarks of Arm Limited or its subsidiaries in the US and or elsewhere All rights reserved ...

Page 4: ...n a reset is performed by the internal power on reset pins of the MCUs that use the internal power on reset are undefined until power supply voltage reaches the voltage at which power on reset is val id 2 Unused pins Unused input output ports of the MCUs are prohibited to use The pins are high impedance Generally if MCUs operate while the high impedance pins left open electrostatic damage or latch...

Page 5: ...s All registers have a 32 bit unique address and the addresses of the registers are defined as follows with some exceptions Base address Unique address Base Address 0x0000_0000 Register name Address Base Control register SAMCR 0x0004 0x000C Note SAMCR register address is 32 bits wide from the address 0x0000_0004 Base Address 0x00000000 unique address 0x0004 Note The register shown above is an exam...

Page 6: ...le mode 2 011 Sample mode 3 The settings other than those above Reserved 6 0 TDATA 6 0 W Transmitted data Note The Type is divided into three as shown below R W READ WRITE R READ W WRITE c Data description Meanings of symbols used in the SFR description are as shown below x channel numbers ports n m bit numbers d Register description Registers are described as shown below Register name Bit Symbol ...

Page 7: ...Revision History Date Revision Comment 2019 02 06 1 First Release ...

Page 8: ......

Page 9: ...es and function list 1 4 2 2 PORT Debug pin 1 4 2 3 Control pin 1 4 2 4 Power Supply pin 2 Product Information 2 1 Built in Functions of the M3V6 and M3V4 20 2 2 Information of Each Peripheral Function 21 2 2 1 Exception 21 2 2 1 1 Differences of the Interrupt Factors 2 2 2 16 bit Timer Event Counters TMRB 22 2 2 3 Serial Channel SIO UART 24 2 2 4 Universal Asynchronous Serial Communication Circui...

Page 10: ...6 2 2 CGSYSCR System control register 47 6 2 3 CGOSCCR Oscillation control register 48 6 2 4 CGSTBYCR Standby control register 50 6 2 5 CGPLLSEL PLL Selection Register 51 6 2 6 CGCKSEL System clock selection register 52 6 3 Clock control 53 6 3 1 Clock Type 53 6 3 2 Initial Values after Reset 53 6 3 3 Clock system Diagram 54 6 3 4 Warm up function 55 6 3 5 Clock Multiplication Circuit PLL 57 6 3 5...

Page 11: ...5 1 3 Transmission 7 5 1 4 Precautions when using external interrupt pins 7 5 1 5 List of Interrupt Sources 7 5 1 6 Active level 7 5 2 Interrupt Handling 89 7 5 2 1 Flowchart 7 5 2 2 Preparation 7 5 2 3 Detection by Clock Generator 7 5 2 4 Detection by CPU 7 5 2 5 CPU processing 7 5 2 6 Interrupt Service Routine ISR 7 6 Exception Interrupt Related Registers 95 7 6 1 Register List 95 7 6 2 NVIC Reg...

Page 12: ...5 10 16 bit Timer Event Counters TMRB 10 1 Outline 157 10 2 Differences in the Specifications 158 10 3 Configuration 159 10 4 Registers 160 10 4 1 Register list according to channel 160 10 4 2 TBxEN Enable register 161 10 4 3 TBxRUN RUN register 162 10 4 4 TBxCR Control register 163 10 4 5 TBxMOD Mode register 164 10 4 6 TBxFFCR Flip flop control register 165 10 4 7 TBxST Status register 166 10 4 ...

Page 13: ...194 11 3 9 UARTxCR UART Control Register 196 11 3 10 UARTxIFLS UART Interrupt FIFO Level Selection Register 197 11 3 11 UARTxIMSC UART Interrupt Disable Enable Register 198 11 3 12 UARTxRIS UART Raw Interrupt Status Register 199 11 3 13 UARTxMIS UART Masked Interrupt Status Register 200 11 3 14 UARTxICR UART Interrupt Clear Register 201 11 3 15 UARTxHCCR 50 Duty Control Register 202 11 4 Operation...

Page 14: ...12 9 Receive 241 12 9 1 Receive Counter 241 12 9 2 Receive Control Unit 241 12 9 2 1 I O interface mode 12 9 2 2 UART Mode 12 9 3 Receive Operation 241 12 9 3 1 Receive Buffer 12 9 3 2 Receive FIFO Operation 12 9 3 3 I O interface mode with clock output mode 12 9 3 4 Read Received Data 12 9 3 5 Wake up Function 12 9 3 6 Overrun Error 12 10 Transmit 245 12 10 1 Transmit Counter 245 12 10 2 Transmit...

Page 15: ...281 13 5 5 Operating mode 281 13 5 6 Configuring the SBI as a Transmitter or a Receiver 282 13 5 7 Configuring the SBI as a Master or a Slave 282 13 5 8 Generating Start and Stop Conditions 282 13 5 9 Interrupt Service Request and Release 283 13 5 10 Arbitration Lost Detection Monitor 283 13 5 11 Slave Address Match Detection Monitor 285 13 5 12 General call Detection Monitor 285 13 5 13 Last Rece...

Page 16: ...lock ratios 325 14 6 Frame Format 326 14 6 1 SSI frame format 327 14 6 2 SPI frame format 328 14 6 3 Microwire frame format 330 15 Remote Control Signal Preprocessor RMC 15 1 Basic operation 333 15 1 1 Reception of Remote Control Signal 333 15 2 Block Diagram 333 15 3 Registers 334 15 3 1 Register List 334 15 3 2 RMCxEN Enable Register 335 15 3 3 RMCxREN Receive Enable Register 336 15 3 4 RMCxRBUF...

Page 17: ...DREG7 Conversion Result Register 7 374 16 4 18 ADREG8 Conversion Result Register 8 375 16 4 19 ADREG9 Conversion Result Register 9 376 16 4 20 ADREG10 Conversion Result Register 10 377 16 4 21 ADREG11 Conversion Result Register 11 378 16 4 22 ADTSET03 ADTSET47 ADTSET811 Timer Trigger Program Registers 379 16 4 23 ADSSET03 ADSSET47 ADSSET811 Software Trigger Program Registers 383 16 4 24 ADASET03 A...

Page 18: ...ration Description 419 19 3 1 Control 419 19 3 2 Function 419 19 3 2 1 Enabling disabling the voltage detection operation 19 3 2 2 Selecting the detection voltage level 20 Oscillation Frequency Detector OFD 20 1 Block diagram 421 20 2 Registers 422 20 2 1 Register List 422 20 2 1 1 OFDCR1 Control register 1 20 2 1 2 OFDCR2 Control register 2 20 2 1 3 OFDMN Lower detection frequency setting registe...

Page 19: ...otect mask register 22 2 Detail of Flash Memory 453 22 2 1 Function 453 22 2 2 Operation Mode of Flash Memory 453 22 2 3 Hardware Reset 453 22 2 4 How to Execute Command 454 22 2 5 Command Description 454 22 2 5 1 Automatic Page Program 22 2 5 2 Automatic Chip Erase 22 2 5 3 Automatic Block Erase 22 2 5 4 Automatic Protect Bit Program 22 2 5 5 Auto Protect Bit Erase 22 2 5 6 ID Read 22 2 5 7 Read ...

Page 20: ...rnal Host 484 22 4 2 1 Step 1 22 4 2 2 Step 2 22 4 2 3 Step 3 22 4 2 4 Step 4 22 4 2 5 Step 5 22 4 2 6 Step 6 23 Debug Interface 23 1 Specification Overview 489 23 2 SWJ DP 489 23 3 ETM 489 23 4 Pin Functions 490 23 5 Peripheral Functions in Halt Mode 491 23 6 Connection with a Debug Tool 492 23 6 1 About connection with debug tool 492 23 6 2 Important points of using debug interface pins used as ...

Page 21: ...07 25 6 4 1 AC Measurement Condition 25 6 4 2 SSP SPI mode Master 25 6 4 3 SSP SPI mode Slave 25 6 5 Event Counter 511 25 6 6 Capture 511 25 6 7 External Interrupt 511 25 6 8 SCOUT pin AC Characteristics 512 25 6 9 Debug Communication 513 25 6 9 1 SWD Interface 25 6 9 2 JTAG Interface 25 6 10 ETM Trace 514 25 6 11 On chip Oscillator Characteristic 514 25 6 12 Flash Characteristic 514 25 7 Recommen...

Page 22: ...xiv ...

Page 23: ...roved program flow New 32 bit Thumb instructions for improved performance New Thumb mixed 16 32 bit instruction set can produce faster more efficient code b Both high performance and low power consumption have been achieved High performance A 32 bit multiplication 32 32 32 bits can be executed with one clock A division takes within 2 to 12 cycles Low power consumption Optimized design using a low ...

Page 24: ...t output ports PORT Input Output pin TMPM3V6FWFG TMPM3V61FWDFG 83 pin TMPM3V4FWUG TMPM3V4FWEFG 47 pin TMPM3V4FSUG TMPM3V4FSEFG 47 pin Output pin TMPM3V6FWFG TMPM3V6FWDFG 1 pin TMPM3V4FWUG TMPM3V4FWEFG 1 pin TMPM3V4FSUG TMPM3V4FSEFG 1 pin 7 16 bit timer TMRB 8 channels 16 bit interval timer mode 16 bit event counter mode 16 bit PPG output External trigger 16 bit programmable square wave output mode...

Page 25: ...otocol that includes SPI 3 types SPI SSI Microwire 16byte FIFO equipped 8 bit width 8 depth 14 12 bit AD converter ADC 1 unit TMPM3V6FWFG TMPM3V6FWDFG 18 channel TMPM3V4FWUG TMPM3V4FWEFG 10 channel TMPM3V4FSUG TMPM3V4FSEFG 10 channel Fixed channel Channel scan mode Single repeat mode External trigger start and internal timer trigger start are possible Repeat conversion is capable AD monitoring Min...

Page 26: ...g erasing and debugging 0 C to 70 C during Flash writing erasing and debugging 12 2 24 Package TMPM3V6FWFG LQFP100 14mm x 14mm 0 5mm pitch TMPM3V6FWDFG QFP100 14mm x 20mm 0 65mm pitch TMPM3V4FWUG LQFP64 10mm x 10mm 0 5mm pitch TMPM3V4FWEFG QFP64 14mm x 14mm 0 65mm pitch TMPM3V4FSUG LQFP64 10mm x 10mm 0 5mm pitch TMPM3V4FSEFG QFP64 14mm x 14mm 0 65mm pitch TMPM3V6 M3V4 1 1 Features Page 4 2019 02 0...

Page 27: ...tex M3 NVIC Debug FLASH RAM BOOT ROM 4KB TMRB VLTD WDT EHOSC IHOSC CG PORT IO Bus X1 X2 ELOSC XT1 XT2 APB POR ADC UART RTC OFD AHB to IO Bridge AHB to APB Bridge SIO UART SSP RMC I2C SIO Figure 1 1 Block Diagram TMPM3V6 M3V4 Page 5 2019 02 06 ...

Page 28: ... PG2 PG3 1 LQFP100 14x14mm 0 5mm pitch Figure 1 2 Pin Layout LQFP100 14x14mm TOP VIEW 1 3 2 TMPM3V6FWDFG PG7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PE0 PE1 PE2 PE3 DVDD5 PE4 PE5 DVSS PE6 PE7 PN0 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 Pl1 Pl0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 VOUT3 RESET RVDD5 MODE VOUT15 DVSS PN7 PN6 PN5 PN4 PN3 PN2 PN1 5 10 15 20 25 30 80 75 70 65 60 55 51 100 95 90 85 81 Top View PF4 PF3 PF2 PF1 PF...

Page 29: ...M1 DVSS DVSS LQFP64 10x10mm 0 5mm pitch Figure 1 4 Pin Layout LQFP64 10x10mm TOP VIEW 1 3 4 TMPM3V4FWEFG TMPM3V4FSEFG Top View 1 10 5 15 45 35 40 33 17 25 20 30 60 55 50 49 64 PA7 PA6 PA1 PE 0 PE5 PE4 PE3 PE2 PE1 PA0 PA5 PA4 PA3 PA2 DVSS PH0 PI1 PH1 PH2 PH3 PH4 PH5 PH6 PH7 VOUT3 RESET RVDD5 MODE VOUT15 DVSS PI0 PB1 PB2 PB5 PF0 PB 0 AVDD5 DVSS DVDD5 PL0 PL2 PF1 PB3 PB4 PB6 PB7 AVSS DVDD5 DVSS PC0 P...

Page 30: ...ke input pin UART UTxTXD Output Data output pin UTxTXD50A Output Data output pin UTxTXD50B Output Data output pin UTxRXD Input Data input pin UTxRXD50 Input Data input pin I2C SIO SDAx I O Data input output pin I2C bus mode SOx Output Data output pin Clock synchronous 8 bit SIO mode SCLx I O Clock input output pin I2C bus mode SIx Input Data input pin Clock synchronous 8 bit SIO mode SCKx I O Cloc...

Page 31: ...utput pin 1 1 4 1 3 Control function Table 1 3 Pin name and functions Pin name Input or Output Function X1 Input High frequency resonator connection pin X2 Output High frequency resonator connection pin XT1 Input Low frequency resonator connection pin XT2 Output Low frequency resonator connection pin MODE Input MODE pin This pin must be fixed to Low level RESET Input Reset signal input pin BOOT In...

Page 32: ...μF for the regulator RVDD5 Power supply pin for the regulator DVDD5 Power supply pin for the digital circuit DVDD5 supplies the following pins PA PB PC PD PE PF PG PL PM PN PP MODE RESET BOOT DVSS GND pin for the digital circuit AVDD5 Power supply pin for the analog circuit AVDD5 supplies the following pins PH PI PJ AVSS GND pin for ADC TMPM3V6 M3V4 1 4 Pin names and Functions Page 10 2019 02 06 ...

Page 33: ...tal power supply line in the close vicinity of this capacitor If the unseparated line is long due to common impedance coupling electrical power fluctuation is conducted to analog power supply from dig ital power supply This causes the noise of the analog circuit Note 3 When wiring power supply and GND lines they must be placed close If not a power supply and GND line make a power supply loop throu...

Page 34: ...num ber in this cell is corresponded with the number of function register 3 Pin specification The mean of the symbol in the table is shown below SMT CMOS Type of input gate SMT Schmitt input CMOS CMOS input OD Programmable open drain output support Yes supported N A Not supported PU PD Programmable Pull Up Pull Down PU Programmable Pull Up supported PD Programmable Pull Down supported Pin No LQFP1...

Page 35: ... 35 20 PA3 TB1OUT RXIN0 PU PD Yes SMT 34 36 21 PA4 SCLK1 CTS1 PU PD Yes SMT 35 37 22 PA5 TXD1 TB6OUT PU PD Yes SMT 36 38 23 PA6 RXD1 TB6IN PU PD Yes SMT 37 39 24 PA7 TB4IN INT8 PU PD Yes SMT PORT B 86 88 55 PB0 TRACECLK PU PD Yes SMT 87 89 56 PB1 TRACEDATA0 PU PD Yes SMT 88 90 57 PB2 TRACEDATA1 PU PD Yes SMT 89 91 58 PB3 TMS SWDIO PU PD Yes SMT 90 92 59 PB4 TCK SWCLK PU PD Yes SMT 91 93 60 PB5 TDO...

Page 36: ...A PU PD Yes SMT 7 9 2 PC7 UT0RXD UT0RXD50 PU PD Yes SMT PORT D 5 7 PD0 TB5IN INTC PU PD Yes SMT 4 6 PD1 TB5OUT PU PD Yes SMT 3 5 PD2 INTD PU PD Yes SMT 2 4 PD3 INT9 PU PD Yes SMT 1 3 PD4 SCLK2 CTS2 PU PD Yes SMT 100 2 PD5 TXD2 PU PD Yes SMT 99 1 PD6 RXD2 PU PD Yes SMT PORT E 38 40 25 PE0 TXD0 PU PD Yes SMT 39 41 26 PE1 RXD0 PU PD Yes SMT 40 42 27 PE2 SCLK0 CTS0 PU PD Yes SMT 41 43 28 PE3 TB4OUT PU...

Page 37: ... SMT PORT G 22 24 PG0 PU PD Yes SMT 23 25 PG1 PU PD Yes SMT 24 26 PG2 PU PD Yes SMT 25 27 PG3 PU PD Yes SMT 26 28 PG4 PU PD Yes SMT 27 29 PG5 PU PD Yes SMT 28 30 PG6 PU PD Yes SMT 29 31 PG7 PU PD Yes SMT PORT H 62 64 39 PH0 AIN0 INT0 PU PD Yes SMT 63 65 40 PH1 AIN1 INT1 PU PD Yes SMT 64 66 41 PH2 AIN2 INT2 PU PD Yes SMT 65 67 42 PH3 AIN3 PU PD Yes SMT 66 68 43 PH4 AIN4 PU PD Yes SMT 67 69 44 PH5 A...

Page 38: ... 74 PJ0 AIN10 PU PD Yes SMT 73 75 PJ1 AIN11 PU PD Yes SMT 74 76 PJ2 AIN12 PU PD Yes SMT 75 77 PJ3 AIN13 PU PD Yes SMT 76 78 PJ4 AIN14 PU PD Yes SMT 77 79 PJ5 AIN15 PU PD Yes SMT 78 80 PJ6 AIN16 INTA PU PD Yes SMT 79 81 PJ7 AIN17 INTB PU PD Yes SMT PORT L 84 86 53 PL0 BOOT PU PD Yes SMT 85 87 54 PL2 INTF PU PD Yes SMT PORT M 20 22 15 PM0 X1 PU PD Yes SMT 18 20 13 PM1 X2 PU PD Yes SMT TMPM3V6 M3V4 1...

Page 39: ...64 1 2 3 4 5 PU PD OD SMT CMOS PORT N 48 50 PN0 PU PD Yes SMT 49 51 PN1 PU PD Yes SMT 50 52 PN2 PU PD Yes SMT 51 53 PN3 PU PD Yes SMT 52 54 PN4 PU PD Yes SMT 53 55 PN5 PU PD Yes SMT 54 56 PN6 PU PD Yes SMT 55 57 PN7 INTE PU PD Yes SMT PORT P 17 19 12 PP0 XT1 PU PD Yes SMT 16 18 11 PP1 XT2 PU PD Yes SMT TMPM3V6 M3V4 Page 17 2019 02 06 ...

Page 40: ... MODE 60 62 37 RESET 84 86 53 BOOT 1 4 2 4 Power Supply pin Table 1 11 The number of pin and pin names Pin No Power supply Pin name LQFP 100 QFP 100 LQFP64 QFP64 59 61 36 RVDD5 57 59 34 VOUT15 61 63 38 VOUT3 15 42 83 17 44 85 10 29 52 DVDD5 6 19 21 45 56 82 8 21 23 47 58 84 1 14 16 32 33 51 DVSS 81 83 50 AVDD5 80 82 49 AVSS TMPM3V6 M3V4 1 4 Pin names and Functions Page 18 2019 02 06 ...

Page 41: ...r Peripheral Function 2 1 Built in Functions of the M3V6 and M3V4 2 2 Information of Each Peripheral Function 2 2 1 Exception 2 2 2 16 bit Timer Event Counters TMRB 2 2 3 Serial Channel SIO UART 2 2 4 Universal Asynchronous Serial Communication Circuit UART 2 2 5 I2C Bus I2C SIO 2 2 6 Synchronous Serial Interface SSP 2 2 7 Analog Digital Converter ADC 2 2 8 Debug Interface TMPM3V6 M3V4 Page 19 201...

Page 42: ... PB0 1 2 3 4 5 6 7 Port C 8 PC0 1 2 3 4 5 6 7 8 PC0 1 2 3 4 5 6 7 Port D 8 PD0 1 2 3 4 5 6 7 Port E 8 PE0 1 2 3 4 5 6 7 6 PE0 1 2 3 4 5 Port F 5 PF0 1 2 3 4 2 PF0 1 Port G 8 PG0 1 2 3 4 5 6 7 Port H 8 PH0 1 2 3 4 5 6 7 8 PH0 1 2 3 4 5 6 7 Port I 8 PI0 1 2 3 4 5 6 7 8 PI0 1 2 3 4 5 6 7 Port J 8 PJ0 1 2 3 4 5 6 7 Port L 8 PL0 1 2 3 4 5 6 7 8 PL0 1 2 3 4 5 6 7 Port M 8 PM0 1 2 3 4 5 6 7 8 PM0 1 2 3 4...

Page 43: ...M3V6 M3V4 38 INT6 External interrupt pin 6 39 INT7 External interrupt pin 7 40 INTRX2 Serial channel receive interrupt ch2 41 INTTX2 Serial channel receive interrupt ch2 59 INT9 External interrupt pin 9 60 INTA External interrupt pin A 61 INTB External interrupt pin B 74 INTC External interrupt pin C 75 INTD External interrupt pin D 76 INTE External interrupt pin E TMPM3V6 M3V4 Page 21 2019 02 06 ...

Page 44: ...rs Table 2 3 Differences of channels of the TMRB M3V6 External pin Trigger function between the timers Interrupt Internal connection Channel External clock capture trigger input pin Timer flip flop output pin Capture trigger Synchronous start trigger channel Capture in terrupt TMRB interrupt Start of ADC conversion Transfer clock for SIO UART RMC TMRB0 TB0IN TB0OUT TB7OUT INTCAP00 INTCAP01 INTTB00...

Page 45: ... INTCAP00 INTCAP01 INTTB00 INTTB01 TMRB1 TB1N TB1OUT TB7OUT TB0PRUN TB0RUN INTCAP10 INTCAP11 INTTB10 INTTB11 RMC TMRB2 TB2IN TB2OUT TB7OUT TB0PRUN TB0RUN INTCAP20 INTCAP21 INTTB20 INTTB21 TMRB3 TB2OUT TB0PRUN TB0RUN INTCAP30 INTCAP31 INTTB30 INTTB31 TMRB4 TB4IN TB4OUT TB2OUT INTCAP40 INTCAP41 INTTB40 INTTB41 SIO0 SIO1 TMRB5 TB2OUT TB4PRUN TB4RUN INTCAP50 INTCAP51 INTTB50 INTTB51 INTTB51 TMRB6 TB6I...

Page 46: ... RXDx SCLKx CTSx Reception Transmission Transfer clock input SIO0 PE0 PE1 PE2 PE2 INTRX0 INTTX0 TB4OUT TMRB4 SIO1 PA5 PA6 PA4 PA4 INTRX1 INTTX1 TB4OUT TMRB4 SIO2 2 2 4 Universal Asynchronous Serial Communication Circuit UART TMPM3V6 3V4 incorporates 2 channels of the UART Table 2 7 UART Pin specifications Channel Pin specification Normal mode 50 duty mode PCFR4 7 6 11 PCFR5 7 5 000 PCFR4 7 6 00 PC...

Page 47: ...DI SP0CLK SP0FSS SSP0 PC0 PC1 PC2 PC3 2 2 7 Analog Digital Converter ADC The M3V6 incorporates one unit 18 channel AD converter the M3V4 incorporates one unit 10 channel AD converter Table 2 10 ADC pin specifications Unit Product AIN0 to 7 AIN8 to 9 AIN10 to 17 ADC M3V6 PH0 to 7 PI0 to 1 PJ0 to 7 M3V4 PH0 to 7 PI0 to 1 TMPM3V6 M3V4 Page 25 2019 02 06 ...

Page 48: ... usage of JTAG SW without TRST which is in the Debug Inter face chapter Table 2 11 Debug pin specifications TMS SWDIO TCK SWCLK TDO SWV TDI TRST JTAG Serial wire PB3 PB4 PB5 PB6 PB7 TRACECLK TRACEDATA0 TRACEDATA1 Trace output PB0 PB1 PB2 TMPM3V6 M3V4 2 Product Information 2 2 Information of Each Peripheral Function Page 26 2019 02 06 ...

Page 49: ...he CPU core and architecture refer to the Arm manual Cortex M ser ies processors in the following URL http infocenter arm com help index jsp Product Name Core Revision TMPM3V6FW r2p1 3 2 Configurable Options The Cortex M3 core has optional blocks The optional blocks of the revision r2p1 are ETM and MPU The fol lowing table shows the configurable options in the TMPM3V6 3V4 Feature Configure option ...

Page 50: ...ception For the detail of SysTick exception refer to the section of SysTick in the exception and the register of Sy sTick in the NVIC register 3 3 4 SYSRESETREQ The Cortex M3 core outputs SYSRESETREQ signal when SYSRESETREQ bit of Application Inter rupt and Reset Control Register are set TMPM3V6 3V4 provides the same operation when SYSRESETREQ signal are output Note The reset operation by SYSRESET...

Page 51: ...output when SLEEPDEEP bit of System Control Register is set These signals are output in the following circumstances Wait For Interrupt WFI instruction execution Wait For Event WFE instruction execution the timing when interrupt service routine ISR exit in case that SLEEPONEXIT bit of System Control Reg ister is set TMPM3V6 3V4 does not use SLEEPDEEP signal so that SLEEPDEEP bit must not be set And...

Page 52: ...TMPM3V6 M3V4 3 Processor Core 3 6 Exclusive access Page 30 2019 02 06 ...

Page 53: ...R means the control regis ters of all input output ports and peripheral functions The CPU register area is the processor core s internal register region For more information on each region see the Arm documentation set for the Arm Cortex M3 Note that access to regions indicated as Fault causes a memory fault if memory faults are enabled or causes a hard fault if memory faults are disabled Also do ...

Page 54: ...ndor Specific 0xE010_0000 0xFFFF_FFFF Bit Band Alias 0x43FF_FFFF 0x4200_0000 Fault SFR Fault Fault Boot ROM 4KB 0x3F81_FFFF 0x3F80_0000 0x3F7F_FFFF Fault Fault Single boot mode SFR RAM 10KB Bit Band Alias CPU Register Reg Vendor Specific Bit Band Alias Fault SFR Fault Fault Fault Fault Internal ROM 128KB Mirror 0x0000_0FFF 0x0000_0000 0x3F7F_F000 Boot ROM 4KB Mirror SFR SFR Figure 4 1 Memory Map F...

Page 55: ... Boot ROM 4KB B B B Fault Fault Single boot mode SFR Bit Band Alias Fault SFR Fault Fault Fault B B B Bit Band Alias RAM 8KB Fault Bit Band Alias Internal ROM 64KB Mirror Boot ROM 4KB Mirror CPU Register Reg CPU Register Reg SFR SFR Vendor Specific Vendor Specific Reserved B Figure 4 2 MemoryMap FLASH 64KB TMPM3V6 M3V4 Page 33 2019 02 06 ...

Page 56: ...tions via connections described as o or in the following figure shows a connec tion to a mirror area While multiple slaves are connected on the same bus master line in the Bus Matrix if multiple slave accesses are generated at the same time a priority is given to access from a master with the smallest slave number TMPM3V6 M3V4 4 Memory Map 4 2 Bus Matrix Page 34 2019 02 06 ...

Page 57: ...ex M3 System Data Instruction M0 M1 M2 M3 M4 Main RAM BOOT ROM Flash ROM S0 S1 S2 S0 S1 S2 M0 M1 M2 M3 M4 RTC CG RMC OFD POR VLTD DNF WDT I2C SIO SIO UART ADC TMRB PORT SSP UART Figure 4 3 Bus Matrix of TMPM3V6 3V4 TMPM3V6 M3V4 Page 35 2019 02 06 ...

Page 58: ...ruction M0 M1 M2 M3 M4 Main RAM BOOT ROM Flash ROM S0 S1 S2 S0 S1 S2 M0 M1 M2 M3 M4 RTC CG RMC OFD POR VLTD DNF WDT I2C SIO SIO UART ADC TMRB PORT SSP UART Figure 4 4 Bus Matrix of TMPM3V6 3V4 TMPM3V6 M3V4 4 Memory Map 4 2 Bus Matrix Page 36 2019 02 06 ...

Page 59: ... S Bus Core D Bus Core I Bus Slave S0 S1 S2 0x0000_0000 Flash ROM M0 Fault ο ο 0x0002_0000 Fault Fault Fault Fault 0x2000_0000 Main RAM M1 ο Fault Fault 0x2000_2800 Fault Fault Fault Fault 0x2200_0000 Bit band alias ο Fault Fault 0x2400_0000 Fault Fault Fault Fault TMPM3V6 M3V4 Page 37 2019 02 06 ...

Page 60: ...M M1 ο Fault Fault 0x2000_2800 Fault Fault Fault Fault 0x2200_0000 Bit band alias ο Fault Fault 0x2400_0000 Fault Fault Fault Fault 0x3F7F_F000 Boot ROM mirror M2 ο Fault Fault 0x3F80_0000 Flash ROM mirror M0 ο Fault Fault 0x3F82_0000 Fault Fault Fault Fault Note Please do not access the address range given in Reserved TMPM3V6 M3V4 4 Memory Map 4 2 Bus Matrix Page 38 2019 02 06 ...

Page 61: ... Fault Fault 0x4004_0300 Fault Fault Fault Fault 0x4004_0400 RMC M3 ο Fault Fault 0x4004_0500 Fault Fault Fault Fault 0x4004_0700 Reserved 0x4004_0800 OFD M3 ο Fault Fault 0x4004_0900 VLTD ο Fault Fault 0x4004_0A00 Fault Fault Fault Fault 0x4006_0000 DNF M3 ο Fault Fault 0x4006_0010 Fault Fault Fault Fault 0x400C_0000 SSP M4 ο Fault Fault 0x400C_2000 UART ο Fault Fault 0x400C_3000 Fault Fault Faul...

Page 62: ...ch1 0x4001_0040 ch2 0x4001_0080 ch3 0x4001_00C0 ch4 0x4001_0100 ch5 0x4001_0140 ch6 0x4001_0180 ch7 0x4001_01C0 Serial Bus interface I2C SIO ch0 0x4002_0000 Serial Channel SIO UART ch0 0x4002_0080 ch1 0x4002_00C0 ch2 0x4002_0100 Analog Digital Converter ADC 0x4003_0000 Watchdog Timer WDT 0x4004_0000 Real Time Clock RTC 0x4004_0100 Clock Mode control CG 0x4004_0200 Remote control signal preprocesso...

Page 63: ...it SYSRESETREQ To recognize a source of reset check CGRSTFLG in the clock generator register described in Chapter of Excep tion Detail about the power on reset circuit the power detection circuit the watchdog timer and the oscillation fre quency detection circuit refer to each chapter A reset by SYSRESETREQ is referred to Cortex M3 Technical Reference Manual Note Once reset operation is done inter...

Page 64: ... Operation 5 1 Cold Reset Page 42 2019 02 06 Note The above sequence is applied as well when restoring power Once power voltage is beyond operating voltage of power on reset internal reset signal is enabled TMPM3V6 M3V4 have a function to enable low voltage detection circuit VLTD operation And beyond the release voltage of power on reset kept internal reset by VLTD When the supply voltage becomes ...

Page 65: ...he supply voltage becomes upper than the detection voltage VDLVL 1 0 inter nal reset signal is released after RESET pin is set to Low IRVF V tPWUP 9 7 detection YROWDJH 9s 9 0V Power voltage operation range Power on reset release voltage CPU fetch starts Power on counter Power on detection signal Internal reset signal RESET pin If an external reset is generated ahead of this timing a reset process...

Page 66: ... reset the control register of processor core and the peripheral function control register SFR are almost in itialized System debug component registers FPB DWT and ITM of the internal core CGRSTFLG in the clock generator and FCSECBIT in the Flash related register are only initialized by cold reset When reset is released MCU starts operation by a clock of internal high speed oscillator External clo...

Page 67: ...escaler clock and warm up of the PLL clock multi plication circuit and oscillator There is also the low power consumption mode which can reduce power consumption by mode transitions This chapter describes how to control clock operating modes and mode transitions TMPM3V6 M3V4 Page 45 2019 02 06 ...

Page 68: ...x4004_0200 Register name Address Base System control register CGSYSCR 0x0000 Oscillation control register CGOSCCR 0x0004 Standby control register CGSTBYCR 0x0008 PLL selection register CGPLLSEL 0x000C System clock selection register CGCKSEL 0x0010 TMPM3V6 M3V4 6 Clock Mode control 6 2 Registers Page 46 2019 02 06 ...

Page 69: ...nce is required when setting 1 stop 19 18 R Read as 0 17 16 SCOSEL 1 0 R W SCOUT out 00 fs 01 fsys 2 10 fsys 11 φT0 Enables to output the specified clock from SCOUT pin 15 14 R Read as 0 13 12 FPSEL 1 0 R W φT0 source clock 00 The clock divided fgear by a prescaler 01 The clock divided fc by a prescaler 10 fsys 11 fsys Specifies the source clock to φT0 In the SLOW mode must be set 10 or 11 11 R Re...

Page 70: ...X2 When external oscillator is used set PMCR PMPUP PMPDN PMIE of Port M to disable After reset PMCR PMPUP PMPDN PMIE are set to disable 17 OSCSEL R W High speed oscillator Note 3 0 internal high speed oscillator 1 external high speed oscillator 16 XEN2 R W internal high speed oscillator operation 0 Stop 1 Oscillation 15 14 WUODRL 1 0 R W Warm up counter setup value Setup the 16 bit timer for warm ...

Page 71: ...er Read as 0 Note 1 Refer to Section 6 3 4 Warm up function about the Warm up setup Note 2 Refer to 6 3 5 Clock Multiplication Circuit PLL about setting PLL Note 3 If CGOSCCR OSCSEL is 1 PMCR PMPUP PMPDN PMIE can not be modified Note 4 When using fIHOSC as system clock do not use PLL multiplying TMPM3V6 M3V4 Page 49 2019 02 06 ...

Page 72: ...19 17 R W Write 0 16 DRVE R W Controls the port in STOP mode 0 Not drive ports 1 Drive ports 15 10 R Read as 0 9 RXTEN R W Low speed oscillator operation after releasing STOP mode 0 Stop 1 Oscillation 8 RXEN R W High speed oscillator operation after releasing STOP mode 0 Stop 1 Oscillation 7 3 R Read as 0 2 0 STBY 2 0 R W Low power consumption mode 000 Reserved 001 STOP 010 SLEEP 011 IDLE 100 Rese...

Page 73: ...ter reset 0 0 0 1 1 1 1 0 Bit Bit Symbol Type Function 31 16 R Read as 0 15 12 R W Write 1101 11 R Read as 0 10 8 R W Write 000 7 1 R W Write 0001111 0 PLLSEL R W Use of PLL 0 fosc use 1 fPLL use Specifies use or disuse of the clock multiplied by the PLL fosc internal high speed oscillator is automatically set after reset Resetting is required when using the PLL Note When using fIHOSC as system cl...

Page 74: ...d 1 low speed Specifies system clock When change value of SYSCK oscillation must stable High speed oscillator fEHOSC or fIHOSC and Low speed oscillator According to the used oscillator corresponding CGOSCCR XEN1 XEN2 or XTEN must be set to 1 in advance 0 SYSCKFLG R System clock status 0 high speed 1 low speed Shows the status of the system clock When switching the oscillator with SYSCK generates t...

Page 75: ...EL 1 0 Clock specified by CGSYSCR PRCK 2 0 prescaler clock The gear clock fgear and the prescaler clock φT0 are dividable as follows Gear clock fc fc 2 fc 4 fc 8 fc 16 Prescaler clock fperiph fperiph 2 fperiph 4 fperiph 8 fperiph 16 fperiph 32 6 3 2 Initial Values after Reset Reset operation initializes the clock configuration as follows internal high speed oscillator oscillating external high spe...

Page 76: ...GSYSCR PRCK 2 0 1 4 1 2 fperiph fsys ȭT0 SCOUT CGSYSCR SCOSEL 1 0 OFD CGOSCCR XEN Stops oscillation after reset 1 4 1 2 1 16 1 8 FCSTOP CGSYSCR FCSTOP Starts oscillation after reset AHB Bus I Oࠚ CPU ROM RAM BOOT ROM APB Bus I Oࠚ SSP UART IO Bus I Oࠚ TMRB WDT RTC SIO UART I2C SIO RMC ADC PORT Internal High Speed oscillator External High Speed oscillator XT1 XT2 CGOSCCR XTEN Stops oscillation after ...

Page 77: ...t CGOSCCR WUODRL 1 0 to 00 for high speed oscillation example 1 When using high speed oscillator 8MHz and set warm up time 5ms warm up time to set input frequency cycle s 4000 cycle 0x9C40 5ms 1 8MHz Round lower 4 bit off set 0x9C4 to CGOSCCR WUODR 11 0 3 confirm the start and completion of warm up The CGOSCCR WUEON WUEF is used to confirm the start and completion of warm up through software instr...

Page 78: ... clock Specifies external oscillator fEHOSC CGOSCCR WUODR 11 0 0x9C4 CGOSCCR WUODRL 1 0 00 Specifies the warm up time CGOSCCR WUODR 11 0 read Confirm warm up time reflecting Repeat until the read data is 0x9C4 CGOSCCR XEN1 1 high speed oscillator fEHOSC enable CGOSCCR WUEON 1 Start the warm up timer WUP CGOSCCR WUEF read Wait until the state becomes 0 warm up is finished TMPM3V6 M3V4 6 Clock Mode ...

Page 79: ...eed 6 3 5 1 How to configure the PLL function The PLL is disabled after reset To enable the PLL set CGOSCCR PLLON to 1 After 200μs for lock up time elapses set CGPLLSEL PLLSEL to 1 fPLL which is multiplied by 4 from fosc is used The PLL requires a certain amount of time to be stabilized which should be secured using the warm up function or other methods Note When using fIHOSC as system clock do no...

Page 80: ...ion fosc setting in the case of using external high speed oscillator CGOSCCR XEN1 1 CGOSCCR WUPSEL2 1 CGOSCCR WUPSEL1 0 CGOSCCR HOSCON 1 Set warm up time to WUODR 11 0 Start warm up counter Confirm the completion of warm up by read ing WUEF CGOSCCR OSCSEL 1 PLL operation CGOSCCR PLLON 1 PLL starts lock up time takes approximately 200μs for lock up time PLL setting CGPLLSEL PLLSEL 1 PLL used Possib...

Page 81: ...sed as the system clock Although the setting can be changed while operating the actual switching takes place after a slight delay Table 6 2 shows the example of the operation frequency by the setting PLL and the clock gear Table 6 2 The range of an operation frequency when a clock gear and PLL are used Unit MHz Reserved Don t care Input frequency PLL multiplying Min operation frequency fc Max oper...

Page 82: ...L 0 Use fosc CGSYSCR GEAR 2 0 000 No division fosc setting in the case of using internal high speed oscillator The specification is not need fosc setting in the case of using external high speed oscillator CGOSCCR WUPSEL2 1 CGOSCCR WUPSEL1 0 Select an external high speed oscillator CGOSCCR HOSCON 1 Use the external high speed oscillator CGOSCCR XEN1 1 Start external high speed oscillation Operate ...

Page 83: ...lock fsys and fsys 2 and the prescaler input clock for peripheral functions φT0 Note 1 The phase difference AC timing between the system clock output by the SCOUT and the internal clock is not guaranteed Note 2 When fsys is output from SCOUT pin SCOUT pin outputs the unexpected waveform just after changing clock gear In the case of influencing to system by the unexpected waveform the output of SCO...

Page 84: ...t used the SLOW and SLEEP modes cannot be used Figure 6 2 shows a mode transition diagram For a detail of sleep on exit refer to Cortex M3 Technical Reference Manual Reset release Reset NORMAL mode IDLE mode Interrupt Instruction sleep on exit Interrupt Instruction Instruction sleep on exit SLOW mode SLEEP mode STOP mode Interrupt Instruction sleep on exit Interrupt Instruction sleep on exit Instr...

Page 85: ... clock can also be oscillated 6 5 2 SLOW mode This mode is to operate the CPU core and the peripheral hardware by using the low speed clock with high speed clock stopped The SLOW mode reduces power consumption compared to the NORMAL mode Note 1 In the SLOW mode CGSYSCR FPSEL 1 0 must be set 10 or 11 Note 2 In the slow mode be sure not to perform reset using the Application Interrupt and Reset Cont...

Page 86: ...s prohibited The features of IDLE SLEEP STOP mode are described as follows 6 6 1 IDLE mode Only the CPU is stopped in this mode Each peripheral function has one bit in its control register for ena bling or disabling operation in the IDLE mode When the IDLE mode is entered peripheral functions for which operation in the IDLE mode is disabled stop operation and hold the state at that time The follow...

Page 87: ...ntering STOP mode Please refer to 6 6 8 Clock Operations in Mode Transition about warm up time Table 6 4 Pin States in the STOP mode Function Pin Name I O DRVE 0 DRVE 1 Oscillator X1 XT1 Input X2 XT2 Output High level output High level output PORT Px Input Depends on PxIE m Output Depends on PxCR m Debug TMS SWDIO TDO SWV Input Depends on PxIE m Output Depend on PxCR m and enable when data is vali...

Page 88: ... register CGSTBYCR STBY 2 0 Table 6 5 shows the mode setting in the STBY 2 0 Table 6 5 Low power consumption mode setting Mode CGSTBYCR STBY 2 0 STOP 001 SLEEP 010 IDLE 011 Note Do not set any value other than those shown above in STBY 2 0 TMPM3V6 M3V4 6 Clock Mode control 6 6 Low Power Consumption Modes Page 66 2019 02 06 ...

Page 89: ...ο Operation is available when in the target mode The clock to module stops automatically after transiting to the target mode It is necessary that the select module must be stopped by software before entering in the target mode Note 1 The high speed oscillator EHOSC or IHOSC does not stop automatically in SLOW mode and must be stopped by setting CGOSCCR XEN1 or XEN2 after switched from NORMAL mode ...

Page 90: ...o 71 ο INTCAP00 to 70 01 to 71 ο SysTick Interrupt ο Non Maskable Interrupt INTWDT ο Reset WDT ο Reset POR ο ο ο Reset OFD ο Reset VLTD ο ο ο Reset RESET pin ο ο ο ο Starts the interrupt handling after the mode is released The reset initializes the LSI Unavailable Note 1 When releasing from IDLE SLEEP STOP mode by interrupting level mode hold the level until the inter rupt handling starts If the l...

Page 91: ... or STOP mode Before entering in the SLEEP mode or STOP mode INTWDT must be disabled Release by reset Any low power consumption mode can be released by a reset from the RESET pin or POR Only IDLE mode can be released by a reset from OFD or WDT The SLEEP mode and STOP mode can not be released by a reset from OFD or WDT Before entering in the SLEEP mode or STOP mode the reset from OFD and WDT must b...

Page 92: ...scillator and then activate the warm up In regard to warm up time please refer to 6 6 8 Clock Operations in Mode Transition Table 6 8 shows whether the warm up setting of each mode transition is required or not Table 6 8 Warm up setting in mode transition Mode transition Warm up setting NORMAL IDLE Not required NORMAL SLEEP Not required Note1 NORMAL SLOW Not required Note1 NORMAL STOP Not required...

Page 93: ... internal or external high speed oscilla tor If PLL is used the warm up time must be added a lock up time approximate 200μs Returning to the NORMAL mode by reset does not induce the automatic warm up The reset signal as same as a cold reset should be input fsys System clock STOP fosc NORMAL NORMAL Mode Warm up System clock stops Internal high speed clock starts oscillating Warm up starts WFI instr...

Page 94: ...he NORMAL mode by reset does not induce the automatic warm up The reset signal as same as a cold reset should be input fsys System clock SLEEP fosc NORMAL NORMAL Mode Warm up System clock stops Internal high speed clock starts oscillating Warm up starts WFI instruction sleep on exit Release event occurs Warm up completes System clock starts 1UEKNNCVKQP EQPVKPWGU fs QY URGGF ENQEM TMPM3V6 M3V4 6 Cl...

Page 95: ...tem clock stops External low speed clock starts oscillating Warm up starts WFI instruction sleep on exit Release event occurs Warm up completes System clock starts 6 6 8 4 Transition of operation modes SLOW SLEEP SLOW The external low speed oscillator continues oscillation in the SLEEP mode There is no need to make a warm up setting fsys System clock fs SLEEP fs SLOW SLOW Mode System clock stops W...

Page 96: ...ediately after the WFI instruction and then write the instruction to be executed b Case when the interrupts are enabled Write the interrupt process routine because the MCU branches to the interrupt service rou tine 2 Before the MCU entering SLEEP mode or STOP mode select the clock with CGOSCCR WUPSEL1 WUPSEL2 which is the same as the clock selected with CGOSCCR OSCSEL to use the same source clock ...

Page 97: ...pin or peripheral function All exceptions are handled by the Nested Vectored Interrupt Controller NVIC in the CPU according to the re spective priority levels When an exception occurs the CPU stores the current state to the stack and branches to the corresponding interrupt service routine ISR Upon completion of the ISR the information stored to the stack is automatically restored 7 1 1 Exception T...

Page 98: ...on by CG CPU The CG CPU detects the exception request Section 7 1 2 1 Handling by CPU The CPU handles the exception request Section 7 1 2 2 Branch to ISR The CPU branches to the corresponding interrupt service routine ISR Execution of ISR Necessary processing is executed Section 7 1 2 3 Return from exception The CPU branches to another ISR or returns to the previous program Section 7 1 2 4 TMPM3V6...

Page 99: ...d If a disabled exception occurs it is handled as Hard Fault Table 7 1 Exception Types and Priority No Exception type Priority Description 1 Reset 3 highest Reset pin WDT POR OFD VLTD SYSRESETREQ 2 Non Maskable Interrupt 2 WDT 3 Hard Fault 1 Fault that cannot activate because a higher priority fault is being han dled or it is disabled 4 Memory Management Configurable Exception from the Memory Prot...

Page 100: ...e emption priority If the priority is the same as the pre emption priority then it is compared with the sub priority If the sub priority is the same as the priority the smaller the exception number the higher the priority The Table 7 2 shows the priority group setting The pre emption priority and the sub pri ority in the table are the number in the case that PRI_n is defined as an 8 bit configurat...

Page 101: ... have been pushed Old SP previous xPSR PC LR r12 r3 r2 r1 SP r0 2 Fetching an ISR The CPU enables instruction to fetch the interrupt processing with data store to the register Prepare a vector table containing the top addresses of ISRs for each exception After reset the vec tor table is located at address 0x0000_0000 in the Code area By setting the Vector Table Offset Reg ister you can place the v...

Page 102: ...dress Required 0x0C Hard Fault ISR address Required 0x10 Memory Management ISR address Optional 0x14 Bus Fault ISR address Optional 0x18 Usage Fault ISR address Optional 0x1C to 0x28 Reserved 0x2C SVCall ISR address Optional 0x30 Debug Monitor ISR address Optional 0x34 Reserved 0x38 PendSV ISR address Optional 0x3C SysTick ISR address Optional 0x40 External Interrupt ISR address Optional 7 1 2 3 E...

Page 103: ...ighest priority stacked exception is of high er priority than the highest priority pending exception the CPU returns to the last stacked ISR Returning to the previous program If there are no pending or stacked exceptions the CPU returns to the previous program 2 Exception exit sequence When returning from an ISR the CPU performs the following operations Pop eight registers Pops the eight registers...

Page 104: ... reset exception occurs when the power is turned on For details see the chapter on the POR Reset exception by OFD The oscillation frequency detection OFD has a reset generating feature For details see the chapter on the OFD Reset exception by VLTD The Voltage Level Detector VLTD has a reset generating feature For details see the chapter on the VLTD 7 3 Non Maskable Interrupts NMI Non maskable inte...

Page 105: ...ption occurs You may be pending exceptions and use a flag to know when the timer reaches 0 The SysTick Calibration Value Register holds a reload value for counting 10 ms with the system timer The count clock frequency varies with each product and so the value set in the SysTick Calibration Value Register al so varies with each product Note In this product the systick timer counts based on an exter...

Page 106: ...issued by the peripheral function that is not used to release standby are directly input to the CPU route 1 The peripheral function interrupts used to release standby route 2 and interrupts from the external inter rupt pin route 3 are input to the clock generator and are input to the CPU through the logic for releas ing standby route 4 and 5 If interrupts from the external interrupt pins are not u...

Page 107: ...for clearing a standby mode are transmitted to the CPU via the clock generator For these interrupt sources appropriate settings must be made in the clock generator in advance External interrupt sources not used for exiting a standby mode can be used with out setting the clock generator 7 5 1 4 Precautions when using external interrupt pins If you use external interrupts be aware the followings not...

Page 108: ...ved Reserved 17 INTRTC RTC interrupt ο CGIMCGE 18 Reserved Reserved 19 INTRMCRX Remote Controller reception interrupt ο CGIMCGE 20 INTTB00 16 bit TMRB compare match detection 0 overflow channel 0 21 INTTB01 16 bit TMRB compare match detection 1 channel 0 22 INTTB10 16 bit TMRB compare match detection 0 overflow channel 1 23 INTTB11 16 bit TMRB compare match detection 1 channel 1 24 INTTB40 16 bit ...

Page 109: ...RB input capture 0 channel 2 51 INTCAP21 16 bit TMRB input capture 1 channel 2 52 INTCAP30 16 bit TMRB input capture 0 channel 3 53 INTCAP31 16 bit TMRB input capture 1 channel 3 54 INTADSFT ADC conversion started by software is fin ished 55 Reserved Reserved 56 INTADTMR ADC conversion triggered by timer is finish ed 57 Reserved Reserved 58 INT8 External interrupt pin 8 ο ο ο ο ο CGIMCGC 59 INT9 E...

Page 110: ...ignals directly sent from peripheral func tions to the CPU are configured to output High to indicate an interrupt request Active level is set to the clock generator for interrupts which can be a trigger to release standby Inter rupt requests from peripheral functions are set as rising edge or falling edge triggered Interrupt requests from interrupt pins can be set as level sensitive High or Low or...

Page 111: ...rom external pin Port οSetting for interrupt from peripheral function Peripheral function See the chapter of each peripheral function for details Interrupt generation An interrupt request is generated CG detects interrupt clearing standby mode Clearing standby mode Not clearing standby mode Interrupt lines used for clearing a standby mode are connected to the CPU via the clock generator 7 5 2 3 De...

Page 112: ...Program for the ISR Clear the interrupt source if needed 7 5 2 6 Interrupt Service Routine ISR Return to preceding program Configure to return to the preceding program of the ISR TMPM3V6 M3V4 7 Exceptions 7 5 Interrupts Page 90 2019 02 06 ...

Page 113: ...ction 5 Preconfiguration 3 Interrupt Set Pending Register 6 Configuring the clock generator 7 Enabling interrupt by CPU 1 Disabling interrupt by CPU To make the CPU for not accepting any interrupt write 1 to the corresponding bit of the PRI MASK Register All interrupts and exceptions other than non maskable interrupts and hard faults can be masked Use MSR instruction to set this register Interrupt...

Page 114: ... Precautions when us ing external interrupt pins 4 Preconfiguration 2 Interrupt from peripheral function The setting varies depending on the peripheral function to be used See the chapter of each periph eral function for details 5 Preconfiguration 3 Interrupt Set Pending Register To generate an interrupt by using the Interrupt Set Pending Register set 1 to the corresponding bit of this register NV...

Page 115: ...gister setting factors to trigger interrupts are lost if pending interrupts are cleared Thus this operation is not necessary At the end PRIMASK register is zero cleared NVIC register Interrupt Clear Pending m 1 Interrupt Set Enable m 1 Interrupt mask register PRIMASK 0 Note 1 m corresponding bit Note 2 PRIMASK register cannot be modified by the user access level 7 5 2 3 Detection by Clock Generato...

Page 116: ...f needed Interrupt requests with higher priority and exceptions such as NMI are accepted even when an ISR is being executed We recommend you to push the contents of general purpose registers that might be rewritten 2 Clearing an interrupt source If an interrupt source is used for clearing a standby mode each interrupt request must be cleared with the CG Interrupt Request Clear CGICRCG Register If ...

Page 117: ...ing Register 2 0x0204 Interrupt Set Pending Register 3 0x0208 Interrupt Clear Pending Register 1 0x0280 Interrupt Clear Pending Register 2 0x0284 Interrupt Clear Pending Register 3 0x0288 Interrupt Priority Register 0x0400 to 0x045C Vector Table Offset Register 0x0D08 Application Interrupt and Reset Control Register 0x0D0C System Handler Priority Register 0x0D18 0x0D1C 0x0D20 System Handler Contro...

Page 118: ...turns 1 if timer counted to 0 since last time this was read Clears on read of any part of the SysTick Control and Status Register 15 3 R Read as 0 2 CLKSOURCE R W 0 External reference clock fosc 32 Note 1 CPU clock fsys 1 TICKINT R W 0 Do not pend SysTick 1 Pend SysTick 0 ENABLE R W 0 Disable 1 Enable If 1 is set it reloads with the value of the Reload Value Register and starts operation Note In t...

Page 119: ... Register when the timer reaches 0 7 6 2 3 SysTick Current Value Register 31 30 29 28 27 26 25 24 bit symbol After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol CURRENT After reset Undefined 15 14 13 12 11 10 9 8 bit symbol CURRENT After reset Undefined 7 6 5 4 3 2 1 0 bit symbol CURRENT After reset Undefined Bit Bit Symbol Type Function 31 24 R Read as 0 23 0 CURRENT R W Read Current S...

Page 120: ...l TENMS After reset 1 1 0 0 0 1 0 0 Bit Bit Symbol Type Function 31 NOREF R 0 Reference clock provided 1 No reference clock 30 SKEW R 0 Calibration value is 10 ms 1 Calibration value is not 10 ms 29 24 R Read as 0 23 0 TENMS R Calibration value Reload value to use for 10 ms timing 0x9C4 Note Note When using a multi shot timer the calibration value is subtracted 1 from this value and use it TMPM3V6...

Page 121: ...en set this register to 1 the corresponding interrupt is enabled Writing 0 has no meaning When this register is read whether the corresponding interrupt is enabled or disabled is identified To clear the bit of this register set 1 to the corresponding bit of the interrupt clear enable register Bit symbol Type Function SETENA R W Interrupt No 77 0 Write 1 Enables interrupts Read 0 Interrupts are dis...

Page 122: ... reset 0 0 0 0 0 0 0 0 b Interrupt Set Enable Register 2 31 30 29 28 27 26 25 24 Bit symbol SETENA Interrupt 61 SETENA Interrupt 60 SETENA Interrupt 59 SETENA Interrupt 58 SETENA Interrupt 56 After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 Bit symbol SETENA Interrupt 54 SETENA Interrupt 53 SETENA Interrupt 52 SETENA Interrupt 51 SETENA Interrupt 50 SETENA Interrupt 49 SETENA Interrupt 48 After...

Page 123: ...1 10 9 8 Bit symbol SETENA Interrupt 77 SETENA Interrupt 76 SETENA Interrupt 75 SETENA Interrupt 74 SETENA Interrupt 73 SETENA Interrupt 72 After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Bit symbol SETENA Interrupt 71 SETENA Interrupt 70 SETENA Interrupt 69 SETENA Interrupt 68 SETENA Interrupt 67 SETENA Interrupt 66 After reset 0 0 0 0 0 0 0 0 TMPM3V6 M3V4 Page 101 2019 02 06 ...

Page 124: ...this register is read whether the corresponding interrupt is enabled or disabled is identified Bit symbol Type Function CLRENA R W Interrupt No 77 0 Write 1 Disables interrupts Read 0 Interrupts are disabled 1 Interrupts are enabled Note For descriptions of interrupts and interrupt numbers see Section 7 5 1 5 List of Inter rupt Sources TMPM3V6 M3V4 7 Exceptions 7 6 Exception Interrupt Related Regi...

Page 125: ... 1 CLRENA Interrupt 0 After reset 0 0 0 0 0 0 0 0 b Interrupt Clear Enable Register 2 31 30 29 28 27 26 25 24 Bit symbol CLRENA Interrupt 61 CLRENA Interrupt 60 CLRENA Interrupt 59 CLRENA Interrupt 58 CLRENA Interrupt 56 After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 Bit symbol CLRENA Interrupt 54 CLRENA Interrupt 53 CLRENA Interrupt 52 CLRENA Interrupt 51 CLRENA Interrupt 50 CLRENA Interrupt...

Page 126: ... Interrupt 77 CLRENA Interrupt 76 CLRENA Interrupt 75 CLRENA Interrupt 74 CLRENA Interrupt 73 CLRENA Interrupt 72 After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Bit symbol CLRENA Interrupt 71 CLRENA Interrupt 70 CLRENA Interrupt 69 CLRENA Interrupt 68 CLRENA Interrupt 67 CLRENA Interrupt 66 After reset 0 0 0 0 0 0 0 0 TMPM3V6 M3V4 7 Exceptions 7 6 Exception Interrupt Related Registers Page 104 2019 0...

Page 127: ...terrupt which has already been suspended or disabled Writing 0 has no meaning When this register is read whether the corresponding interrupt is suspended or not Bit symbol Type Function SETPEND R W Interrupt No 77 0 Write 1 Interrupts are suspended Read 0 No pending interrupts 1 Pending interrupts exist Note For descriptions of interrupts and interrupt numbers see Section 7 5 1 5 List of Inter rup...

Page 128: ... Undefined Undefined b Interrupt Set Pending Register 2 31 30 29 28 27 26 25 24 Bit symbol SETPEND Interrupt 61 SETPEND Interrupt 60 SETPEND Interrupt 59 SETPEND Interrupt 58 SETPEND Interrupt 56 After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 23 22 21 20 19 18 17 16 Bit symbol SETPEND Interrupt 54 SETPEND Interrupt 53 SETPEND Interrupt 52 SETPEND Interr...

Page 129: ...9 8 Bit symbol SETPEND Interrupt 77 SETPEND Interrupt 76 SETPEND Interrupt 75 SETPEND Interrupt 74 SETPEND Interrupt 73 SETPEND Interrupt 72 After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 7 6 5 4 3 2 1 0 Bit symbol SETPEND Interrupt 71 SETPEND Interrupt 70 SETPEND Interrupt 69 SETPEND Interrupt 68 SETPEND Interrupt 67 SETPEND Interrupt 66 After reset Un...

Page 130: ...dy been started Writing 0 has no meaning When this register is read it indicates whether the corresponding interrupt is suspended Bit symbol Type Function CLRPEND R W Interrupt No 77 0 Write 1 Clears pending interrupts Read 0 No pending interrupts 1 Pending interrupts exists Note For descriptions of interrupts and interrupt numbers see Section 7 5 1 5 List of Inter rupt Sources TMPM3V6 M3V4 7 Exce...

Page 131: ...ndefined Undefined Undefined Undefined Undefined b Interrupt Clear Pending Register 2 31 30 29 28 27 26 25 24 Bit symbol CLRPEND Interrupt 61 CLRPEND Interrupt 60 CLRPEND Interrupt 59 CLRPEND Interrupt 58 CLRPEND Interrupt 56 After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 23 22 21 20 19 18 17 16 Bit symbol CLRPEND Interrupt 54 CLRPEND Interrupt 53 CLRPE...

Page 132: ...rrupt 77 CLRPEND Interrupt 76 CLRPEND Interrupt 75 CLRPEND Interrupt 74 CLRPEND Interrupt 73 CLRPEND Interrupt 72 After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 7 6 5 4 3 2 1 0 Bit symbol CLRPEND Interrupt 71 CLRPEND Interrupt 70 CLRPEND Interrupt 69 CLRPEND Interrupt 68 CLRPEND Interrupt 67 CLRPEND Interrupt 66 After reset Undefined Undefined Undefined...

Page 133: ...I_54 PRI_53 PRI_52 0xE000_E438 PRI_59 PRI_58 PRI_56 0xE000_E43C PRI_61 PRI_60 0xE000_E440 PRI_67 PRI_66 0xE000_E444 PRI_71 PRI_70 PRI_69 PRI_68 0xE000_E448 PRI_75 PRI_74 PRI_73 PRI_72 0xE000_E44C PRI_77 PRI_76 The number of bits to be used for assigning a priority varies with each product This product uses three bits for assigning a priority The following shows the fields of the Interrupt Priority...

Page 134: ...ead as 0 23 21 PRI_2 R W Priority of interrupt number 2 20 16 R Read as 0 15 13 PRI_1 R W Priority of interrupt number 1 12 8 R Read as 0 7 5 PRI_0 R W Priority of interrupt number 0 4 0 R Read as 0 TMPM3V6 M3V4 7 Exceptions 7 6 Exception Interrupt Related Registers Page 112 2019 02 06 ...

Page 135: ... Bit Symbol Type Function 31 30 R Read as 0 29 TBLBASE R W Table base The vector table is in 0 Code space 1 SRAM space 28 7 TBLOFF R W Offset value Set the offset value from the top of the space specified in TBLBASE The offset must be aligned based on the number of exceptions in the table This means that the minimum alignment is 32 words that you can use for up to 16 interrupts For more interrupts...

Page 136: ...f subpriority 100 three bits of pre emption priority five bits of subpriority 101 two bits of pre emption priority six bits of subpriority 110 one bit of pre emption priority seven bits of subpriority 111 no pre emption priority eight bits of subpriority The bit configuration to split the interrupt priority register PRI_n into pre emption priority and sub priority 7 3 R Read as 0 2 SYSRESET REQ R ...

Page 137: ...assigning a priority The following shows the fields of the System Handler Priority Registers for Memory Management Bus Fault and Usage Fault Unused bits return 0 when read and writing to unused bits has no effect 31 30 29 28 27 26 25 24 bit symbol PRI_7 After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol PRI_6 After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol PRI_5 After rese...

Page 138: ... 31 19 R Read as 0 18 USGFAULT ENA R W Usage Fault 0 Disabled 1 Enable 17 BUSFAUL TENA R W Bus Fault 0 Disabled 1 Enable 16 MEMFAULT ENA R W Memory Management 0 Disabled 1 Enable 15 SVCALL PENDED R W SVCall 0 Not pended 1 Pended 14 BUSFAULT PENDED R W Bus Fault 0 Not pended 1 Pended 13 MEMFAULT PENDED R W Memory Management 0 Not pended 1 Pended 12 USGFAULT PENDED R W Usage Fault 0 Not pended 1 Pen...

Page 139: ... Read as 0 1 BUSFAULT ACT R W Bus Fault 0 Inactive 1 Active 0 MEMFAULT ACT R W Memory Management 0 Inactive 1 Active Note You must clear or set the active bits with extreme caution because clearing and setting these bits does not repair stack contents TMPM3V6 M3V4 Page 117 2019 02 06 ...

Page 140: ...CGx 2 0 R W Sets the active level for release of low power con sumption mode The factor of active level can be selected from Ta ble 7 3 000 Low level 001 High level 010 Falling edge 011 Rising edge 100 Both edges Settings other than the above Prohibited EMSTx 1 0 R Detected active level This bit is valid only when EMCGx 2 0 100 00 01 Rising edge 10 Falling edge 11 Both edges INTxEN R W Release the...

Page 141: ...6 2 0 ο ο ο ο ο INT7 External interrupt pin 7 CGIMCGB EMCG7 2 0 ο ο ο ο ο INT8 External interrupt pin 8 CGIMCGC EMCG8 2 0 ο ο ο ο ο INT9 External interrupt pin 9 CGIMCGC EMCG9 2 0 ο ο ο ο ο INTA External interrupt pin A CGIMCGC EMCGA 2 0 ο ο ο ο ο INTB External interrupt pin B CGIMCGC EMCGB 2 0 ο ο ο ο ο INTC External interrupt pin C CGIMCGD EMCGC 2 0 ο ο ο ο ο INTD External interrupt pin D CGIMCG...

Page 142: ... 7 Note 5 Undefined value is read from bits 25 17 9 and 1 2 CGIMCGB CG Interrupt Mode Control Register B 31 30 29 28 27 26 25 24 Bit symbol EMCG7 EMST7 INT7EN After reset 0 0 1 0 0 0 undefined 0 23 22 21 20 19 18 17 16 Bit symbol EMCG6 EMST6 INT6EN After reset 0 0 1 0 0 0 undefined 0 15 14 13 12 11 10 9 8 Bit symbol EMCG5 EMST5 INT5EN After reset 0 0 1 0 0 0 undefined 0 7 6 5 4 3 2 1 0 Bit symbol ...

Page 143: ...read from bits 31 23 15 and 7 Note 5 Undefined value is read from bits 25 17 9 and 1 4 CGIMCGD CG Interrupt Mode Control Register D 31 30 29 28 27 26 25 24 Bit symbol EMCGF EMSTF INTFEN After reset 0 0 1 0 0 0 undefined 0 23 22 21 20 19 18 17 16 Bit symbol EMCGE EMSTE INTEEN After reset 0 0 1 0 0 0 undefined 0 15 14 13 12 11 10 9 8 Bit symbol EMCGD EMSTD INTDEN After reset 0 0 1 0 0 0 undefined 0 ...

Page 144: ... request Refer to Table 7 4 Note 2 EMSTx is valid only when EMCGx 2 0 is set to 100 for both on rising and falling edges In the other cases the value is undefined The active level used for release of low power consumption mode can be checked by reading EMSTx If interrupts are cleared with the CGICRCG register EMSTx is also cleared Note 3 Do not specify INTxEN when the edge is selected Select the e...

Page 145: ...5 4 3 2 1 0 Bit symbol ICRCG After reset 0 0 0 0 0 0 0 0 Bit Bit symbol Type Function 31 5 R Read as 0 4 0 ICRCG 4 0 W Clear interrupt requests 0_0000 INT0 0_1000 INT8 1_0000 INTRTC 0_0001 INT1 0_1001 INT9 1_0001 INTRMCRX 0_0010 INT2 0_1010 INTA 0_0011 INT3 0_1011 INTB 0_0100 INT4 0_1100 INTC 0_0101 INT5 0_1101 INTD 0_0110 INT6 0_1110 INTE 0_0111 INT7 0_1111 INTF 1_00010 to 1_1111 setting prohibit...

Page 146: ...bit symbol After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol NMIFLG0 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31 3 R Read as 0 2 1 R Reads as undefined 0 NMIFLG0 R NMI source generation flag 0 not applicable 1 generated from WDT Note NMIFLG are cleared to 0 when they are read TMPM3V6 M3V4 7 Exceptions 7 6 Exception Interrupt Related Registers Page 124 2019 02 06 ...

Page 147: ...ritten 1 Reset from SYSRESETREQ 3 VLTDRSTF R W VLTD reset flag 0 0 is written 1 Reset from VLTD 2 WDTRSTF R W WDT reset flag 0 0 is written 1 Reset from WDT 1 PINRSTF R W RESET pin flag 0 0 is written 1 Reset from RESET pin 0 PONRSTF R W Power On reset flag 0 0 is written 1 Reset from Power On reset Note 1 This flag indicates a reset generated by the SYSRESETREQ bit of the Application Interrupt an...

Page 148: ...TMPM3V6 M3V4 7 Exceptions 7 6 Exception Interrupt Related Registers Page 126 2019 02 06 ...

Page 149: ...rupt request External interrupt pin INT1 Filtering circuit NFCKCR NFCKS NFENCR NFEN1 Port control Noise filter circuit INT2 interrupt request External interrupt pin INT2 Filtering circuit NFCKCR NFCKS NFENCR NFEN2 Port control Noise filter circuit INTF interrupt request External interrupt pin INTF Filtering circuit NFCKCR NFCKS NFENCR NFEN Port control Noise filter circuit INTE interrupt request E...

Page 150: ...er List Base Address 0x4006_0000 Register name Address Base Noise filter control register NFCKCR 0x0000 Noise filter enable register NFENCR 0x0004 TMPM3V6 M3V4 8 Digital Noise Filter Circuit DNF 8 2 Registers Page 128 2019 02 06 ...

Page 151: ... 2 0 R W Noise filter clock selection 000 Clock control circuit stops 001 fsys 2 clock output 010 fsys 4 clock output 011 fsys 8 clock output 100 fsys 16 clock output 101 fsys 32 clock output 110 fsys 64 clock output 111 fsys 128 clock output Note 1 NFCKCR NFCKS setting is specified in NFENCR NFEN2 NFEN1 NFEN0 000 Note 2 If external inputs are used to release STOP mode the noise filter circuit can...

Page 152: ... W INTD noise filter is enabled disabled 0 Disabled 1 Enabled 12 NFENC R W INTC noise filter is enabled disabled 0 Disabled 1 Enabled 11 NFENB R W INTB noise filter is enabled disabled 0 Disabled 1 Enabled 10 NFENA R W INTA noise filter is enabled disabled 0 Disabled 1 Enabled 9 NFEN9 R W INT9 noise filter is enabled disabled 0 Disabled 1 Enabled 8 NFEN8 R W INT8 noise filter is enabled disabled 0...

Page 153: ...nal and noise filter circuit counter are cleared when releasing STOP mode Note Enabled Post noise filtering output signal Note Some pulses shorter than fsys cannot be filtered noise Especially in the case that fsys frequency is low noise filtering operation may not be effective Note Before external interrupt signals are enabled clear the interrupt events and then set the correspond ing bit of NFEN...

Page 154: ... 3 Noise Filter Usable Operation Mode The noise filter circuit can be used only in the NORMAL mode and IDLE mode 8 3 4 Precautions on Use of STOP Mode If STOP mode is used the noise filter circuit cannot be used due to a stop of fsys clock If external input are used to release STOP mode set the following procedure Set the interrupt enable bit to be disabled set the noise filter enable disable bit ...

Page 155: ...signed function can be enabled by setting 1 This register exists for the each function assigned to the port In case of having some function only one function can be ena bled PxOD Open drain control register 0 CMOS 1 Open drain This register controls programmable open drain outputs Programmable open drain outputs are set with PxOD When output data is 1 output buffer is disabled and be comes a pseud...

Page 156: ... PIDATA PJDATA Output control register 0x0004 PFCR PGCR PHCR PICR PJCR Function register 1 0x0008 PFFR1 PHFR1 PJFR1 Function register 2 0x000C PFFR2 Function register 3 0x0010 Function register 4 0x0014 Open drain control register 0x0028 PFOD PGOD PHOD PIOD PJOD Pull up control register 0x002C PFPUP PGPUP PHPUP PIPUP PJPUP Pull down control register 0x0030 PFPDN PGPDN PHPDN PIPDN PJPDN Input contr...

Page 157: ... Setting List Table 9 12 PORT M Setting List Table 9 13 PORT N Setting List Table 9 14 PORT P Setting List The cell of PxFRn shows the function register which must be set to select a function If this register is set to 1 the corresponding function is enabled A bit in the cell filled with a hatch is read as 0 and the writing a data to this bit is invalid 0 or 1 in the table is shown the value which...

Page 158: ...utput Port Output 0 1 1 0 0 1 0 1 0 1 0 TB1OUT Output FT1 0 1 1 PAFR1 0 1 0 1 0 1 0 RXIN0 Input FT1 0 1 0 PAFR2 0 1 0 1 0 1 1 PA4 After reset 0 0 0 0 0 0 0 Input Port Input 0 1 0 0 0 1 0 1 0 1 1 Output Port Output 0 1 1 0 0 1 0 1 0 1 0 SCLK1 Input FT1 0 1 0 PAFR1 0 1 0 1 0 1 1 Output 0 1 1 PAFR1 0 1 0 1 0 1 0 CTS1 Input FT1 0 1 0 PAFR2 0 1 0 1 0 1 1 PA5 After reset 0 0 0 0 0 0 0 Input Port Input 0...

Page 159: ...0 1 0 1 1 Output Port Output 0 1 1 0 0 1 0 1 0 1 0 TMS Input FT2 0 1 0 PBFR1 0 1 0 1 0 1 1 SWDIO I O FT2 0 1 1 PBFR1 0 1 0 1 0 1 1 PB4 After reset TCK SWCLK 0 0 PBFR1 0 0 1 1 Input Port Input 0 1 0 0 0 1 0 1 0 1 1 Output Port Output 0 1 1 0 0 1 0 1 0 1 0 TCK Input FT2 0 1 0 PBFR1 0 1 0 1 0 1 1 SWCLK Input FT2 0 1 0 PBFR1 0 1 0 1 0 1 1 PB5 After reset TDO SWV 0 1 PBFR1 0 0 0 0 Input Port Input 0 1 ...

Page 160: ...0 SCK0 Input FT1 0 1 0 PCFR3 0 1 0 1 0 1 1 Output 0 1 1 PCFR3 0 1 0 1 0 1 0 PC3 After reset 0 0 0 0 0 0 0 Input Port Input 0 1 0 0 0 1 0 1 0 1 1 Output Port Output 0 1 1 0 0 1 0 1 0 1 0 SP0FSS Input FT3 0 1 0 PCFR2 0 1 0 1 0 1 1 Output 0 1 1 PCFR2 0 1 0 1 0 1 0 PC4 After reset 0 0 0 0 0 0 0 Input Port Input 0 1 0 0 0 1 0 1 0 1 1 Output Port Output 0 1 1 0 0 1 0 1 0 1 0 PC5 After reset 0 0 0 0 0 0 ...

Page 161: ...ut 0 1 1 0 0 1 0 1 0 1 0 INTD Input FT4 0 1 0 PDFR3 0 1 0 1 0 1 1 PD3 After reset 0 0 0 0 0 0 0 Input Port Input 0 1 0 0 0 1 0 1 0 1 1 Output Port Output 0 1 1 0 0 1 0 1 0 1 0 INT9 Input FT4 0 1 0 PDFR1 0 1 0 1 0 1 1 PD4 After reset 0 0 0 0 0 0 0 Input Port Input 0 1 0 0 0 1 0 1 0 1 1 Output Port Output 0 1 1 0 0 1 0 1 0 1 0 SCLK2 Input FT1 0 1 0 PDFR1 0 1 0 1 0 1 1 Output 0 1 1 PDFR1 0 1 0 1 0 1 ...

Page 162: ... Input 0 1 0 0 0 1 0 1 0 1 1 Output Port Output 0 1 1 0 0 1 0 1 0 1 0 TB4OUT Output FT1 0 1 1 PEFR1 0 1 0 1 0 1 0 PE4 After reset 0 0 0 0 0 0 0 Input Port Input 0 1 0 0 0 1 0 1 0 1 1 Output Port Output 0 1 1 0 0 1 0 1 0 1 0 TB2IN Input FT1 0 1 0 PEFR1 0 1 0 1 0 1 1 INT5 Input FT4 0 1 0 PEFR2 0 1 0 1 0 1 1 PE5 After reset 0 0 0 0 0 0 0 Input Port Input 0 1 0 0 0 1 0 1 0 1 1 Output Port Output 0 1 1...

Page 163: ...put Port Input 0 1 0 0 0 1 0 1 0 1 1 Output Port Output 0 1 1 0 0 1 0 1 0 1 0 TB7OUT Output FT1 0 1 1 PFFR1 0 1 0 1 0 1 0 ALARM Output FT1 0 1 1 PFFR2 0 1 0 1 0 1 0 PF2 After reset 0 0 0 0 0 0 0 Input Port Input 0 1 0 0 0 1 0 1 0 1 1 Output Port Output 0 1 1 0 0 1 0 1 0 1 0 PF3 After reset 0 0 0 0 0 0 0 Input Port Input 0 1 0 0 0 1 0 1 0 1 1 Output Port Output 0 1 1 0 0 1 0 1 0 1 0 PF4 After reset...

Page 164: ...put Port Output 0 1 1 0 1 0 1 0 1 0 PG3 After reset 0 0 0 0 0 0 Input Port Input 0 1 0 0 1 0 1 0 1 1 Output Port Output 0 1 1 0 1 0 1 0 1 0 PG4 After reset 0 0 0 0 0 0 Input Port Input 0 1 0 0 1 0 1 0 1 1 Output Port Output 0 1 1 0 1 0 1 0 1 0 PG5 After reset 0 0 0 0 0 0 Input Port Input 0 1 0 0 1 0 1 0 1 1 Output Port Output 0 1 1 0 1 0 1 0 1 0 PG6 After reset 0 0 0 0 0 0 Input Port Input 0 1 0 0...

Page 165: ...N2 Input FT5 0 1 0 0 1 0 0 0 PH3 After reset 0 0 0 0 0 0 0 Input Port Input 0 0 0 0 1 0 1 0 1 1 Output Port Output 0 1 0 0 1 0 1 0 1 0 AIN3 Input FT5 0 1 0 0 1 0 0 0 PH4 After reset 0 0 0 0 0 0 0 Input Port Input 0 0 0 0 1 0 1 0 1 1 Output Port Output 0 1 0 0 1 0 1 0 1 0 AIN4 Input FT5 0 1 0 0 1 0 0 0 PH5 After reset 0 0 0 0 0 0 0 Input Port Input 0 0 0 0 1 0 1 0 1 1 Output Port Output 0 1 0 0 1 0...

Page 166: ...0 0 1 0 1 0 1 1 Output Port Output 0 1 0 1 0 1 0 1 0 AIN8 Input FT5 0 1 0 0 1 0 0 0 PI1 After reset 0 0 0 0 0 0 Input Port Input 0 0 0 1 0 1 0 1 1 Output Port Output 0 1 0 1 0 1 0 1 0 AIN9 Input FT5 0 1 0 0 1 0 0 0 Note To use the Port I as an analog input of the AD converter disable input on PIIE and disable pull up on PIPUP TMPM3V6 M3V4 9 Input Output port 9 1 Registers Page 144 2019 02 06 ...

Page 167: ...tput 0 1 0 0 1 0 1 0 1 0 AIN13 Input FT5 0 1 0 0 1 0 0 0 PJ4 After reset 0 0 0 0 0 0 0 Input Port Input 0 0 0 0 1 0 1 0 1 1 Output Port Output 0 1 0 0 1 0 1 0 1 0 AIN14 Input FT5 0 1 0 0 1 0 0 0 PJ5 After reset 0 0 0 0 0 0 0 Input Port Input 0 0 0 0 1 0 1 0 1 1 Output Port Output 0 1 0 0 1 0 1 0 1 0 AIN15 Input FT5 0 1 0 0 1 0 0 0 PJ6 After reset 0 0 0 0 0 0 0 Input Port Input 0 0 0 0 1 0 1 0 1 1 ...

Page 168: ... Port Input 0 1 0 0 0 1 0 1 0 1 1 Output Port Output 0 1 1 0 0 1 0 1 0 1 0 INTF Input FT4 0 1 0 PLFR1 0 1 0 1 0 1 1 Note 2 PL0 works as a BOOT function It is enabled to be input and pulled up while RESET pin is Low At the rising edge of the reset signal if PL0 is High the device enters single chip mode and boots from the on chip flash memory If PL0 is Low the device enters single BOOT mode and boo...

Page 169: ...MFRn PMOD PMPUP PMPDN PMIE PM0 After reset 0 0 0 0 0 0 Input Port Input 0 1 0 0 1 0 1 0 1 1 Output Port Output 0 1 1 0 1 0 1 0 1 0 X1 Input FT5 0 1 0 0 0 0 0 PM1 After reset 0 0 0 0 0 0 Input Port Input 0 1 0 0 1 0 1 0 1 1 Output Port Output 0 1 1 0 1 0 1 0 1 0 X2 Output FT5 0 1 1 0 0 0 0 TMPM3V6 M3V4 Page 147 2019 02 06 ...

Page 170: ... 0 0 1 0 1 0 1 0 PN3 After reset 0 0 0 0 0 0 0 Input Port Input 0 1 0 0 0 1 0 1 0 1 1 Output Port Output 0 1 1 0 0 1 0 1 0 1 0 PN4 After reset 0 0 0 0 0 0 0 Input Port Input 0 1 0 0 0 1 0 1 0 1 1 Output Port Output 0 1 1 0 0 1 0 1 0 1 0 PN5 After reset 0 0 0 0 0 0 0 Input Port Input 0 0 0 0 1 0 1 0 1 1 Output Port Output 0 1 0 0 1 0 1 0 1 0 PN6 After reset 0 0 0 0 0 0 0 Input Port Input 0 0 0 0 1 ...

Page 171: ...FRn PPOD PPPUP PPPDN PPIE PP0 After reset 0 0 0 0 0 0 Input Port Input 0 1 0 0 1 0 1 0 1 1 Output Port Output 0 1 1 0 1 0 1 0 1 0 XT1 Input FT5 0 1 0 0 0 0 0 PP1 After reset 0 0 0 0 0 0 Input Port Input 0 1 0 0 1 0 1 0 1 1 Output Port Output 0 1 1 0 1 0 1 0 1 0 XT2 Output FT5 0 1 1 0 0 0 0 TMPM3V6 M3V4 Page 149 2019 02 06 ...

Page 172: ...n the Block diagrams of ports 9 2 1 Type FT1 PxPUP Pull up Control PxPDN Pull down Control PxOD Open Drain Control PxIE Input Control RESET I O Port Drive Disable in STOP Mode Port Read 0 1 Internal Data Bus PxCR Output Control PxFRn Function Control PxDATA Output Latch Function Output Function Input 1 0 Power On Reset Figure 9 1 Port Type FT1 TMPM3V6 M3V4 9 Input Output port 9 2 Block Diagrams of...

Page 173: ... PxIE Input Control I O Port Drive Disable in STOP Mode 0 1 Internal Data Bus PxCR Output Control PxFRn Function Control PxDATA Output Latch Function Output Function Input 1 0 Function Output Enable 0 1 Port Read Power On Reset Figure 9 2 Port Type FT2 TMPM3V6 M3V4 Page 151 2019 02 06 ...

Page 174: ... O Port Drive Disable in STOP Mode 0 1 Internal Data Bus PxCR Output Control PxFRn Function Control PxDATA Output Latch Function Output Function Input 1 0 Function Output Enable 0 1 Port Read Power On Reset Figure 9 3 Port Type FT3 TMPM3V6 M3V4 9 Input Output port 9 2 Block Diagrams of Ports Page 152 2019 02 06 ...

Page 175: ...in Control PxIE Input Control RESET I O Port Drive Disable in STOP Mode 0 1 Internal Data Bus PxCR Output Control PxFRn Function Control PxDATA Output Latch Function Input Noise Filter 30ns Typ Port Read Power On Reset Figure 9 4 Port Type FT4 TMPM3V6 M3V4 Page 153 2019 02 06 ...

Page 176: ...Drain Control PxIE Input Control RESET I O Port Drive Disable in STOP Mode 0 1 Internal Data Bus PxCR Output Control PxDATA Output Latch AINn Port Read Power On Reset Figure 9 5 Port Type FT5 TMPM3V6 M3V4 9 Input Output port 9 2 Block Diagrams of Ports Page 154 2019 02 06 ...

Page 177: ...ontrol PxPDN Pull down Control PxOD Open Drain Control RESET I O Port Drive Disable in STOP Mode Internal Data Bus PxCR Output Control PxDATA Output Latch BOOT Power On Reset Figure 9 6 Port Type FT6 TMPM3V6 M3V4 Page 155 2019 02 06 ...

Page 178: ...TMPM3V6 M3V4 9 Input Output port 9 2 Block Diagrams of Ports Page 156 2019 02 06 ...

Page 179: ...neration mode PPG External trigger programmable pulse generation mode PPG Timer synchronous mode The use of the capture function allows TMRB to perform the following three measurements One shot pulse output by an external trigger Frequency measurement Pulse width measurement In the following explanation of this section x indicates a channel number TMPM3V6 M3V4 Page 157 2019 02 06 ...

Page 180: ...tion Table 10 1 Differences in the Specifications of TMRB Modules Specifica tion External pins Trigger function between timers Interrupt Internal Connects Channel External clock capture trigger in put pins Timer Flip Flop output pins Capture trigger Synchro nous start trigger channel Capture interrupt TMRB interrupt Start AD conversion Timer Flip Flop Connect with SIO UART RMC TXTRG Transfer clock...

Page 181: ...l Register buffer1 Match detect Timer flip flop control Capture Interrupt INTCAPx1 TBxCR TBWBF Interrupt mask register TBxIM Capture Interrupt INTCAPx0 Comparator CP0 Comparator CP1 16 bit up counter UC Capture register1 TBxCP1 Capture register0 TBxCP0 Up counter Capture register TBxUC Prescaler Up counter control Synchronous start trigger input Synchronous start trigger output Run clear TBxOUT St...

Page 182: ...r TBxEN 0x0000 RUN register TBxRUN 0x0004 Control register TBxCR 0x0008 Mode register TBxMOD 0x000C Flip flop control register TBxFFCR 0x0010 Status register TBxST 0x0014 Interrupt mask register TBxIM 0x0018 Up counter capture register TBxUC 0x001C Timer register 0 TBxRG0 0x0020 Timer register 1 TBxRG1 0x0024 Capture register 0 TBxCP0 0x0028 Capture register 1 TBxCP1 0x002C TMPM3V6 M3V4 10 16 bit ...

Page 183: ...disabled no clock is supplied to the other registers in the TMRB module This can reduce power consumption This disables reading from and writing to the oth er registers except TBxEN register To use the TMRB enable the TMRB operation set to 1 before programming each register in the TMRB module If the TMRB operation is executed and then disabled the settings will be maintained in each register 6 TBH...

Page 184: ...it symbol TBPRUN TBRUN After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31 3 R Read as 0 2 TBPRUN R W Prescaler operation 0 Stop clear 1 Count 1 R Read as 0 0 TBRUN R W Count operation 0 Stop clear 1 Count Note When the counter is stopped TBRUN 0 and TBxUC TBUC 15 0 is read the value which was captured when the counter was operated is read TMPM3V6 M3V4 10 16 bit Timer Event Counters TMRB 1...

Page 185: ...0 0 0 Bit Bit Symbol Type Function 31 8 R Read as 0 7 TBWBF R W Double buffer 0 Disable 1 Enable 6 R W Write as 0 5 TBSYNC R W Synchronous mode switching 0 individual unit of channel 1 synchronous 4 R Read as 0 3 I2TB R W Operation at IDLE mode 0 Stop 1 Operation 2 R Read as 0 1 TRGSEL R W Select external trigger 0 Rising edge 1 Falling edge Select the edge of the external trigger Signal to TBxIN ...

Page 186: ...le 01 TBxIN Takes count values into capture register 0 TBxCP0 upon rising of TBxIN pin input 10 TBxIN TBxIN Takes count values into capture register 0 TBxCP0 upon rising of TBxIN pin input Takes count values into capture register 1 TBxCP1 upon falling of TBxIN pin input 11 TBxOUT TBxOUT Takes count values into capture register 0 TBnCP0 upon rising of 16 bit timer match output TBxOUT and into captu...

Page 187: ...ter value is taken into the TBxCP0 0 Disable trigger 1 Enable trigger By setting 1 the timer flip flop reverses when the up counter value is taken into the Capture register 0 TBxCP0 3 TBE1T1 R W TBxFF0 reverse trigger when the up counter value is matched with TBxRG1 0 Disable trigger 1 Enable trigger By setting 1 the timer flip flop reverses when the up counter value is matched with the Timer regi...

Page 188: ...1 is set 1 INTTB1 R Match flag TBxRG1 0 No detection of a match 1 Detects a match with TBxRG1 When a match with the timer register 1 TBxRG1 is detected 1 is set 0 INTTB0 R Match flag TBxRG0 0 No match is detected 1 Detects a match with TBxRG0 When a match with the timer register 0 TBxRG0 is detected 1 is set Note 1 The factors only which is not masked by TBxIM output interrupt request to the CPU E...

Page 189: ... Type Function 31 3 R Read as 0 2 TBIMOF R W Overflow interrupt mask 0 Disable 1 Enable Sets the up counter overflow interrupt to disable or enable 1 TBIM1 R W Match interrupt mask TBxRG1 0 Disable 1 Enable Sets the match interrupt mask with the Timer register 1 TBxRG1 to enable or disable 0 TBIM0 R W Match interrupt mask TBxRG0 0 Disable 1 Enable Sets the match interrupt mask with the Timer regis...

Page 190: ... 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol TBUC After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31 16 R Read as 0 15 0 TBUC 15 0 R Captures a value by reading up counter out If TBxUC is read current up counter value can be captured Note When the counter is operated and TBxUC is read the value of the up counter is captured and read TMPM3V6 M3V4 10 16 bit Timer Event Counters TMRB 10 4 Registe...

Page 191: ...ction 31 16 R Read as 0 15 0 TBRG0 15 0 R W Sets a value comparing to the up counter 10 4 11 TBxRG1 Timer register 1 31 30 29 28 27 26 25 24 bit symbol After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol TBRG1 After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol TBRG1 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function ...

Page 192: ... TBCP0 15 0 R A value captured from the up counter is read 10 4 13 TBxCP1 Capture register 1 31 30 29 28 27 26 25 24 bit symbol After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol TBCP1 After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol TBCP1 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31 16 R Read as 0 15 0 T...

Page 193: ...ph 32 fc 26 1 6 μs fc 28 6 4 μs fc 210 25 6 μs 100 fc 2 000 fperiph 1 fc 22 0 1 μs fc 24 0 4 μs fc 26 1 6 μs 001 fperiph 2 fc 23 0 2 μs fc 25 0 8 μs fc 27 3 2 μs 010 fperiph 4 fc 24 0 4 μs fc 26 1 6 μs fc 28 6 4 μs 011 fperiph 8 fc 25 0 8 μs fc 27 3 2 μs fc 29 12 8 μs 100 fperiph 16 fc 26 1 6 μs fc 28 6 4 μs fc 210 25 6 μs 101 fperiph 32 fc 27 3 2 μs fc 29 12 8 μs fc 211 51 2 μs 101 fc 4 000 fperi...

Page 194: ... μs 100 fperiph 16 fc 25 0 8 μs fc 27 3 2 μs fc 29 12 8 μs 101 fperiph 32 fc 26 1 6 μs fc 28 6 4 μs fc 210 25 6 μs 110 fc 8 000 fperiph 1 fc 25 0 8 μs 001 fperiph 2 fc 24 0 4 μs fc 26 1 6 μs 010 fperiph 4 fc 25 0 8 μs fc 27 3 2 μs 011 fperiph 8 fc 24 0 4 μs fc 26 1 6 μs fc 28 6 4 μs 100 fperiph 16 fc 25 0 8 μs fc 27 3 2 μs fc 29 12 8 μs 101 fperiph 32 fc 26 1 6 μs fc 28 6 4 μs fc 210 25 6 μs 111 f...

Page 195: ...egisters TBxRG0 TBxRG1 TBxRG0 and TBxRG1 are registers for setting values to compare with up counter values and two registers are built into each channel If the comparator detects a match between a value set in this timer register and that in a UC up counter it outputs the match detection signal TBxRG0 and TBxRG1 are consisted of the double buffered configuration which are paired with register buf...

Page 196: ... is a match or not If a match is detected INTTBx0 and INTTBx1 are generated 10 5 8 Timer Flip flop TBxFF0 The timer flip flop TBxFF0 is reversed by a match signal from the comparator and a latch signal to the cap ture registers It can be enabled or disabled to reverse by setting the TBxFFCR TBC1T1 TBC0T1 TBE1T1 TBE0T1 The value of TBxFF0 becomes undefined after a reset The flip flop can be reverse...

Page 197: ... capture function to disable 01 10 11 TBxRG1 Specifies a time interval 16 bits TBxRUN 1 X 1 Starts TMRBx Note X Don t care No change 10 6 2 16 bit Event Counter Mode It is possible to make it the event counter by using an input clock as an external clock TBxIN pin input The up counter counts up on the rising edge of TBxIN pin input It is possible to read the count value by cap turing value using s...

Page 198: ...xRG1 TBxOUT pin Match with TBxRG0 INTTBx0 interrupt Match with TBxRG1 INTTBx1 interrupt Figure 10 2 Example of Output of Programmable Pulse Generation PPG In this mode by enabling the double buffering of TBxRG0 the value of register buffer 0 is shifted into TBxRG0 when the set value of the up counter matches the set value of TBxRG1 This facilitates handling of small duties Q2 Q1 Match with TBxRG1 ...

Page 199: ...X X 0 X 0 Stops count operation TBxCR 0 0 X X 0 0 Disable double buffering TBxRG0 Specifies a duty 16 bits TBxRG1 Specifies a cycle 16 bits TBxCR 1 0 X 0 0 0 0 0 TBxFFCR X X 0 0 1 1 1 0 Enables the TBxRG0 TBxRG1 double buffering Changes the duty cycle when the INTTBx interrupt is gener ated Specifies to trigger TBxFF0 to reverse when a match with TBxRG0 or TBxRG1 is detected and sets the initial v...

Page 200: ...e the count up on the rising edge of external trigger 4 After the generation of one shot pulse on the rising edge of TBxIN pin set a reverse of the timer flip flop TBxFF0 to disable with the interrupt of INTTBx1 or set 0 to TBxRUN TBRUN to clear the value and stop the 16 bit up counter operation The symbols d and p in the above description corresponds to the symbol d and p in the following figure ...

Page 201: ...2 TMRB3 TMRB4 TMRB5 TMRB6 TMRB7 Use of the timer synchronous mode is specified in TBxCR TBSYNC bit TBSYNC 0 Timer operates individually TBSYNC 1 Timers operates synchronously Set 0 to the TBSYNC bit in the master channel If TBSYNC 1 is set in the slave channel the start timing is synchronized with master channel start tim ing Setting of start timing for TBxRUN TBPRUN TBRUN bit in the slave channel...

Page 202: ...nd the delay time d c d and set the timer registers TBxRG1 to the sum of the TBxRG0 values and the pulse width p of one shot pulse c d p TBxRG1 change must be completed before the next match In addition the timer flip flop control registers TBxFFCR TBE1T1 TBE0T1 must be set to 11 This en ables triggering the timer flip flop TBxFF0 to reverse when UC matches TBxRG0 and TBxRG1 This trig ger is disab...

Page 203: ...terrupt Interrupt Set Enable Register Permits to generate interrupt specified by INTTBx interrupt corresponding bit setting to 1 Processing of INTTBx interrupt service routine Output disable TBxFFCR X X 0 0 Clears TBxFF0 reverse trigger setting Interrupt enable clear register Prohibits interrupts specified by INTTBx interrupt correspond ing bit by setting to 1 Note 1 m corresponding bit of port No...

Page 204: ...s 200 Hz 100 0 5 s 200 Hz Count clock TB0IN pin input Taking data into TB0CP1 TB7OUT Taking data into TB0CP0 C1 C1 C1 C2 C2 C2 INTTB70 INTTB71 Figure 10 8 Frequency Measurement 10 7 3 Pulse width measurement By using the capture function the High level width of an external pulse can be measured Specifically by putting it in a free running state using the prescaler output clock an external pulse is...

Page 205: ...ond stage of INTCAPx0 interrupt processing as shown in Figure 10 9 Pulse Width Measurement and this differ ence is multiplied by the cycle of the prescaler output clock to obtain the Low level width 3UHVFDOHU RXWSXW FORFN Taking data into TBxCP1 TBxIN SLQ LQSXW H WHUQDO SXOVH Taking data into TBxCP0 C1 C1 C1 C2 C2 C2 INTCAPx1 INTCAPx0 Figure 10 9 Pulse Width Measurement TMPM3V6 M3V4 Page 183 2019 ...

Page 206: ...TMPM3V6 M3V4 10 16 bit Timer Event Counters TMRB 10 7 Applications using the Capture Function Page 184 2019 02 06 ...

Page 207: ...FIFO Transmission 8 bit width 32 deep reception 12 bit width 32 deep Enable disable decision possible Interrupt function Multiple interrupt event outputs Each interrupt can be enabled disabled Baud rate generator Transmit and receive common clock can be generated from fsys 50 duty mode Corresponding to the communication of the 50 duty signal 0 data can be output by distributing to the two terminal...

Page 208: ...aud rate generator Baud16 Control and status 8bit x 32 transmit FIFO Transmitter Receiver Receive FIFO Status Transmit FIFO status FIFO status and interrupt generation FIFO Flags INTUARTx 50 duty control UTxTXD UTxTXD50A UTxTXD50B UTxRXD UTxRXD50 fsys Figure 11 1 Block diagram of UART TMPM3V6 M3V4 11 Universal Asynchronous Receiver Transmitter Circuit UART 11 2 Structure Page 186 2019 02 06 ...

Page 209: ... UARTxFBRD 0x0028 Line control register UARTxLCR_H 0x002C Control register UARTxCR 0x0030 interrupt FIFO level select register UARTxIFLS 0x0034 Interrupt mask set clear register UARTxIMSC 0x0038 Raw interrupt status register UARTxRIS 0x003C Masked interrupt status register UARTxMIS 0x0040 Interrupt clear register UARTxICR 0x0044 Reserved 0x0048 50 duty control register UARTxHCCR 0x0050 Reserved 0x...

Page 210: ...s set to 1 If the FIFO is enabled this error is stored at the top of the FIFO If a break error occurs 0 is stored in the FIFO as data Next data reception is enabled after the UTxRXD input is 1 marking state and the start bit is received 9 PE R Parity error 0 No error 1 Error When this bit is set to 1 this indicates that a received data parity does not match the parity programmed with UARTxLCR_H EP...

Page 211: ...ared to 0 by writing data to UARTxECR If FIFO is enabled this error is input to the top of the FIFO If a break error occurs 0 is input to FIFO as data In the next data reception UTxRXD input is set to 1 marking status this bit is enabled after a start bit is received 1 PE R Parity error 0 No error 1 Error When this bit is 1 this indicates that the parity of received data does not match the parity ...

Page 212: ...mbol OE BE PE FE After reset 0 0 0 0 0 0 0 0 Bit Bit symbol Type Function 31 4 R Read as 0 3 OE W When data is written to UARTxECR each framing parity break and overrun errors are cleared This clear ing is executed regard less of the data value The address of this register is the same as those of the UARTxSR register 2 BE W 1 PE W 0 FE W TMPM3V6 M3V4 11 Universal Asynchronous Receiver Transmitter ...

Page 213: ...IFO is full When UARTxLCR_H FEN 0 0 The receive hold register is not full 1 The receive hold register is full 5 TXFF R When UARTxLCR_H FEN 1 0 The transmit FIFO is not full 1 The transmit FIFO is full When UARTxLCR_H FEN 0 0 The transmit hold register is not full 1 The transmit hold register is full 4 RXFE R When UARTxLCR_H FEN 1 0 The receive FIFO is not empty 1 The receive FIFO is empty When UAR...

Page 214: ...value written to UARTxIBRD will be valid upon currently ongoing transmission or reception is complete Note 2 The value written to UARTxIBRD will be valid when data is written to UARTxLCR_H Note 3 Set BAUDDIVINT 15 0 before UARTxCR UARTEN is set to 1 Note 4 0x0000 0x0001 cannot be set Note 5 The value of the worst case baud rate divisor of the set value due to the baud rate shift total error betwee...

Page 215: ...to 0x3F The fractional part of a baud rate divisor value Note 1 The value written to UARTxFBRD will be valid upon currently ongoing transmission or reception is complete Note 2 The value written to UARTxFBRD will be valid when data is written to UARTxLCR_H Note 3 Set BAUDDIVFRAC 5 0 before 1 is set to UARTxCR UARTEN Note 4 The minimum value of a baud rate divisor is 1 and the maximum value is 6553...

Page 216: ...e FIFO is enabled 3 STP2 R W Selects a transmission stop bit length 0 1 bit 1 2 bits In reception a 2 bit length stop bit is not checked 2 EPS R W Even parity selection 0 Odd parity 1 Even parity Controls a parity bit in transmission reception When PEN is set to 0 if parity check and generation are disabled this bit has no meaning 1 PEN R W Parity enable 0 Disabled Parity is disabled A parity bit ...

Page 217: ...ion SPS Parity selection Transmission or check 0 No transmission and check 1 1 0 Even parity transmission or even parity re ception 1 0 0 Odd parity transmission or odd parity re ception 1 0 1 1 is sent received as a parity bit 1 1 1 0 is sent received as a parity bit Note X don t care TMPM3V6 M3V4 Page 195 2019 02 06 ...

Page 218: ...reception is disabled during the reception reception stops after currently ongoing data reception is complete 8 TXE R W Enables disables the transmission 0 Disabled 1 Enabled When TXE is set to 1 transmission is enabled If transmission is disabled during transmission transmis sion stops after currently ongoing transmission is complete 7 R W Write as 0 6 3 R Read as an undefined value 2 R W Write a...

Page 219: ...ener ated when the transition is made through the specified FIFO level For example if the FIFO level is set to full of 1 8 4 bytes when the 4th byte data is stored in the receive FIFO an interrupt occurs after a STOP bit is received 2 0 TXIFLSEL 2 0 R W Selects the transmission interrupt FIFO level 000 The transmit FIFO full of 1 8 001 The transmit FIFO full of 1 4 010 The transmit FIFO full of 1 ...

Page 220: ...lue 10 OEIM R W Overrun error interrupt mask 0 Disabled 1 Enabled 9 BEIM R W Break error interrupt mask 0 Disabled 1 Enabled 8 PEIM R W Parity error interrupt mask 0 Disabled 1 Enabled 7 FEIM R W Framing error interrupt mask 0 Disabled 1 Enabled 6 RTIM R W Receive timeout interrupt mask 0 Disabled 1 Enabled 5 TXIM R W Transmit interrupt mask 0 Disabled 1 Enabled 4 RXIM R W Receive interrupt mask 0...

Page 221: ...t is requested 9 BERIS R Break error interrupt status 0 No interrupt request 1 An interrupt is requested 8 PERIS R Parity error interrupt status 0 No interrupt request 1 An interrupt is requested 7 FERIS R Framing error interrupt status 0 No interrupt request 1 An interrupt is requested 6 RTRIS R Receive time out interrupt status 0 No interrupt request 1 An interrupt is requested 5 TXRIS R Transmi...

Page 222: ...pt status 0 No interrupt request 1 An interrupt is requested 8 PEMIS R Parity error mask interrupt status 0 No interrupt request 1 An interrupt is requested 7 FEMIS R Framing error mask interrupt status 0 No interrupt request 1 An interrupt is requested 6 RTMIS R Receive time out mask interrupt status 0 No interrupt request 1 An interrupt is requested 5 TXMIS R Transmit mask interrupt status 0 No ...

Page 223: ...0 Invalid 1 Clear 9 BEIC W Break error interrupt clear 0 Invalid 1 Clear 8 PEIC W Parity error interrupt clear 0 Invalid 1 Clear 7 FEIC W Framing error interrupt clear 0 Invalid 1 Clear 6 RTIC W Receive time out interrupt clear 0 Invalid 1 Clear 5 TXIC W Transmit interrupt clear 0 Invalid 1 Clear 4 RXIC W Receive interrupt clear 0 Invalid 1 Clear 3 W Write as 0 2 W Write as 0 1 W Write as 0 0 W Wr...

Page 224: ...han 0 detection 010 2 16 width more than 0 detection 011 3 16 width more than 0 detection 100 4 16 width more than 0 detection 101 5 16 width more than 0 detection 110 6 16 width more than 0 detection 111 7 16 width more than 0 detection 3 R W Write as 0 2 HCST R W Terminal selection to start the start bit 0 UTxTXD50A 1 UTxTXD50B 1 HCMD R W Transmission terminal mode selection 0 1 terminal mode 1 ...

Page 225: ...k Error Parity Error Framing Error Receive data Receive data 7 bits Overrun Error Break Error Parity Error Framing Error Receive data Receive data 6 bits Overrun Error Break Error Parity Error Framing Error Receive data Receive data 5 bits Overrun Error Break Error Parity Error Framing Error Receive data Note Empty bits in the receive data are undefined 11 4 2 Transmit Data and Receive data Data w...

Page 226: ...elow the decimal point are omitted Generated baud rate divisor is calculated using the above integer part and fractional part as below BAUDDIV 1 5 64 1 078 At this time generated baud rate is calculated as follows Generated baud rate 4 106 16 1 078 231911 A margin of error 231911 230400 230400 100 0 656 In addition the maximum margin of error is 1 64 100 1 56 when the UARTxFBRD register is used Th...

Page 227: ... the corresponding interrupt clear register Interruptpriortomasking Interruptaftermasking Interruptmasksignal Interruptrequestflag UARTCLK F F 2 Generation circuit for overrun error flag An interrupt request flag changes with overrun errors in real time The register status is not maintained An overrun flag is cleared by reading the receive FIFO Interruptpriortomasking Interruptaftermasking Interru...

Page 228: ...11 clocks of Baud16 has elapsed Transmission interrupt When the FIFO is unused After the transmission is enabled when a START bit and STOP bit in the first byte of the transmission data are sent a transmit inter rupt occurs In the second byte and the following byte a transmit inter rupt occurs only when a STOP bit is sent In this case each interrupt is cleared after the transmit data is writ ten W...

Page 229: ...l circuit is enabled and the UART en ters the 50 duty mode Duty conversion is performed on transmission reception signals in the 50 duty control circuit Port pin functions can select whether duty conversion is performed on the signal Figure 11 1 shows the circuit configuration Note Do not modify the UARTxHCCR register during the communication 11 4 7 3 Operational Description 1 Transmission a 1 pin...

Page 230: ... duty 0 1 1 0 1 0 1 1 0 1 1 0 0 0 0 Start bit Stop bit Parity bit Data bit UTxRXD50 UTxRXD Figure 11 5 Example of waveforms in reception 3 Selection of the start bit pin A start bit can be selected either from UTxTXD50A or UTxTXD50B with UARTxHCCR HCST in 2 pin transmission mode Figure 11 6 shows an example where the start bit is set to UTxTXD50B Figure 11 4 shows an example where the start bit is...

Page 231: ...e width of UARTCLK Width of 3 16 Not recognized as 0 Figure 11 7 Example of data 0 detection period 5 The loop back test control When 1 is set to UARTxHCCR HCLPB the loop back test control is enabled At this time UTxTXD50A and UTxTXD50B are internally connected to UTxRXD50 therefore TMPM3V6 M3V4 can singly check transmit receive operation UTxTXD50A and UTxTXD50B are ANDed The result is sent to UTx...

Page 232: ...TMPM3V6 M3V4 11 Universal Asynchronous Receiver Transmitter Circuit UART 11 4 Operation Description Page 210 2019 02 06 ...

Page 233: ...e usable 4 byte FIFO including transmit and receive I O Interface Mode Transfer Mode the half duplex transmit receive the full duplex Clock Output fixed rising edge Input selectable either rising or falling edge Make it possible to specify the interval time of continuous transmission The state of TXDx pin after output of the last bit can be selected as follow Keep a High level Low level or the sta...

Page 234: ...fer SCxBUF RB8 Receive buffer SCxBUF Parity control Error flag Internal data bus Internal data bus Internal data bus FIFO control FIFO control Noise canceller Figure 12 1 Serial Channel Block Diagram ȭT0 ȭTS0 ȭTS2 ȭTS8 ȭTS32 ȭTS2 SC BRCR BRCK TBxOUT from TMRBx SCxBRCR BRADDE SCxCR IOC SIOCLK SCxMOD0 SC SCxMOD0 SM SCxBRCR BRS SCxBRADD BRK SCLKx SLQ 2 2 4 8 16 32 64 ȭTS8 ȭTS32 SCxEN BRCKSEL ȭTS0 2 B...

Page 235: ...0 SCxMOD0 0x000C Baud rate generator control register SCxBRCR 0x0010 Baud rate generator control register 2 SCxBRADD 0x0014 Mode control register 1 SCxMOD1 0x0018 Mode control register 2 SCxMOD2 0x001C Receive FIFO configuration register SCxRFC 0x0020 Transmit FIFO configuration register SCxTFC 0x0024 Receive FIFO status register SCxRST 0x0028 Transmit FIFO status register SCxTST 0x002C FIFO confi...

Page 236: ...R W Selects input clock for prescaler 0 φT0 2 1 φT0 0 SIOE R W Serial channel operation 0 Disabled 1 Enabled Specified the Serial channel operation To use the Serial channel set SIOE 1 When the operation is disabled no clock is supplied to the other registers in the Serial channel module This can reduce the power consumption If the Serial channel operation is executed and then disabled the setting...

Page 237: ...l After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol TB RB After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31 8 R Read as 0 7 0 TB 7 0 RB 7 0 R W write TB Transmit buffer or FIFO read RB Receive buffer or FIFO TMPM3V6 M3V4 Page 215 2019 02 06 ...

Page 238: ...O interface mode 0 Low level output 1 High level output 9 8 TIDLE 1 0 R W The state of TXDx pin after output of the last bit For only I O interface mode When TIDLE 1 0 is set to 10 set 000 to EHOLD 2 0 00 Keep a Low level output 01 Keep a High level output 10 Keep a last bit 11 Reserved 7 RB8 R Receive data bit 8 For only UART mode 9th bit of the received data in the 9 bit UART mode 6 EVEN R W Par...

Page 239: ...Dx pin starts from High level Rising edge mode 1 Data in the transmit buffer is sent to TXDx pin every one bit on the rising edge of SCLKx pin Data from RXDx pin is received in the receive buffer every one bit on the falling edge of SCLKx pin In this case the state of a SCLKx starts from Low level 0 IOC R W Selecting clock For I O Interface mode 0 Clock output mode A transfer clock is output from ...

Page 240: ...Enabled 4 WU R W Wake up function For only UART mode 0 Disabled 1 Enabled This function is available only at 9 bit UART mode In other mode this function has no meaning When it is enabled interrupt is occurred only when RB9 1 in a 9 bit UART mode 3 2 SM 1 0 R W Specifies transfer mode 00 I O interface mode 01 7 bit UART mode 10 8 bit UART mode 11 9 bit UART mode 1 0 SC 1 0 R W Serial transfer clock...

Page 241: ...pecify the only configura tion of FIFO 4 TXE R W Transmit control Note1 Note2 0 Disabled 1 Enabled This bit enables transmission and is valid for all the transfer modes 3 1 SINT 2 0 R W Interval time of continuous transmission For I O interface mode 000 None 001 1 x SCLK cycle 010 2 x SCLK cycle 011 4 x SCLK cycle 100 8 x SCLK cycle 101 16 x SCLK cycle 110 32 x SCLK cycle 111 64 x SCLK cycle This ...

Page 242: ...ouble buffers this bit changes to 1 When reading the receive buffer this bit is cleared to 0 5 TXRUN R In transmission flag 0 Stop 1 Operate This is a status flag to show that data transmission is in progress TXRUN and TBEMP bits indicate the following status TXRUN TBEMP Status 1 Transmission in progress 0 1 Transmission is completed 0 Wait state with data in transmit buffer 4 SBLEN R W STOP bit l...

Page 243: ...and FIFO become initial state Note1 Note2 Register Bit SCxMOD0 RXE SCxMOD1 TXE SCxMOD2 TBEMP RBFLL TXRUN SCxCR OERR PERR FERR Note 1 While data transmission is in progress any software reset operation must be executed twice in succession Note 2 A software reset requires 2 clocks duration at the time between the end of recognition and the start of execution of soft ware reset instruction TMPM3V6 M3...

Page 244: ...divider function Only for UART mode 0 disabled 1 enabled 5 4 BRCK 1 0 R W Select input clock to the baud rate generator 00 φTS0 01 φTS2 10 φTS8 11 φTS32 3 0 BRS 3 0 R W Division ratio N 0000 N 16 0001 N 1 0010 N 2 1111 N 15 Note 1 As a division ratio 1 0001 or 16 0000 can not be applied to N when using the N 16 K 16 division func tion in the UART mode Note 2 The division ratio 1 of the baud rate g...

Page 245: ... for the N 16 K 16 division For UART mode 0000 Prohibited 0001 K 1 0010 K 2 1111 K 15 Table 12 1 lists the settings of baud rate generator division ratio Table 12 1 Setting division ratio BRADDE 0 BRADDE 1 Note1 Only in the UART mode BRS Specify N BRK No setting required Specify K Note2 Division ratio Divide by N N 16 K 16 GLYLVLRQ Note 1 To use the N 16 K 16 division function be sure to set BRADD...

Page 246: ...rrupts are enabled or disabled by this parameter 1 RXTXCNT R W Automatic disable of RXE TXE 0 None 1 Auto disable Controls automatic disabling of transmission and reception Setting 1 enables to operate as follows Half duplex Receive When the receive shift register receive buffers and receive FIFO are filled up to the specified number of valid bytes SCxMOD0 RXE is automatically set to 0 to inhibit ...

Page 247: ...Note 1 Regarding Transmit FIFO the maximum number of bytes being configured is always available See also CNFG Note 2 The FIFO can not be used in 9 bit UART mode TMPM3V6 M3V4 Page 225 2019 02 06 ...

Page 248: ...t interrupt generation condition 0 When FIFO fill level SCxRST RLVL 2 0 Receive FIFO fill level to generate receive interrupt RIL 1 0 1 When FIFO fill level SCxRST RLVL 2 0 Receive FIFO fill level to generate receive interrupt RIL 1 0 For the detail of interrupt condition refer to 12 12 1 2 FIFO 5 2 R Read as 0 1 0 RIL 1 0 R W FIFO fill level to generate receive interrupts Half duplex Full duplex ...

Page 249: ...ondition 0 When FIFO fill level SCxTST TLVL 2 0 Transmit FIFO fill level to generate transmit interrupt TIL 1 0 1 When FIFO fill level SCxTST TLVL 2 0 Transmit FIFO fill level to generate transmit interrupt TIL 1 0 For the detail of interrupt condition refer to 12 12 2 2 FIFO 5 2 R Read as 0 1 0 TIL 1 0 R W Fill level which transmit interrupt is occurred Half duplex Full duplex 00 Empty Empty 01 1...

Page 250: ...bit symbol ROR RLVL After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31 8 R Read as 0 7 ROR R Receive FIFO Overrun Note 0 Not generated 1 Generated 6 3 R Read as 0 2 0 RLVL 2 0 R Status of Receive FIFO fill level 000 Empty 001 1 byte 010 2 bytes 011 3 bytes 100 4 bytes Note ROR is cleared to 0 when receive data is read from the SCxBUF TMPM3V6 M3V4 12 Serial Channel with 4bytes FIFO SIO UAR...

Page 251: ...eset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol TUR TLVL After reset 1 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31 8 R Read as 0 7 TUR R Transmit FIFO Under run Note 0 Not generated 1 Generated 6 3 R Read as 0 2 0 TLVL 2 0 R Status of Transmit FIFO level 000 Empty 001 1 byte 010 2 byte 011 3 byte 100 4 byte Note TUR is cleared to 0 when transmit data is written to the SCxBUF TMPM3V6 M3V4 Page 22...

Page 252: ...K clock can be used for both input and output modes The direc tion of data transfer can be selected from LSB first or MSB first This mode is not allowed either to use parity bits or STOP bits The mode 1 mode 2 and mode 3 are asynchronous modes and the transfer directions can be selected as only the LSB first Parity bits can be added in the mode 1 and mode 2 The mode 3 has a wakeup function in whic...

Page 253: ...Without parity bit 0 1 2 3 4 5 6 7 parity stop start With parity stop bit 0 1 2 3 4 5 6 start 7 8 bit 0 1 2 3 4 5 6 7 bit 8 stop Wake up start Mode3 9bits UART mode bit 8 1 represents address select code bit 8 0 represents data 1 bit 0 2 3 4 5 6 Mode0 I O interface mode LSB first Transmission direction 7 6 bit 7 5 4 3 2 1 Mode0 I O interface mode MSB first Transmission direction 0 Figure 12 3 Data...

Page 254: ...Reception If the received data is moved from the receive shift register to the receive buffer a parity is generated In the 7 bit UART mode the generated parity is compared with the parity stored in SCxBUF RB 7 in the 8 bit UART mode it is compared with the one in SCxCR RB8 If there is any difference a parity error occurs and the SCxCR PERR is set to 1 In use of the FIFO PERR indicates that a parit...

Page 255: ...erator generates transmit and receive clocks to determine the serial channel transfer rate 1 Baud Rate Generator input clock The input clock of the baud rate generator is selected from the prescaler outputs divided by 1 4 16 and 64 This input clock is selected by setting the SCxEN BRCKSEL and SCxBRCR BRCK SCxEN BRCKSEL SCxBRCR BRCK Baud rate generator input clock φTx 0 00 φT0 2 0 01 φT0 8 0 10 φT0...

Page 256: ...to 15 1 to 15 Note 1 N N 1 frequency division ratio can be used only when a double buffer is enabled The input clock to the divider of baud rate generator is φTx the baud rate in the case of 1 N and N 16 K 16 is shown below Divide by N ǾTx CWF TCVG N N 16 K 16 division ȭTx DXG UDWH N 16 K 16 TMPM3V6 M3V4 12 Serial Channel with 4bytes FIFO SIO UART 12 6 Clock Control Page 234 2019 02 06 ...

Page 257: ...ck Selection in I O Interface Mode Mode SCxMOD0 SM 1 0 Input Output selection SCxCR IOC Clock edge selection SCxCR SCLKS Clock of use 00 I O interface mode 0 Clock output mode 0 Transmit falling edge Receive rising edge Divided by 2 of the baud rate generator output 1 Clock input mode 0 Transmit falling edge Receive rising edge SCLKx pin input 1 Transmit rising edge Receive falling edge SCLKx pin ...

Page 258: ... conditions must be satisfied SCLK cycle 2 fsys To enable the timer output a timer flip flop output inverts when the value of the counter and that of TBxRG1 match The SIOCLK clock frequency is Setting value of TBxRG1 2 Baud rates can be obtained by using the following formula Baud rate calculation Transfer rate Clock frequency selected by CGSYSCR PRCK 1 0 TBxRG1 2 2 16 In the case the tim er presc...

Page 259: ...nsmit Receive Buffer Transmit buffer and receive buffer are double buffered The buffer configuration is specified by SCxMOD2 WBUF When serial channel is operated as receive if it is operated as clock input mode in the I O interface mode or it is operated as the UART mode it s double buffered regardless of WBUF settings In other modes it s according to the WBUF settings Table 12 5 shows correlation...

Page 260: ...2 TBEMP is set to 1 Note In the I O interface mode with clock input mode is input asynchronously When transmit operation is stopped do not input the clock 12 6 3 4 FIFO In addition to the double buffer function above described 4 byte FIFO can be used To enable FIFO enable the double buffer by setting SCxMOD2 WBUF to 1 and SCxFCNF CNFG to 1 The FIFO buffer configuration is specified by SCxMOD1 FDPX...

Page 261: ...ading the SCxCR Mode Flag OERR PERR FERR UART mode Over run error Parity error Framing error I O Interface mode Clock input mode Over run error Under run error When a double buffer and FIFO are used Fixed to 0 Fixed to 0 When a double buffer and FIFO are not used I O Interface mode Clock output mode Undefined Undefined Fixed to 0 12 8 1 OERR Flag In both UART and I O interface modes this bit is se...

Page 262: ...it shift register with no data in the transmit buffer In the clock output mode PERR is set to 1 after completing output of all data and the clock output stops Note To switch from the I O interface mode with clock output mode to other modes read the SCxCR and clear the under run flag 12 8 3 FERR Flag A framing error is generated if the corresponding stop bit is determined to be 0 by sampling the bi...

Page 263: ...l unit has a start bit detection circuit which is used to initiate receive operation when a normal start bit is detected 12 9 3 Receive Operation 12 9 3 1 Receive Buffer The received data is stored by 1 bit in the receive shift register When a complete set of bits has been stor ed the interrupt INTRXx is generated When the double buffer is enabled the data is moved to the receive buffer SCxBUF and...

Page 264: ...XCNT CNFG 10111 SCxRFC RIL 1 0 00 SCxRFC RFCS RFIS 01 Clears receive FIFO and sets the condition of interrupt generation After setting of the above FIFO configuration the data reception is started by writing 1 to the SCxMOD0 RXE When the data is stored all in the receive shift register receive buffer and receive FIFO SCxMOD0 RXE is automatically cleared and the receive operations completed In the ...

Page 265: ...and shake When the data in a buffer is read clock output is restarted 2 Case of double buffer Stop clock output after receiving the data into a receive shift register and a receive buffer When a data is read clock output is restarted 3 Case of FIFO Stop clock output after receiving the data into a shift register received buffer and FIFO When one byte data is read the data in the received buffer is...

Page 266: ...n the wake up mode by setting the wake up function SCxMOD0 WU to 1 In this case the interrupt INTRXx will be generated only when SCxCR RB8 is set to 1 12 9 3 6 Overrun Error When receive FIFO is disabled the overrun error occurs without completing reading data before receiv ing the next data When an overrun error occurs a content of receive buffer and SCxCR RB8 is not lost but a content of receive...

Page 267: ...terface Mode In the clock output mode with SCxCR IOC set to 0 each bit of data in the transmit buffer is output ted to the TXDx pin on the falling edge of SCLKx pin In the clock input mode with SCxCR IOC set to 1 each bit of data in the transmit buffer is output ted to the TXDx pin on the rising or falling edge of the SCLKx pin according to the SCxCR SCLKS 12 10 2 2 In UART Mode When the transmit ...

Page 268: ...transmit shift register The INTTXx interrupt is generated at the same time and the transmit buffer empty flag SCxMOD2 TBEMP is set to 1 This flag indicates that the next transmit data can be written When the next data is written to the transmit buffer the TBEMP flag is cleared to 0 DATA 1 Transmit buffer SCxMOD2 TBEMP Transmit shift register INTTXx Write data DATA 2 DATA 1 Transmit shift register ...

Page 269: ... same as the interrupt generation fill level SCxTFC TIL 1 0 00 Sets the interrupt generation fill level to 0 SCxTFC TFCS TFIS 11 Clears receive FIFO and sets the condition of interrupt generation SCxFCNF CNFG 1 Enable FIFO After above settings are configured data transmission can be initiated by writing 5 bytes of data to the transmit buffer and FIFO and setting the SCxMOD1 TXE bit to 1 When the l...

Page 270: ... of all data stored in the transmit shift register transmit buffer and FIFO is comple ted the SCLK output stops The next data is written clock output resumes If SCxFCNF RXTXCNT is configured SCxMOD0 TXE bit is cleared at the same time as clock stops and the transmission stops 12 10 3 4 Level of TXDx pin after the last bit is output in I O interface mode The level of TXDx pin after the data hold ti...

Page 271: ...n SCxCR TIDLE 1 0 00 SCxCR TXDEMP 1 TXDx pin SCxCR TIDLE 1 0 01 SCxCR TXDEMP 0 TXDx pin SCxCR TIDLE 1 0 01 SCxCR TXDEMP 1 TXDx pin SCxCR TIDLE 1 0 10 SCxCR TXDEMP 0 TXDx pin SCxCR TIDLE 1 0 10 SCxCR TXDEMP 1 Figure 12 10 Level of TXDx pin when Under run Error is Occurred In the I O interface mode with SCLK output setting the clock output automatically stops so SCxCR PERR has no meaning Note Before...

Page 272: ...ext data transmission is suspended after the cur rent transmission is completed Note 2 Data transmission starts on the first falling edge of the TXDCLK clock after CTSx is set to Low level Although no RTS pin is provided a handshake control function can easily implemented by assigning one bit of the port for the RTS function By setting the port to High level upon completion of data reception in th...

Page 273: ...ve buffter Specific timings are If data does not exist in the receive buffer a receive interrupt occurs in the vicinity of the center of the 1st stop bit If data exists in both the receive shift regis ter and the receive buffer a receive interrupt occurs when the buffer is read A receive interrupt occurs when data is transferred from the receive shift regis ter to the receive buffer Specific timin...

Page 274: ...2 12 2 1 Singe Buffer Double Buffer Transmit interrupts are generated at the time depends on the transfer mode and the buffer configura tions which are given as follows Table 12 9 Transmit Interrupt conditions in use of Single Buffer Double Buffer Buffer Configurations UART modes IO interface modes Single Buffer Just before the stop bit is sent Immediately after the raising falling edge of the las...

Page 275: ...nerate transmit interrupt TIL 1 0 When transmit data is write into transmit FIFO 12 12 3 Error Generation 12 12 3 1 UART Mode Error 9 bits 7 bits 8 bits 7 bits Parity 8 bits Parity Framing Error over run Error Around the center of stop bit Parity Error Determination Around the center of parity bit Flag change Around the center of stop bit 12 12 3 2 I O Interface Mode over run Error Immediately aft...

Page 276: ...01 As a result SCxMOD0 RXE SCxMOD1 TXE SCxMOD2 TBEMP RBFLL TXRUN SCxCR OERR PERR FERR are initialized And the receive circuit and the transmit circuit become initial state Other states are maintained TMPM3V6 M3V4 12 Serial Channel with 4bytes FIFO SIO UART 12 13 Software Reset Page 254 2019 02 06 ...

Page 277: ...SCxMOD2 WBUF 0 Data is output from the TXDx pin and the clock is output from the SCLKx pin each time the CPU writes data to the transmit buffer When all data is output an interrupt INTTXx is generated If the transmit double buffer is enabled SCxMOD2 WBUF 1 Data is moved from the transmit buffer to the transmit shift register when the CPU writes data to the transmit buffer in the shift register is ...

Page 278: ...ata in buffer SCxCR TIDLE 01 bit 7 Figure 12 15 Transmit Operation in the I O Interface Mode Clock Output Mode TMPM3V6 M3V4 12 Serial Channel with 4bytes FIFO SIO UART 12 14 Operation in Each Mode Page 256 2019 02 06 Transmit data write timing SCLKx output TXDx INTTXx interrupt request Transmit data write timing SCLKx output TXDx INTTXx interrupt request SCxMOD2 TBEMP Transmit data write timing SC...

Page 279: ...SCxMOD2 WBUF 1 Data is moved from the transmit buffer to the transmit shift register when the CPU writes data to the transmit buffer before the clock input becomes active or when data trans mission from the transmit shift register is completed Simultaneously SCxMOD2 TBEMP is set to 1 and the INTTXx interrupt is generated If the clock input becomes active while no data is in the transmit buffer alt...

Page 280: ...g SCLKx input SCxCR SCLKS 1 Falling edge mode SCLKx input SCxCR SCLKS 0 Rising edge mode INTTXx interrupt request Transmit data write timing SCxMOD2 TBEMP INTTXx interrupt request Transmit data write timing SCxCR PERR Functions to detect under run errors TXDx SCLKx input SCxCR SCLKS 1 Falling edge mode SCLKx input SCxCR SCLKS 0 Rising edge mode TXDx SCLKx input SCxCR SCLKS 1 Falling edge mode SCLK...

Page 281: ...register is moved to the receive buffer and the receive buffer can receive the next frame A data is moved from the shift register to the receive buffer SCxMOD2 RBFLL is set to 1 and the INTRXx is generated When a data is in the receive buffer if the data is not read from the receive buffer be fore completing reception of the next 8 bits the INTRXx interrupt is not generated and the clock output st...

Page 282: ...t 0 WBUF 1 if double buffering is enabled and data is read from buffer bit 7 bit 7 SCxMOD2 RBFLL INTRXx interrupt request Receive data read timing SCxMOD2 RBFLL bit 0 bit 1 bit 6 WBUF 1 if double buffering is enabled and data cannot be read from buffer bit 7 bit 7 Figure 12 17 Receive Operation in the I O Interface Mode Clock Output Mode TMPM3V6 M3V4 12 Serial Channel with 4bytes FIFO SIO UART 12 ...

Page 283: ...t 1 bit 6 bit 5 bit 7 bit 0 If data is read from buffer bit 0 bit 1 bit 6 bit 5 bit 7 bit 0 If data cannot be read from buffer Receive data read timing SCLKx input SCxCR SCLKS 0 Rising mode SCLKx input SCxCR SCLKS 1 Falling mode RXDx INTRXx interrupt request SCxMOD2 RBFLL Receive data read timing SCLKx input SCxCR SCLKS 0 Rising mode SCLKx input SCxCR SCLKS 1 Falling mode RXDx INTRXx interrupt req...

Page 284: ...mission is resumed only when both conditions are satisfied If double buffers are enabled SCxMOD2 WBUF 1 Clock is outputted when the CPU writes data to the transmit buffer A data is shifted into the receive shift register moved to the receive buffer and the INTRXx is generated While a data is received a transmit data is output from the TXDx pin When all data are sent out the INTTXx is generated and...

Page 285: ...uest TXDx INTTXx interrupt request SCLKx output RXDx INTRXx interrupt request bit 0 bit 1 bit 6 Transmit data write timing bit 5 bit 7 bit 1 bit 0 WBUF 1 if double buffering is enabled Receive data read timing bit 0 bit 1 bit 6 bit 5 bit 7 bit 1 bit 0 Transmit data write timing WBUF 1 if double buffering is enabled SCxCR TIDLE 00 Receive data read timing bit 0 bit 1 bit 6 bit 5 bit 7 bit 0 bit 1 b...

Page 286: ...it shift register after completing data transmission from the transmit shift register At the same time data received is shifted to the shift register it is moved to the receive buffer and the INTRXx is generated Note that transmit data must be written into the transmit buffer before the clock input for the next data data must be written before the point A in Figure 12 20 Data must be read before c...

Page 287: ...NTTXx interrupt request Transmit data write timing WBUF 1 if double buffering is enabled with error generation SCxCR TXDEMP TIDLE 1 00 Receive data read timing bit 0 bit 1 bit 6 RXDx bit 5 bit 7 bit 1 bit 0 INTRXx interrupt request SCxCR PERR Under run errors A A bit 0 bit 1 bit 6 bit 5 bit 7 bit 0 bit 1 bit 6 bit 5 bit 7 bit 1 bit 0 SCLKx input SCxCR SCLKS 1 Falling mode SCLKx input SCxCR SCLKS 0...

Page 288: ...h 2 fperiph fsys 7 6 5 4 3 2 1 0 SCxMOD0 x 0 0 0 1 0 1 Set 7 bit UART mode SCxCR x 1 1 x x x 0 0 Even parity enabled SCxBRCR 0 0 1 0 0 1 0 0 Set 2400bps SCxBUF Set transmit data x don t care no change 12 14 3 Mode 2 8 bit UART mode The 8 bit UART mode is selected by setting SCxMOD0 SM 1 0 to 10 In this mode parity bits can be added and parity enable disable is controlled using SCxCR PE If PE 1 ena...

Page 289: ...a When writing or reading data to from the buffers the most significant bit must be written or read first be fore writing or reading to from SCxBUF The stop bit length can be specified using SCxMOD2 SBLEN 12 14 4 1 Wakeup function In the 9 bit UART mode slave controllers can be operated in the wake up mode by setting SCxMOD0 WU to 1 In this case the interrupt INTRXx will be generated only when SCx...

Page 290: ...h the con troller s own select code it clears the WU to 0 5 The master controller transmits data to the designated slave controller the controller of which SCxMOD0 WU is cleared to 0 In this the most significant bit bit 8 TB8 must be set to 0 stop start bit 0 1 2 3 4 5 6 7 bit 8 Data 0 6 The slave controllers with the WU set to 1 ignore the receive data because the most signif icant bit bit 8 RB8 ...

Page 291: ...t the I2C SIO in each operating mode Table 13 1 Port settings for using serial bus interface channel Operating mode pin Port Function Reg ister Port Output Control Register Port Input Control Register Port Open Drain Output Control Register SBI0 I2C bus mode SCL0 PC1 SDA0 PC0 PCFR3 1 0 11 PCCR 1 0 11 PCIE 1 0 11 PCOD 1 0 11 SIO mode SCK0 PC2 SI0 PC1 SO0 PC0 PCFR3 2 0 111 PCCR 2 0 101 SCK0 output P...

Page 292: ...ler SIO data control Transfer control circuit Noise canceller I2C bus clock synchroni zation control SIO clock control Frequency Divider fsys I2C bus data control Input Output control SDA SO SI SCL SCK SBICR2 SBISR SBII2CAR SBIDBR SBICR0 1 SBIBR0 INTSBI interrupt request SCK SDA SO SCL SI Figure 13 1 I2C SIO Block Interface TMPM3V6 M3V4 13 Serial Bus Interface I2C SIO 13 1 Configuration Page 270 2...

Page 293: ...ntrol register of SIO mode 13 2 1 Registers for each channel The tables below show the registers and register addresses for each channel Base Address 0x4002_0000 Register name Address Base Control register 0 SBICR0 0x0000 Control register 1 SBICR1 0x0004 Data buffer register SBIDBR 0x0008 I2C bus address register SBII2CAR 0x000C Control register 2 SBICR2 writing 0x0010 Status register SBISR readin...

Page 294: ...ta Data Slave address 1 to 8 bits 1 R W 8 bit A C K R W 8 bit Once Repeated 1 to 8 bits 1 1 S A C K A C K A C K P S Data Data Data 1 to 8 bits 1 a Addressing format b Addressing format with repeated start condition c Free data format master transmitter to slave receiver Note S Start condition R W Direction bit ACK Acknowledge bit P Stop condition Figure 13 2 I2C Bus Mode Data Formats TMPM3V6 M3V4 ...

Page 295: ...ol SBIEN After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31 8 R Read as 0 7 SBIEN R W Serial bus interface operation 0 Disable 1 Enable To use the serial bus interface enable this bit first For the first time in case of setting to enable the relevant SBI registers can be read or written Since all clocks except SBICR0 stop if this bit is disabled power consumption can be reduced by disabli...

Page 296: ...01 5 5 6 5 110 6 6 7 6 111 7 7 8 7 4 ACK R W Master mode 0 Acknowledgement clock pulse is not generated 1 Acknowledgement clock pulse is generated Slave mode 0 Acknowledgement clock pulse is not counted 1 Acknowledgement clock pulse is counted 3 R Read as 1 2 1 SCK 2 1 R W Select internal SCL output clock frequency Note 2 0 SCK 0 W 000 n 5 385 kHz 001 n 6 294 kHz System Clock fsys Clock gear fc 1 ...

Page 297: ...it is 0 Note 4 The initial value for selecting a frequency is SCK 2 0 000 and is independent of the read initial value Note 5 When BC 2 0 001 and ACK 0 in master mode SCL line may be fixed to L by falling edge of SCL line after generation of STOP condition and the other master devices can not use the bus In the case of bus which is connected with several master devices the number of bits per trans...

Page 298: ... condition generated 4 PIN W Clear INTSBI interrupt request 0 1 Clear interrupt request 3 2 SBIM 1 0 W Select serial bus interface operating mode Note 00 Port mode Disables a serial bus interface output 01 SIO mode 10 I2C bus mode 11 Reserved 1 0 SWRST 1 0 W Software reset generation Write 10 followed by 01 to generate a reset For details refer to 13 5 16 Software Reset Note Make sure that modes a...

Page 299: ... 0 7 MST R Master slave selection monitor 0 Slave mode 1 Master mode 6 TRX R Transmit receive selection monitor 0 Receive 1 Transmit 5 BB R I2C bus state monitor 0 Free 1 Busy 4 PIN R INTSBI interrupt request monitor 0 Interrupt request generated 1 Interrupt request cleared 3 AL R Arbitration lost detection 0 1 Detected 2 AAS R Slave address match detection 0 1 Detected This bit is set when the ge...

Page 300: ...25 24 bit symbol After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol DB After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31 8 R Read as 0 7 0 DB 7 0 R Receive W Transmit Receive data Transmit data Note 1 The transmission data must be written in to the register from...

Page 301: ...evice 0 ALS R W Specify address recognition mode 0 Recognize its slave address 1 Do not recognize its slave address free data format Note 1 Please set the bit 0 ALS of I2C bus address register SBII2CAR to 0 except when you use a free da ta format It operates as a free data format when setting it to 1 Selecting the master fixes to transmis sion Selecting the slave fixes to reception Note 2 Do not s...

Page 302: ...e The first master that pulls its clock line to the Low level overrides other masters producing the High level on their clock lines This must be detected and responded by the masters producing the High level Clock synchronization assures correct data transfer on a bus that has two or more master For example the clock synchronization procedure for a bus with two masters is shown below Wait for High...

Page 303: ... signals Howev er the second byte of the general call is necessary to be controlled by software to generate an acknowledge ment signal depending on the contents of the second byte By setting ACK to 0 the non acknowledgment mode is activated When operating as a master the SBI does not generate clock for acknowledgement signals In slave mode the clock for acknowledgement sig nals is counted 13 5 3 S...

Page 304: ...t changed by the hardware 13 5 7 Configuring the SBI as a Master or a Slave Setting SBICR2 MST to 1 configures the SBI to operate as a master device Setting MST to 0 configures the SBI as a slave device MST is cleared to 0 by the hardware when it detects the stop condition on the bus or the arbitration lost 13 5 8 Generating Start and Stop Conditions When SBISR BB is 0 writing 1 to SBICR2 MST TRX ...

Page 305: ...hen the received slave address match es the values specified at SBII2CAR or when a general call eight bits data following the start condition is all 0 is received When an interrupt request INTSBI is generated SBICR2 PIN is cleared to 0 While PIN is cleared to 0 the SBI pulls the SCL line to the Low level PIN is set to 1 when data is written to or read from SBIDBR It takes a period of tLOW for the ...

Page 306: ...SDA output master B SDA Line Loses arbitration and sets the internal SDA output to 1 Figure 13 7 Lost Arbitration A master compares the SDA bus line level and the internal SDA output level at the rising of the SCL line If there is a difference between these two values Arbitration Lost occurs and SBISR AL is set to 1 When an arbitration lost occurs SBIxSR MST and TRX are cleared to 0 causing the SB...

Page 307: ...d has been received AAS is cleared to 0 when data is written to or read from SBIDBR 13 5 12 General call Detection Monitor When the SBI operates as a slave device SBISR ADO is set to 1 when it receives the general call ad dress i e the eight bits following the start condition are all zeros ADO is cleared to 0 when the start or stop condition is detected on the bus 13 5 13 Last Received Bit Monitor...

Page 308: ...by 01 to SBIxCR2 SWRST 1 0 generates a reset signal that initializes the serial bus interface circuit When writing SBIxCR2 SWRST 1 0 set SBIxCR2 MST TRX BB PIN to 0000 and SBIxCR2 SBIM 1 0 to 10 for I2C bus mode After a reset all control registers and status flags are initialized to their reset values When the serial bus interface is initialized SWRST 1 0 is automatically cleared to 0 Note A softw...

Page 309: ...6 2 Generating the Start Condition and a Slave Address 13 6 2 1 Master mode In the master mode the following steps are required to generate the start condition and a slave address First ensure that the bus is free BB 0 Then write 1 to SBICR1 ACK to select the acknowl edgment mode Write to SBIDBR a slave address and a direction bit to be transmitted When BB 0 writing 1111 to SBICR2 MST TRX BB PIN g...

Page 310: ...e during the first eight clocks on the SCL line If the received address matches its slave address specified at SBII2CAR or is equal to the general call ad dress the SBI pulls the SDA line to the Low level during the ninth clock and outputs an acknowledg ment signal The INTSBI interrupt request is generated on the falling of the ninth clock and PIN is cleared to 0 In the slave mode the SBI holds th...

Page 311: ... and ACK are programmed and the transmit data is written into SBIDBR Writing the data makes PIN to 1 causing the SCL pin to generate a serial clock for transferring a next data word and the SDA pin to transfer the data word After the transfer is completed the INTSBI interrupt request is generated PIN is cleared to 0 and the SCL pin is pulled to the Low level To transmit more data words test LRB ag...

Page 312: ...n to the Low level Each time the received data is read from SBIDBR one word transfer clock and an acknowledgement signal are output Read the received data PIN Acknowledgment signal to transmitter Master output Slave output D7 D6 2 3 4 5 6 7 8 9 D5 D4 D3 D2 D1 ACK Next D7 D0 1 SCL pin INTSBIinterrupt request SDA pin Figure 13 11 BC 2 0 000 ACK 1 Receiver Mode To terminate the data transmission from...

Page 313: ...bits of data to be received and specify whether ACK is required Reg SBIDBR Reads dummy data End of interrupt INTSBI interrupt first to N 2 th data reception 7 6 5 4 3 2 1 0 Reg SBIDBR Reads the first to N 2 th data words End of interrupt INTSBI interrupt N 1 th data reception 7 6 5 4 3 2 1 0 SBICR1 X X X 0 0 X X X Disables generation of acknowledgement clock Reg SBIDBR Reads the N 1 th data word E...

Page 314: ... However the second byte of the general call is necessary to be controlled by software to generate an ac knowledgement signal depending on the contents of the second byte In the slave mode the normal slave mode processing or the processing as a result of Arbitration Lost is carried out SBISR AL TRX AAS and ADO are tested to determine the processing required Table 13 2 Processing in Slave Mode show...

Page 315: ...set to 0 that means the receiver re quires further data Set the number of bits in the da ta word to BC 2 0 and write the transmit data to the SBIDBR 0 1 1 1 0 Arbitration Lost is detected while a slave address is being transmitted and the SBI receives either a slave address with the direction bit 0 or a general call address transmitted by another master Read the SBIDBR a dummy read to set PIN to 1...

Page 316: ...se no stop condition is generated on the bus other devices recognize that the bus is busy Then test SBISR BB and wait until it becomes 0 to ensure that the SCLx pin is released Next test LRB and wait until it becomes 1 to ensure that no other device is pulling the SCLx bus line to the Low level Once the bus is determined to be free by following the above procedures follow the procedures described ...

Page 317: ...er device is pulling the SCL pin to the Low Then 4 7 μs Wait SBICR1 X X X 1 0 X X X Selects the acknowledgment mode SBIDBR X X X X X X X X Sets the desired slave address and direction SBICR2 1 1 1 1 1 0 0 0 Generates the start condition Note X Don t care SCL pin SCL Bus 0 MST 0 TRX 0 BB 1 PIN SDA pin LRB BB Start condition PIN 1 MST 1 TRX 1 BB 1 PIN 4 7 ms min 9 Figure 13 14 Timing Chart of Genera...

Page 318: ...fter reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol SBIEN After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31 8 R Read as 0 7 SBIEN R W Serial bus interface operation 0 Disable 1 Enable Enable this bit before using the serial bus interface If this bit is disabled power consumption can be reduced because all clocks except SBICR0 stop If the serial bus interface operation is enabled and th...

Page 319: ...e mode 3 R Read as 1 2 0 SCK 2 0 R W On writing SCK 2 0 Select serial clock frequency Note 1 000 n 3 2 5 MHz System clock fsys Clock gear fc 1 Frequency Hz fsys 2 2n 40MHz 001 n 4 1 25 MHz 010 n 5 625 kHz 011 n 6 313 kHz 100 n 7 156 kHz 101 n 8 78 kHz 110 n 9 39 kHz 111 External clock Note 1 After a reset the SCK 0 bit is read as 1 However if the SIO mode is selected at the SBICR2 regis ter the in...

Page 320: ...it Bit Symbol Type Function 31 8 R Read as 0 7 0 DB 7 0 R Receive data W Transmit data Note 1 The transmission data must be written in to the register from the MSB bit 7 The received data is stor ed in the LSB Note 2 Since SBIDBR has independent buffers for writing and reading a written data cannot be read Thus read modify write instructions such as bit manipulation cannot be used TMPM3V6 M3V4 13 ...

Page 321: ...er reset 1 Note 1 1 Note 1 1 Note 1 1 Note 1 0 0 1 Note 1 1 Note 1 Bit Bit Symbol Type Function 31 8 R Read as 0 7 4 R Read as 1 Note 1 3 2 SBIM 1 0 W Select serial bus interface operating mode Note 2 00 Port mode 01 SIO mode 10 I2Cbus mode 11 Reserved 1 0 R Read as 1 Note 1 Note 1 In this document the value written in the column after reset is the value after setting the SIO mode in the initial s...

Page 322: ...After reset 1 Note 1 Note 1 Note 1 Note 0 0 1 Note 1 Note Bit Bit Symbol Type Function 31 8 R Read as 0 7 4 R Read as 1 Note 3 SIOF R Serial transfer status monitor 0 Completed 1 In progress 2 SEF R Shift operation status monitor 0 Completed 1 In progress 1 0 R Read as 1 Note Note In this document the value written in the column after reset is the value after setting the SIO mode in the initial st...

Page 323: ...fter reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol I2SBI After reset 1 0 1 1 1 1 1 0 Bit Bit Symbol Type Function 31 8 R Read as 0 7 R Read as 1 6 I2SBI R W Operation in IDLE mode 0 Stop 1 Operate 5 1 R Read as 1 0 R W Make sure to write 0 TMPM3V6 M3V4 Page 301 2019 02 06 ...

Page 324: ...During this period the serial clock is stop ped automatically and the next shift operation is suspended until the processing is completed a0 b a c ULWH WKH WUDQVPLW GDWD 1 2 3 7 1 2 6 7 8 1 2 3 8 XWRPDWLF ZDLW a1 a2 a5 a6 a7 b0 b1 b5 b6 b7 b4 c0 c1 c2 SCK pin output SO pin output Figure 13 15 Automatic Wait 2 External clock SCK 2 0 111 The SBI uses an external clock supplied from the outside to th...

Page 325: ... shift Data is shifted at the trailing edge of the serial clock or the rising edge of the SCKx pin in put output bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 7654321 765432 76543210 76543 7654 765 76 7 Shift register bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 10 210 0 3210 43210 543210 6543210 76543210 Shift register a Leading edge b Trailing edge SCK pin SO pin SCK pin SI pin Figure 13 17...

Page 326: ...transfer rate varies depending on the maximum latency between when the inter rupt request is generated and when SBIDBR is loaded with data in the interrupt service program At the beginning of transmission the same value as in the last bit of the previously transmitted data is out put in a period from setting SBISR SIOF to 1 to the falling edge of SCK Transmission can be terminated by clearing SIOS...

Page 327: ...put SO pin INTSBI interrupt request SBIDBR SCK pin input SO pin INTSBI interrupt request SBIDBR Figure 13 18 Transmit Mode Example Example of programming external clock to terminate transmission by SIO 7 6 5 4 3 2 1 0 if SBISR SIOF 0 Recognizes the completion of the transmission Then if SCK 1 Recognizes 1 is set to the SCK pin by monitoring the port Then SBICR1 0 0 0 0 0 1 1 1 Completes the transm...

Page 328: ...equest and reading the received data Reception can be terminated by clearing SIOS to 0 or setting SIOINH to 1 in the INTSBI inter rupt service program If SIOS is cleared reception continues until all the bits of received data are writ ten to SBIDBR The program checks SBISR SIOF to determine whether reception has come to an end SIOF is cleared to 0 at the end of reception After confirming the compl...

Page 329: ...In the external clock mode shift operations are executed in synchronization with the external serial clock Therefore the received data must be read and the next transmit data must be written before the next shift operation is started The maximum data transfer rate for the external clock operation varies depend ing on the maximum latency between when the interrupt request is generated and when the ...

Page 330: ... transmit data SBICR1 1 0 1 0 0 X X X Starts reception transmission INTSBI interrupt Reg SBIDBR Reads the received data SBIDBR X X X X X X X X Writes the transmit data 13 8 2 4 Data retention time of the last bit at the end of transmission Under the condition SBICR1 SIOS 0 the last bit of the transmitted data retains the data of SCK ris ing edge as shown below Transmit mode and transmit receive mo...

Page 331: ...16bits wide 8 tiers deep Receive FIFO 16bits wide 8 tiers deep Transmitted received data size 4 to 16 bits Interrupt type Transmit interrupt Receive interrupt Receive overrun interrupt Time out interrupt Communication speed In master mode fsys 2 max 10Mbps In slave mode fsys 40MHz 12 max 3 3Mbps Internal test function The internal loopback test mode is available Control pin SPCLK SPFSS SPDO SPDI T...

Page 332: ...IFO Transmission Reception logic FIFO status and interrupt generation Interrupt request Reception buffer processing request Timeout Overrun Transmission buffer processing request Write data 15 0 Read data 15 0 SPDI SPDO SPCLK SPFSS INTSSP Figure 14 1 SSP block diagram TMPM3V6 M3V4 14 Synchronous Serial Port SSP 14 2 Block Diagram Page 310 2019 02 06 ...

Page 333: ... register SSPIMSC 0x0014 Pre enable interrupt status register SSPRIS 0x0018 Post enable interrupt status register SSPMIS 0x001C Interrupt clear register SSPICR 0x0020 Reserved 0x0028 to 0x0FFC Note 1 These registers in the above table allows to access only word 32 bits basis Note 2 Access to the Reserved area is prohibited TMPM3V6 M3V4 Page 311 2019 02 06 The followings are the SSP control registe...

Page 334: ...K phase 0 Captures data at the 1st clock edge 1 Captures data at the 2nd clock edge This is applicable to Motorola SPI frame format only Refer to Section Motorola SPI frame format 6 SPO R W SPCLK polarity 0 SPCLK is in Low state 1 SPCLK is in High state This is applicable to Motorola SPI frame format only Refer to Section Motorola SPI frame format 5 4 FRF 1 0 R W Frame format 00 SPI frame format 0...

Page 335: ...Type Function 31 4 W Write as 0 3 SOD R W Slave mode SPDO output control 0 Enable 1 Disable Slave mode output disable This bit is relevant only in the slave mode MS 1 2 MS R W Master slave mode select Note 0 Device configured as a master 1 Device configured as a slave 1 SSE R W SSP enable disable 0 Disable 1 Enable 0 LBM R W Loop back mode 0 Normal serial port operation enabled 1 Output of transmi...

Page 336: ...r Reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol DATA After Reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31 16 W Write as 0 15 0 DATA 15 0 R W Transmit receive FIFO data 0x0000 to 0xFFFF Read Receive FIFO Write Transmit FIFO If the data size used in the program is less than 16bits write the data to fit LSB The transmit control circuit ignores unused bits of MSB side The receive control cir...

Page 337: ...l BSY RFF RNE TNF TFE After Reset Undefined Undefined Undefined 0 0 0 1 1 Bit Bit Symbol Type Function 31 5 W Write as 0 4 BSY R Busy flag 0 Idle 1 Busy BSY 1 indicates that the SSP is currently transmitting and or receiving a frame or the transmit FIFO is not empty 3 RFF R Receive FIFO full flag 0 Receive FIFO is not full 1 Receive FIFO is full 2 RNE R Receive FIFO empty flag 0 Receive FIFO is em...

Page 338: ... Undefined Undefined Undefined Undefined Undefined 7 6 5 4 3 2 1 0 bit symbol CPSDVSR After Reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31 8 W Write as 0 7 0 CPSDVSR 7 0 R W Clock prescale divisor Set an even number from 2 to 254 Clock prescale divisor Must be an even number from 2 to 254 depending on the frequency of fsys The least significant bit always returns zero when read Note Set a c...

Page 339: ...e Function 31 4 W Write as 0 3 TXIM R W Transmit FIFO interrupt enable 0 Disable 1 Enable Enable or disable a conditional interrupt to occur if the transmit FIFO is half empty or less 2 RXIM R W Receive FIFO interrupt enable 0 Disable 1 Enable Enable or disable a conditional interrupt to occur if the receive FIFO is half full or less 1 RTIM R W Receive time out interrupt enable 0 Disable 1 Enable ...

Page 340: ... Undefined Undefined 7 6 5 4 3 2 1 0 bit symbol TXRIS RXRIS RTRIS RORRIS After Reset Undefined Undefined Undefined Undefined 1 0 0 0 Bit Bit Symbol Type Function 31 4 W Write as 0 3 TXRIS R Pre enable transmit interrupt flag 0 Interrupt not present 1 Interrupt present 2 RXRIS R Pre enable receive interrupt flag 0 Interrupt not present 1 Interrupt present 1 RTRIS R Pre enable timeout interrupt flag...

Page 341: ... Undefined Undefined Undefined Undefined 7 6 5 4 3 2 1 0 bit symbol TXMIS RXMIS RTMIS RORMIS After Reset Undefined Undefined Undefined Undefined 0 0 0 0 Bit Bit Symbol Type Function 31 4 W Write as 0 3 TXMIS R Post enable transmit interrupt flag 0 Interrupt not present 1 Interrupt present 2 RXMIS R Post enable receive interrupt flag 0 Interrupt not present 1 Interrupt present 1 RTMIS R Post enable...

Page 342: ...14 13 12 11 10 9 8 bit symbol After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 7 6 5 4 3 2 1 0 bit symbol RTIC RORIC After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Bit Bit Symbol Type Function 31 2 W Write as 0 1 RTIC W Clear the time out interrupt flag 0 Invalid 1 Clear 0 RORIC W Clear the overrun interrupt fl...

Page 343: ...n configured as a master a clock prescaler comprising two free running serially linked counters is used to provide the serial output clock SPCLK You can program the clock prescaler through the SSPCPSR register to divide fsys by a factor of 2 to 254 in steps of two Because the least significant bit of the SSPCPSR register is not used division by an odd num ber is not possible The output of the pres...

Page 344: ...able receive overrun interrupt INTSSP a Transmit interrupt The transmit interrupt is asserted when there are four or fewer valid entries in the transmit FIFO The transmit interrupt is also generated when the SSP operation is disabled SSPCR1 SSE 0 The first transmitted data can be written in the FIFO by using this interrupt b Receive interrupt The receive interrupt is asserted when there are four o...

Page 345: ... timeout interrupt enable During data transfer Receive timeout interrupt Internal down counter enable Receive FIFO empty flag bit rate SSPSR RNE SSPIMSC RTIM SPCLK SSPMIS RTMIS TMPM3V6 M3V4 Page 323 2019 02 06 ...

Page 346: ...eive FIFO as valid data To perform transfer proper ly when the overrun interrupt has been generated write 1 to SSPICR RORIC register and then read all data from the receive FIFO Even if all the data is not read data can be transmitted re ceived if the receive FIFO has free space and the number of data to be transmitted does not exceed the free space of the receive FIFO Note that if the receive FIF...

Page 347: ...ransmit FIFO with the operation enabled However if the transmit FIFO contains only four or fewer entries when the operation is enabled a trans mit interrupt will be generated This interrupt can be used to write the initial data Note When the SSP is in the SPI slave mode and the SPFSS pin is not used be sure to transmit data of one byte or more in the FIFO before enabling the operation If the opera...

Page 348: ... during data transmission Serial frame SPFSS In the SPI and Microwire frame formats signals are set to Low active and always asserted to Low during frame transmission In the SSI frame format signals are asserted only during 1 bit rate before each frame transmission In this frame format output data is transmitted at the rising edge of SPCLK and the input data is received at its falling edge Refer t...

Page 349: ...to the receive FIFO at the rising edge of SPCLK after its LSB data is latched 4 to 16 bit MSB LSB Hi Z Note1㸧 Hi Z Note1㸧 Hi Z Note2㸧 MSB Hi Z Note2㸧 LSB SPCLK SPFSS SPDO SPDI Figure 14 2 SSI frame format transmission reception during single transfer 4 to 16bit LSB MSB LSB LSB MSB MSB LSB MSB SPCLK SPFSS SPDO SPDI Figure 14 3 SSI frame format transmission reception during continuous transfer Note ...

Page 350: ...Note2 MSB Hi Z Note2㸧 LSB SPCLK SPFSS SPDO SPDI Figure 14 4 SPI frame format single transfer SPO 0 SPH 0 LSB MSB LSB LSB LSB MSB MSB MSB Hi Z Note2 Hi Z Note2 㸲 to 16bit SPCLK SPFSS SPDO SPDI Figure 14 5 SPI frame format continuous transfer SPO 0 SPH 0 Note 1 When transmission is disable SPDO terminal doesn t output and is high impedance status This terminal needs to add suitable pull up down resi...

Page 351: ...K signal and transmitted at its fall ing edge In the single transfer the SPFSS line will return to the idle High state when all the bits of that data word have been transferred and then one cycle of SPCLK has passed after the last bit was captured However for continuous transfer the SPFSS signal must be pulsed at HIGH between individual data word transfers This is because change is not enabled whe...

Page 352: ...mission the SSP does not receive input data After the mes sage has been transmitted the off chip slave decodes it and after waiting one serial clock after the last bit of the 8 bit control message has been sent responds with the requested data The returned data can be 4 to 16 bits in length making the total frame length anywhere from 13 to 25 bits With this configuration during the idle period The...

Page 353: ...sion signal will be high impedance sta tus this terminal needs to add suitable pull up down resistance to fix the voltage level For continuous transfers data transmission begins and ends in the same manner as a single transfer Howev er the SPFSS line is continuously asserted held Low and transmission of data occurs back to back The control byte of the next frame follows directly after the LSB of t...

Page 354: ...TMPM3V6 M3V4 14 Synchronous Serial Port SSP 14 6 Frame Format Page 332 2019 02 06 ...

Page 355: ...mer output Noise canceling time can be adjusted Leader detection Batch reception up to 72bit of data 15 2 Block Diagram Figure 15 1 shows the block diagram of RMC Receive buffer Receive error flag Receive control Register Internal databus Received control Noise filter Interrupt control Sampling clock System clock 㧔fsys Shift register RXINx RMCxREN RMCxRCR1 4 RMCxEND1 3 RMCxFSSEL RMCxRBUF1 3 RMCxRS...

Page 356: ...010 Receive Control Register 1 RMCxRCR1 0x0014 Receive Control Register 2 RMCxRCR2 0x0018 Receive Control Register 3 RMCxRCR3 0x001C Receive Control Register 4 RMCxRCR4 0x0020 Receive Status Register RMCxRSTAT 0x0024 Receive End bit Number Register 1 RMCxEND1 0x0028 Receive End bit Number Register 2 RMCxEND2 0x002C Receive End bit Number Register 3 RMCxEND3 0x0030 Source Clock selection Register R...

Page 357: ... RMCEN After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31 2 R Read as 0 1 R W Write as 1 0 RMCEN R W Controls RMC operation 0 Disabled 1 Enabled To allow RMC to function enable the RMCEN first If the operation is disabled all the clocks for RMC except for the enable register are stopped and it can reduce power consumption If RMC is enabled and then disabled the settings in each register r...

Page 358: ...t 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol RMCREN After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31 1 R Read as 0 0 RMCREN R W Reception 0 Disabled 1 Enabled Controls reception of RMC Setting this bit to 1 enables reception Note Enable the RMCxREN RMCREN bit after setting the RMCxRCR1 RMCxRCR2 and RMCxRCR3 TMPM3V6 M3V4 15 Remote Control Signal Preprocessor RMC 15 3 Registers Page 336 2...

Page 359: ...RBUF 31 0 R Received data 31 to 0 bit Reads 4 bytes of received data 31 to 0 bit 15 3 5 RMCxRBUF2 Receive Data Buffer Register 2 31 30 29 28 27 26 25 24 bit symbol RMCRBUF Received data 63 to 54 bit After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol RMCRBUF Received data 55 to 48 bit After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol RMCRBUF Received data 47 to 40 bit After r...

Page 360: ...fter reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31 8 R Read as 0 7 0 RMCRBUF 71 64 R Received data 71 to 64 bit Reads 1 byte of received data 71 to 64 bit Note The received bit is stored in the data buffer register in MSB first order and the last received bit is stored in the LSB bit 0 If the remote control signal is received in the LSB first algorithm the received data is stored in revers...

Page 361: ...CMIN 4 fs s 15 8 RMCLLMAX 7 0 R W Specifies a maximum Low width of leader detection Calculating formula of the maximum Low width RMCLLMAX 4 fs s 7 0 RMCLLMIN 7 0 R W Specifies a minimum Low width of leader detection Calculating formula for the minimum Low width RMCLLMIN 4 fs s When RMCxRCR2 RMCLD 1 a value of the Low pulse width is less than the specified value it is defined as data bit Note When ...

Page 362: ...a remote control signal by a phase modulation 0 Not receiving a remote control signal by a phase modulation receive by a cycle modulation 1 Receive remote control signal by a fixed frequency pulse modulation To receive a fixed frequency remote control signal by a pulse modulation set this bit to 1 23 16 R Read as 0 15 8 RMCLL 7 0 R W Excess Low width that triggers reception completion and interrup...

Page 363: ... Read as 0 6 0 RMCDATL 6 0 R W Threshold to determine 0 or 1 smaller threshold to determine a signal pattern in a phase method Calculating formula of the threshold RMCDATL 1 fs s Specifies two kinds of thresholds a threshold to determine whether a data bit is 0 or 1 a smaller threshold within a range of 1T and 1 5T to determine a pattern of remote control signal in a phase method As for the determ...

Page 364: ... 4 3 2 1 0 bit symbol RMCPO RMCNC After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31 8 R Read as 0 7 RMCPO R W Remote control input signal 0 Not reversed 1 Reversed 6 4 R Read as 0 3 0 RMCNC 3 0 R W Specifies noise cancellation time 0000 No cancellation 0001 to 1111 cancellation Calculating formula of noise cancellation time RMCNC 1 fs s TMPM3V6 M3V4 15 Remote Control Signal Preprocessor ...

Page 365: ...um data bit cycle interrupt generated 12 RMCEDIF R Interrupt source flag 0 No falling edge interrupt generated 1 Falling edge interrupt generated 11 8 R Read as 0 7 RMCRLDR R Leader detection 0 Disable leader detection 1 Enable leader detection 6 0 RMCRNUM 6 0 R The number of received data bit 000_0000 no data bit only with leader 000_0001 to 100_1000 1 to 72bit 100_1001 to 111_1111 73bit and more...

Page 366: ...bit 1 to 72bit 100_1001 to 111_1111 Don t set the value 15 3 13 RMCxEND2 Receive End bit Number Register 2 31 30 29 28 27 26 25 24 bit symbol After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol RMCEND2 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31 7 R Read as...

Page 367: ...Bit Symbol Type Function 31 7 R Read as 0 6 0 RMCEND3 6 0 R W Specifies the number of receive data bit 000_0000 No specifically the receive data bit 000_0001 to 100_1000 Specifies that the number of receive data bit 1 to 72bit 100_1001 to 111_1111 Don t set the value Note 1 As specified to RMCxEND1 RMCxEND2 and RMCxEND3 it is able to set three kinds of the receive data bit Note 2 To use the RMCxEN...

Page 368: ...on 0 Low frequency Clock 32 768kHz 1 Timer output TBxOUT For the Sampling of RMC function It is able to set the Low Frequency Clock 32 768kHz or Timer output TBxOUT For the information of TBxOUT used for sampling clock refer to Chapter Product Information The Setting range of Timer output by TBxOUT is from 30 to 34kHz Note To Change the sampling clock by using the RMCxFSSEL disable the RMC operati...

Page 369: ...T RMCE DIF is set Data reception stops when the maximum data bit cycle is detected and Low width matches the set ting value and then an interrupt occurs If RMCEND1 RMCEND2 and RMCEND3 of the regis ter RMCxEND1 RMCxEND2 and RMCxEND3 have been configured data reception stops and an inter rupt occurs only in the case that the number of bits received before maximum data bit cycle is detected The condi...

Page 370: ...s changed to Low after monitoring cycles of Low s specified in RMCNC If Low is monitored RMC recognizes that the signal was changed to High after monitoring cycles of High specified in RMCNC The following figure shows how RMC operates according to the noise cancel setting of RMCNC 3 0 0011 3 cycles Subsequent to noise cancellation the signal is changed from High to Low upon monitoring 3 cycles of ...

Page 371: ...0 RMCLLMIN 7 0 don t care No leader RMCLCMAX 7 0 0000_0000 RMCLCMIN 7 0 don t care RMCLLMAX 7 0 don t care RMCLLMIN 7 0 don t care Low width Minimum low width RMCLLMIN 7 0 Maximum low width RMCLLMAX 7 0 cycle Minimum cycle RMCLCMIN 7 0 Maximum cycle RMCLCMAX 7 0 Waiting for leader Leader detection interrupt Figure 15 4 Leader wave form and the RMCxRCR1 register settings If you want to generate an ...

Page 372: ...ion value is less than threshold value it is determined as 0 2 Determination by falling edge interrupt inputs By setting 1 to the RMCxRCR2 RMCEDIEN a remote control signal input falling edge interrupt can be generated in each falling edge of the data bit Using this interrupt togeth er with a timer enables the determination to be done by software The following shows the determination method of data...

Page 373: ...f the falling edge of the data bit cycle isn t monitored after time specified as threshold in the RMCDMAX 7 0 a maximum data bit cycle is detected The detection completes reception and generates an interrupt After interrupt inputs generated RMCxRSTAT RMCDMAXIF is set to 1 To complete reception by setting the number of receive data is set a RMCxEND1 to 3 reg ister of each RMCEND1 RMCEND2 RMCEND3 In...

Page 374: ...excess Low width is detected The detection completes reception and generates an in terrupt After interrupt inputs generated RMCxRSTAT RMCLOIF is set to 1 Threshold RMCLL 7 0 Excess low width is detected when signal stay low longer than specified Excess low width detection interrupt Figure 15 7 Completion by detecting Low width TMPM3V6 M3V4 15 Remote Control Signal Preprocessor RMC 15 4 Operation D...

Page 375: ...ting RMCxRCR2 RMCLD RMC starts receiving data if it recognizes a signal of which Low width is shorter than a maximum Low width of leader detection specified in the RMCxRCR1 RMCLLMAX 7 0 RMC keeps receiving data until the final data bit is received If RMCxRCR2 RMCLD is enabled the same settings of error detection reception completion and da ta bit determination of 0 or 1 are applied regardless of w...

Page 376: ... detection with the RMCxRCR3 RMCDATL 6 0 The maximum data bit cycle is configured with the RMCDMAX 7 0 of the RMCxRCR2 To complete data reception configure the maximum data bit cycle with RMCDMAX 7 0 of the RMCxRCR2 and configure the Low pulse width detection with RMCLL 7 0 After detecting the maximum data bit cycle and confirming the Low pulse with which is specified af ter receiving the last bit...

Page 377: ...hresholds are used to distinguish three waveform patterns On condition that a cycle between two falling edges is T three patterns show cycles of 1T 1 5T and 2T Details of the two thresholds are shown below Determined by Threshold Register bits to set Threshold 1 Pattern 1 pattern 2 1T to 1 5T RMCxRCR3 RMCDATL 6 0 Threshold 2 Pattern 2 pattern 3 1 5T to 2T RMCxRCR3 RMCDATH 6 0 To determine a remote...

Page 378: ...rst two bits of data need to be 11 Remote control signal Figure 15 11 The waveform pattern in phase method TMPM3V6 M3V4 15 Remote Control Signal Preprocessor RMC 15 4 Operation Description Page 356 2019 02 06 ...

Page 379: ...n result 4 The ADCs generate interrupt signal at the end of the program which was started by MRB trigger 5 The ADCs generate interrupt signal at the end of the program which are the Software Trigger Program and the Constant Trigger Program 6 The ADCs have the AD conversion monitoring function When this function is enabled an interrupt is gen erated when a conversion result matches the specified co...

Page 380: ...0x003C Conversion Result Register 8 ADREG8 0x0040 Conversion Result Register 9 ADREG9 0x0044 Conversion Result Register 10 ADREG10 0x0048 Conversion Result Register 11 ADREG11 0x004C Reserved 0x0050 to 0x00AC Timer Trigger Program Registers 0 to 3 ADTSET03 0x00B0 Timer Trigger Program Registers 4 to 7 ADTSET47 0x00B4 Timer Trigger Program Registers 8 to 11 ADTSET811 0x00B8 Software Trigger Program...

Page 381: ...ymbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol TSH ADCLK After reset 0 1 0 1 1 0 0 0 Bit Bit Symbol Type Function 31 7 R Read as 0 6 3 TSH 3 0 R W Write as 1001 2 0 ADCLK 2 0 R W AD prescaler output SCLK select 000 fc Note 001 to 111 Reserved Note The AD conversion times are 1T 74 1 SCLK in the 12 bit mode and T 68 1 SCLK i...

Page 382: ... 0 0 Bit Bit Symbol Type Function 31 2 R Read as 0 1 DACON R W ADC operation control 1 0 Stop 1 Operate Setting DACON to 1 when using the ADC 0 ADSS W Software triggered conversion 0 Don t care 1 Start Setting ADSS to 1 starts AD conversion software triggered conversion Receiving trigger signal from TMRB interrupt starts AD conversion also For detail setting please read the chapter about TMRB TMPM...

Page 383: ...0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol ADEN ADAS After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31 8 R Read as 0 7 ADEN R W AD conversion control 0 Disable 1 Enable Setting ADEN to 1 when using the ADC After Setting ADEN to 1 setting ADAS to 1 starts AD conversion and repeat conversion 6 1 R Read as 0 0 ADAS R W Constant AD conversion control 0 Disable 1 Enable TMPM3V6 M3V4 Page 361 ...

Page 384: ...n completed 1 Conversion in progress The ADSFN is a software AD conversion busy flag After ADSS was set to 1 when AD conversion is actually started ADSFN is set to 1 When finished AD conversion ADSFN is cleared to 0 0 ADBFN R AD conversion busy flag 0 Conversion not in progress 1 Conversion in progress The ADBFN is an AD conversion busy flag When AD conversion is started regardless of conversion f...

Page 385: ...pe Function 31 16 R Read as 0 15 12 R W Write as 0 11 10 BITS 1 0 R W 12 bit 10 bit resolution mode selection 00 10 bit 01 12 bit 10 to 11 Reserved 9 R W Write as 0 8 RCUT R W ADC operation control 2 0 Operate 1 Stop Write 0 under AD conversion By setting ADMOD3 RCUT to 1 consumption current will be reduced 7 R W Write as 0 6 R W Write as 1 5 3 PMODE 2 0 R W Write as 100 2 0 R W Write as 0 Note AD...

Page 386: ...be compared with an AD conversion result and to set how many times comparison should be performed to determine the result 7 CMP0EN R W Monitoring function 0 Disable 1 Enable By setting CMP0EN 0 disable accumulated number of decision counts is cleared 6 5 R Read as 0 4 ADBIG0 R W Comparison condition 0 Larger than or equal to compare register 1 Smaller than or equal to compare register Compares whe...

Page 387: ...lue to select the register to be compared with an AD conversion result and to set how many times comparison should be performed to determine the result 7 CMP1EN R W Monitoring function 0 Disable 1 Enable By setting CMP1EN 0 disable accumulated number of decision counts is cleared 6 5 R Read as 0 4 ADBIG1 R W Comparison condition 0 Larger than or equal to compare register 1 Smaller than or equal to...

Page 388: ...N 0 CMP1EN 0 in advance when this register is modified 16 4 9 ADCMP1 Conversion Result Compare Register 1 31 30 29 28 27 26 25 24 bit symbol After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol AD1CMP After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol AD1CMP After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31 16 R R...

Page 389: ... 16 R Read as 0 15 4 ADR0 11 0 R The value of an AD conversion result 3 2 R Read as 0 1 OVR0 R OverRun flag 0 No overrun occurred 1 Overrun occurred This flag is set when a new AD conversion result is stored before the value of ADREG0 is read and is cleared when the ADREG0 is read 0 ADR0RF R AD conversion result store flag 0 No result stored 1 Result stored ADR0RF is a flag that is set when an AD ...

Page 390: ... ADR1 11 0 R The value of an AD conversion result 3 2 R Read as 0 1 OVR1 R OverRun flag 0 No overrun occurred 1 Overrun occurred This flag is set when a new AD conversion result is stored before the value of ADREG1 is read and is cleared when the ADREG1 is read 0 ADR1RF R AD conversion result store flag 0 No result stored 1 Result stored ADR1RF is a flag that is set when an AD conversion result is...

Page 391: ...nction 31 16 R Read as 0 15 4 ADR2 11 0 R The value of an AD conversion result 3 2 R Read as 0 1 OVR2 R OverRun flag 0 No overrun occurred 1 Overrun occurred This flag is set when a new AD conversion result is stored before the value of ADREG2 is read and is cleared when the ADREG2 is read 0 ADR2RF R AD conversion result store flag 0 No result stored 1 Result stored ADR2RF is a flag that is set wh...

Page 392: ... ADR3 11 0 R The value of an AD conversion result 3 2 R Read as 0 1 OVR3 R OverRun flag 0 No overrun occurred 1 Overrun occurred This flag is set when a new AD conversion result is stored before the value of ADREG3 is read and is cleared when the ADREG3 is read 0 ADR3RF R AD conversion result store flag 0 No result stored 1 Result stored ADR3RF is a flag that is set when an AD conversion result is...

Page 393: ...nction 31 16 R Read as 0 15 4 ADR4 11 0 R The value of an AD conversion result 3 2 R Read as 0 1 OVR4 R OverRun flag 0 No overrun occurred 1 Overrun occurred This flag is set when a new AD conversion result is stored before the value of ADREG4 is read and is cleared when the ADREG4 is read 0 ADR4RF R AD conversion result store flag 0 No result stored 1 Result stored ADR4RF is a flag that is set wh...

Page 394: ... ADR5 11 0 R The value of an AD conversion result 3 2 R Read as 0 1 OVR5 R OverRun flag 0 No overrun occurred 1 Overrun occurred This flag is set when a new AD conversion result is stored before the value of ADREG5 is read and is cleared when the ADREG5 is read 0 ADR5RF R AD conversion result store flag 0 No result stored 1 Result stored ADR5RF is a flag that is set when an AD conversion result is...

Page 395: ...nction 31 16 R Read as 0 15 4 ADR6 11 0 R The value of an AD conversion result 3 2 R Read as 0 1 OVR6 R OverRun flag 0 No overrun occurred 1 Overrun occurred This flag is set when a new AD conversion result is stored before the value of ADREG6 is read and is cleared when the ADREG6 is read 0 ADR6RF R AD conversion result store flag 0 No result stored 1 Result stored ADR6RF is a flag that is set wh...

Page 396: ... ADR7 11 0 R The value of an AD conversion result 3 2 R Read as 0 1 OVR7 R OverRun flag 0 No overrun occurred 1 Overrun occurred This flag is set when a new AD conversion result is stored before the value of ADREG7 is read and is cleared when the ADREG7 is read 0 ADR7RF R AD conversion result store flag 0 No result stored 1 Result stored ADR7RF is a flag that is set when an AD conversion result is...

Page 397: ...nction 31 16 R Read as 0 15 4 ADR8 11 0 R The value of an AD conversion result 3 2 R Read as 0 1 OVR8 R OverRun flag 0 No overrun occurred 1 Overrun occurred This flag is set when a new AD conversion result is stored before the value of ADREG8 is read and is cleared when the ADREG8 is read 0 ADR8RF R AD conversion result store flag 0 No result stored 1 Result stored ADR8RF is a flag that is set wh...

Page 398: ... ADR9 11 0 R The value of an AD conversion result 3 2 R Read as 0 1 OVR9 R OverRun flag 0 No overrun occurred 1 Overrun occurred This flag is set when a new AD conversion result is stored before the value of ADREG9 is read and is cleared when the ADREG9 is read 0 ADR9RF R AD conversion result store flag 0 No result stored 1 Result stored ADR9RF is a flag that is set when an AD conversion result is...

Page 399: ...ction 31 16 R Read as 0 15 4 ADR10 11 0 R The value of an AD conversion result 3 2 R Read as 0 1 OVR10 R OverRun flag 0 No overrun occurred 1 Overrun occurred This flag is set when a new AD conversion result is stored before the value of ADREG10 is read and is cleared when the ADREG10 is read 0 ADR10RF R AD conversion result store flag 0 No result stored 1 Result stored ADR10RF is a flag that is s...

Page 400: ...ADR11 11 0 R The value of an AD conversion result 3 2 R Read as 0 1 OVR11 R OverRun flag 0 No overrun occurred 1 Overrun occurred This flag is set when a new AD conversion result is stored before the value of ADREG11 is read and is cleared when the ADREG11 is read 0 ADR11RF R AD conversion result store flag 0 No result stored 1 Result stored ADR11RF is a flag that is set when an AD conversion resu...

Page 401: ... m 0 to 11 Table 16 1 Select the AIN pin AINST00 4 0 to AINST53 4 0 AD Channel 0_0000 AIN0 0_0001 AIN1 0_0010 AIN2 0_0011 AIN3 0_0100 AIN4 0_0101 AIN5 0_0110 AIN6 0_0111 AIN7 0_1000 AIN8 0_1001 AIN9 0_1010 AIN10 0_1011 AIN11 0_1100 AIN12 0_1101 AIN13 0_1110 AIN14 0_1111 AIN15 1_0000 AIN16 1_0001 AIN17 1_0010 to 1_1111 reserved ADTSET03 Timer Trigger Program Registers 03 31 30 29 28 27 26 25 24 bit...

Page 402: ...0 20 16 AINST2 4 0 R W AIN select Refer to Table 16 1 Select the AIN pin 15 ENST1 R W ADREG1 enable 0 Disable 1 Enable 14 13 R Read as 0 12 8 AINST1 4 0 R W AIN select Refer to Table 16 1 Select the AIN pin 7 ENST0 R W ADREG0 enable 0 Disable 1 Enable 6 5 R Read as 0 4 0 AINST0 4 0 R W AIN select Refer to Table 16 1 Select the AIN pin TMPM3V6 M3V4 16 Analog Digital Converter ADC 16 4 Register Desc...

Page 403: ... 31 ENST7 R W ADREG7 enable 0 Disable 1 Enable 30 29 R Read as 0 28 24 AINST7 4 0 R W AIN select Refer to Table 16 1 Select the AIN pin 23 ENST6 R W ADREG6 enable 0 Disable 1 Enable 22 21 R Read as 0 20 16 AINST6 4 0 R W AIN select Refer to Table 16 1 Select the AIN pin 15 ENST5 R W ADREG5 enable 0 Disable 1 Enable 14 13 R Read as 0 12 8 AINST5 4 0 R W AIN select Refer to Table 16 1 Select the AIN...

Page 404: ... 0 Disable 1 Enable 30 29 R Read as 0 28 24 AINST11 4 0 R W AIN select Refer to Table 16 1 Select the AIN pin 23 ENST10 R W ADREG10 enable 0 Disable 1 Enable 22 21 R Read as 0 20 16 AINST10 4 0 R W AIN select Refer to Table 16 1 Select the AIN pin 15 ENST9 R W ADREG9 enable 0 Disable 1 Enable 14 13 R Read as 0 12 8 AINST9 4 0 R W AIN select Refer to Table 16 1 Select the AIN pin 7 ENST8 R W ADREG8...

Page 405: ... 2 Select the AIN pin AINSS00 4 0 to AINSS53 4 0 AD Channel 0_0000 AIN0 0_0001 AIN1 0_0010 AIN2 0_0011 AIN3 0_0100 AIN4 0_0101 AIN5 0_0110 AIN6 0_0111 AIN7 0_1000 AIN8 0_1001 AIN9 0_1010 AIN10 0_1011 AIN11 0_1100 AIN12 0_1101 AIN13 0_1110 AIN14 0_1111 AIN15 1_0000 AIN16 1_0001 AIN17 1_0010 to 1_1111 reserved ADSSET03 Software Trigger Program Registers 03 31 30 29 28 27 26 25 24 bit symbol ENSS3 AI...

Page 406: ...0 20 16 AINSS2 4 0 R W AIN select Refer to Table 16 2 Select the AIN pin 15 ENSS1 R W ADREG1 enable 0 Disable 1 Enable 14 13 R Read as 0 12 8 AINSS1 4 0 R W AIN select Refer to Table 16 2 Select the AIN pin 7 ENSS0 R W ADREG0 enable 0 Disable 1 Enable 6 5 R Read as 0 4 0 AINSS0 4 0 R W AIN select Refer to Table 16 2 Select the AIN pin TMPM3V6 M3V4 16 Analog Digital Converter ADC 16 4 Register Desc...

Page 407: ...on 31 ENSS7 R W ADREG7 enable 0 Disable 1 Enable 30 29 R Read as 0 28 24 AINSS7 4 0 R W AIN select Refer to Table 16 2 Select the AIN pin 23 ENSS6 R W ADREG6 enable 0 Disable 1 Enable 22 21 R Read as 0 20 16 AINSS6 4 0 R W AIN select Refer to Table 16 2 Select the AIN pin 15 ENSS5 R W ADREG5 enable 0 Disable 1 Enable 14 13 R Read as 0 12 8 AINSS5 4 0 R W AIN select Refer to Table 16 2 Select the A...

Page 408: ...e 0 Disable 1 Enable 30 29 R Read as 0 28 24 AINSS11 4 0 R W AIN select Refer to Table 16 2 Select the AIN pin 23 ENSS10 R W ADREG10 enable 0 Disable 1 Enable 22 21 R Read as 0 20 16 AINSS10 4 0 R W AIN select Refer to Table 16 2 Select the AIN pin 15 ENSS9 R W ADREG9 enable 0 Disable 1 Enable 14 13 R Read as 0 12 8 AINSS9 4 0 R W AIN select Refer to Table 16 2 Select the AIN pin 7 ENSS8 R W ADREG...

Page 409: ...he AIN pin to be used The numbers of the Constant Trigger Program Registers corre spond to those of the Conversion Result Registers m 0 to 11 Table 16 3 Select the AIN pin AINSA00 4 0 to AINSA53 4 0 AD Channel 0_0000 AIN0 0_0001 AIN1 0_0010 AIN2 0_0011 AIN3 0_0100 AIN4 0_0101 AIN5 0_0110 AIN6 0_0111 AIN7 0_1000 AIN8 0_1001 AIN9 0_1010 AIN10 0_1011 AIN11 0_1100 AIN12 0_1101 AIN13 0_1110 AIN14 0_111...

Page 410: ... 0 Disable 1 Enable 30 29 R Read as 0 28 24 AINSA3 4 0 R W AIN select Refer to Table 16 3 Select the AIN pin 23 ENSA2 R W ADREG2 enable 0 Disable 1 Enable 22 21 R Read as 0 20 16 AINSA2 4 0 R W AIN select Refer to Table 16 3 Select the AIN pin 15 ENSA1 R W ADREG1 enable 0 Disable 1 Enable 14 13 R Read as 0 12 8 AINSA1 4 0 R W AIN select Refer to Table 16 3 Select the AIN pin 7 ENSA0 R W ADREG0 ena...

Page 411: ...ion 31 ENSA7 R W ADREG7 enable 0 Disable 1 Enable 30 29 R Read as 0 28 24 AINSA7 4 0 R W AIN select Refer to Table 16 3 Select the AIN pin 23 ENSA6 R W ADREG6 enable 0 Disable 1 Enable 22 21 R Read as 0 20 16 AINSA6 4 0 R W AIN select Refer to Table 16 3 Select the AIN pin 15 ENSA5 R W ADREG5 enable 0 Disable 1 Enable 14 13 R Read as 0 12 8 AINSA5 4 0 R W AIN select Refer to Table 16 3 Select the ...

Page 412: ...ble 0 Disable 1 Enable 30 29 R Read as 0 28 24 AINSA11 4 0 R W AIN select Refer to Table 16 3 Select the AIN pin 23 ENSA10 R W ADREG10 enable 0 Disable 1 Enable 22 21 R Read as 0 20 16 AINSA10 4 0 R W AIN select Refer to Table 16 3 Select the AIN pin 15 ENSA9 R W ADREG9 enable 0 Disable 1 Enable 14 13 R Read as 0 12 8 AINSA9 4 0 R W AIN select Refer to Table 16 3 Select the AIN pin 7 ENSA8 R W ADR...

Page 413: ...ecuted Output operation is executed Output current of port varies Take a countermeasure such as averaging the multiple conversion results to get precise value 16 5 2 Starting AD Conversion AD conversion is started by software or timer trigger signals These start triggers are given priorities as shown below If the upper level trigger occurs while an AD conversion is in progress the upper level trig...

Page 414: ...he ADCs have the AD conversion monitoring function When this function is enabled an interrupt is gen erated when a conversion result matches the specified comparison value To enable the monitoring function set ADCMPCR0 CMP0EN or ADCMPCR1 CMP1EN to 1 In the monitoring function if the value of AD conversion result register to which the monitoring function is as signed corresponds to the comparison c...

Page 415: ...ure 16 4 AINA0 AINA0 conversion AINA1 AINA1 conversion AINA2 AINA2 conversion AINA3 AINA3 conversion AINA4 AINA4 conversion AD conversion Busy flag varies according to conversion INTADASFT is generated by the completion of selected AD conversion at the timing of clearing of ADSFN Software trigger conversion ADSS 1 AD conversion busy flag ADBFN Software conversion busy flag ADSFN Condition Software...

Page 416: ... is stored to the result register The conversion of AINA2 AINA2 doesn t start Software conversion busy flag ADSFN Clearing of ADBFN is delayed The result of A AINA1 INA1 is not stored to the result register Condition Software trigger setting AINA0 AINA1 AINA2 AINA0 AINA1 AINA2 AIN0 AIN1 AIN2 AIN0 AIN1 AIN2 AIN1 AIN0 AIN0 Figure 16 4 Writing 0 to ADEN during the software trigger AD conversion TMPM3...

Page 417: ...INA0 conversion AINA0 AINA0 conversion AD conversion Reading of the result register 16bit Constant conversion control ADAS 1 1st result of AINA0 AINA0 2nd result of AINA0 AINA0 3rd result of AINA0 AINA0 4th result of AINA0 AINA0 AD conversion result store flag ADR10RF Over Run flag OVR10 Over Run flag is set caused by no reading of 1st result Reading of 2nd result makes Over Run flag cleared 2nd r...

Page 418: ...2 06 AIN0 conversion by software trigger Max 425ns AD conversion conversion by software trigger Condition Software trigger setting AIN0 AIN1 AIN2 Timer trigger setting AIN0 Timer trigger AIN4 Conversion by timer trigger Software trigger conversion interrupt INTADSFT The interrupt is generated after completion of the software AD conversion Timer trigger conversion interrupt 㸦INTADTMR AIN0 to AIN2 c...

Page 419: ...TMPM3V6 M3V4 Page 397 2019 02 06 ...

Page 420: ...TMPM3V6 M3V4 16 Analog Digital Converter ADC 16 6 Timing chart of AD conversion Page 398 2019 02 06 ...

Page 421: ...ess Adjust Figure 17 1 Block Diagram Note 1 Western calendar year column This product uses only the final two digits of the year The year following 99 is 00 years Please take into account the first two digits when handling years in the western calendar Note 2 Leap year A leap year is divisible by 4 excluding a year divisible by 100 the year divisible by 100 is not considered to be a leap year Any ...

Page 422: ...000C Reserved 0x000D Note 1 0x000E Note 1 0x000F Note 1 0 is read by reading the address Writing is disregarded Note 2 Access to the Reserved areas is prohibited 17 3 2 Control Register Reset operation initializes the following registers RTCPAGER PAGE ADJUST INTENA RTCRESTR RSTALM RSTTMR DIS16HZ DIS1HZ DIS2HZ DIS4HZ DIS8HZ Other clock related registers are not initialized by reset operation Before...

Page 423: ... RTCDAYR RTCMONTHR RTCYEARR of PAGE0 captures the current state Table 17 2 PAGE1 alarm function registers Symbol Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Function RTCSECR RTCMINR 40min 20min 10min 8min 4min 2min 1min Minute column RTCHOURR 20hours PM AM 10hour 8hour 4hour 2hour 1hour Hour column RTCDAYR Day of the week Day of the week column RTCDATER Day20 Day10 Day8 Day4 Day2 Day1 Day column RTCMO...

Page 424: ..._1001 59sec Note The setting other than listed above is prohibited 17 3 3 2 RTCMINR Minute column register PAGE0 1 7 6 5 4 3 2 1 0 Bit symbol MI After reset 0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Bit Bit Symbol Type Function 7 R Read as 0 6 0 MI R W Setting digit register of Minutes 000_0000 00min 000_0001 01min 000_0010 02min 000_0011 03min 000_0100 04min 000_0101...

Page 425: ...clock 10_0011 23 o clock 11_1111 don t care Only PAGE1 Note The setting other than listed above is prohibited 2 12 hour clock mode RTCMONTHR MO0 0 7 6 5 4 3 2 1 0 Bit symbol HO After reset 0 0 Undefined Undefined Undefined Undefined Undefined Undefined Bit Bit Symbol Type Function 7 6 R Read as 0 5 0 HO R W Setting digit register of Hour AM PM 00_0000 0 o clock 00_0001 1 o clock 00_0010 2 o clock ...

Page 426: ... Read as 0 5 0 DA R W Setting digit register of day 00_0001 1st day 00_0010 2nd day 00_0011 3rd day 00_0100 4th day 00_0101 5th day 00_0110 6th day 00_0111 7th day 00_1000 8th day 00_1001 9th day 01_0000 10th day 01_0001 11th day 01_0010 12th day 01_0011 13th day 01_0100 14th day 01_0101 15th day 01_0110 16th day 01_0111 17th day 01_1000 18th day 01_1001 19th day 10_0000 20th day 10_0001 21th day ...

Page 427: ...February March April May June 0_0111 0_1000 0_1001 1_0000 1_0001 1_0010 July August September October November December Note The setting other than listed above is prohibited 17 3 3 7 RTCMONTHR Selection of 24 hour clock or 12 hour clock for PAGE1 only 7 6 5 4 3 2 1 0 bit symbol MO0 After reset 0 0 0 0 0 0 0 Undefined Bit Bit Symbol Type Function 7 1 R Read as 0 0 MO0 R W 0 12 hour 1 24 hour Note ...

Page 428: ...rs 0001_0000 10 years 0010_0000 20 years 0011_0000 30 years 0100_0000 40 years 01001_0000 50 years 0110_0000 60 years 0111_0000 70 years 1000_0000 80 years 1001_0000 90 years 1001_1001 99 years Note The setting other than listed above is prohibited 17 3 3 9 RTCYEARR Leap year register for PAGE1 only 7 6 5 4 3 2 1 0 bit symbol LEAP After reset 0 0 0 0 0 0 Undefined Undefined Bit Bit Symbol Type Fun...

Page 429: ...is read it indicates that ADJUST is being executed If 0 is read it indicates that the execution is finished 3 ENATMR R W Clock 0 Disable 1 Enable 2 ENAALM R W ALARM 0 Disable 1 Enable 1 R Read as 0 0 PAGE R W PAGE selection 0 Selects Page0 1 Selects Page1 Note 1 A read modify write operation cannot be performed Note 2 To set interrupt enable bits to ENATMR ENAALM and INTENA you must follow the ord...

Page 430: ... it indicates that the execution is finished 4 RSTALM R W 0 Don t care 1 Alarm reset Initializes alarm registers Minute column hour column day column and day of the week column as follows MInute 00 Hour 00 Day 01 Day of the week Sunday 3 R Read as 0 2 DIS2HZ R W 2 Hz 0 Enable 1 Disable 1 DIS4HZ R W 4 Hz 0 Enable 1 Disable 0 DIS8HZ R W 8 Hz 0 Enable 1 Disable Note A read modify write operation cann...

Page 431: ... DIS1HZ DIS2HZ DIS4HZ DIS8HZ DIS16HZ RTCPAGER ENAALM Interrupt source signal 1 1 1 1 1 1 ALARM 0 1 1 1 1 0 1 Hz 1 0 1 1 1 0 2 Hz 1 1 0 1 1 0 4Hz 1 1 1 0 1 0 8Hz 1 1 1 1 0 0 16 Hz Others Interrupt not generated TMPM3V6 M3V4 Page 409 2019 02 06 ...

Page 432: ... incorrectly if the internal counter operates car ry during reading To ensure correct data reading read the clock data twice as shown below A pair of data read successively needs to match Start RTCPAGER PAGE 0 then select PAGE0 Clock data reading 1st Clock data reading 2nd 1st data 2nd data End NO YES Figure 17 2 Flowchart of the clock data reading 17 4 2 Writing clock data A carry during writing ...

Page 433: ... reset counter RTCRESTR DIS1HZ 0 then enable 1Hz interrupt NO YES Figure 17 3 Flowchart of the clock data writing 3 Disabling the clock Writing 0 to RTCPAGER ENATMR disables clock operation including a carry Stop the clock after the 1Hz interrupt The second counter keeps counting Set the clock again and enable the clock within one second before next 1Hz interrupt Start Disabling clock End Writing ...

Page 434: ...ting registers setting the RTCPAGER ADJUST bit or setting the RTCRESTR RSTTMR bit wait for one second for an interrupt to be generated 2 After changing the clock setting registers setting the RTCPAGER ADJUST bit or setting the RTCRESTR RSTTMR bit read the corresponding clock register values ADJUST or RSTTMR to make sure that the setting you have made is reflected TMPM3V6 M3V4 17 Real Time Clock RT...

Page 435: ...nitialize the alarm with alarm prohibited Write 1 to RTCRESTR RSTALM It makes the alarm setting to be 00 minute 00 hour 01 day and Sunday Setting alarm for min hour date and day is done by writing data to the relevant PAGE1 register Enable the alarm with the RTCPAGER ENAALM bit Enable the interrupt with the RTCPAGER INTE NA bit The following is an example program for outputting an alarm from the A...

Page 436: ...M and RTCRESTR are set as Table 17 3 and then RTCPAGER INTENA 1 is set one cycle low speed 1 Hz 2 Hz 4 Hz 8 Hz or 16 Hz low pulse is output to ALARM pin At the same time INTRTC interrupt is also output TMPM3V6 M3V4 17 Real Time Clock RTC 17 5 Alarm function Page 414 2019 02 06 ...

Page 437: ...ares a voltage divided by the ladder resistor with a reference voltage generated in the refer ence voltage generation circuit in the comparator Power on counter Power on detect signal Power on reset signal VLTD reset signal Supply voltage Supply voltage Reference voltage generation circuit Detect voltage selection circuit Reset detect signal 5 6 7 VDCR VDEN 9s 9 Figure 18 1 Power on reset circuit ...

Page 438: ... ms has elapsed the internal reset signal is released During the internal reset signal generation the CPU and the peripheral functions are reset When a reset input pin is not used supply voltage must be raised to the VLTD detect voltage until the internal reset releasing If power supply voltage does not reach to the VLTD detect voltage during this period TMPM3V6 3V4 cannot operate properly Since i...

Page 439: ...ec tion circuit a comparator and control registers The supply voltage is divided by the ladder resistor and input to the detection voltage selection circuit The detec tion voltage selection circuit selects a voltage according to the specified detection voltage 4 1 0 2V and the com parator compares it with the reference voltage When the supply voltage becomes lower than the detection voltage 4 1 0 ...

Page 440: ... 19 18 17 16 bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol VDEN After reset 0 0 0 0 0 0 1 1 Bit Bit Symbol Type Function 31 3 R Read as 0 2 1 R W Write 01 0 VDEN R W Low voltage detection operation 0 Disabled 1 Enabled Note VDCR is initialized by a power on reset or an external reset input TMPM3V6 M3V4 19 Low Voltage ...

Page 441: ...eration Setting it to 0 disables the op eration VDCR VDEN is set to 1 immediately after a power on reset or a reset by an external reset input is released Note When the supply voltage is lower than the detection voltage 4 1 0 2V setting VDCR VDEN to 1 generates reset signal at the time 19 3 2 2 Selecting the detection voltage level A detection voltage is 4 1 0 2V tVDPW TPORPW tVDDT1 tVDDT2 tVDDT2 ...

Page 442: ...e 40 tVDDT2 Voltage detection releasing time 40 tVDPW Voltage detection minimum pulse width 45 LDLVL Detection voltage 3 9 4 1 4 3 V Symbol Parameter Min Typ Max Unit Symbol Parameter Min Typ Max Unit tPWUP Power on Counter 213 fOSC2 s tPORPW Power on reset minimum pulse time tPORDT2 Power on Reset detection response time 30 45 tPORDT1 Power on Reset release response time 30 μs ...

Page 443: ... stops a reset signal is generated too TMPM3V6 M3V4 uses internal high speed oscillator clock as a reference and the target clock is an external high speed oscillator clock Note It is not guaranteed that OFD can detect all defects at any time and it is not a circuit to measure error frequen cy 20 1 Block diagram IHOSC Reference clock intended detection clock Oscillation Frequency Detection circuit...

Page 444: ...0004 Lower detection frequency setting register OFDMN 0x0008 Reserved 0x000C Higher detection frequency setting register OFDMX 0x0010 Reserved 0x0014 Reset control register OFDRST 0x0018 Status register OFDSTAT 0x001C Note Access to the Reserved area is prohibited TMPM3V6 M3V4 20 Oscillation Frequency Detector OFD 20 2 Registers Page 422 2019 02 06 ...

Page 445: ...0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol OFDWEN After reset 0 0 0 0 0 1 1 0 Bit Bit Symbol Type Description 31 8 R Read as 0 7 0 OFDWEN 7 0 R W Controls register write 0x06 Disable 0xF9 Enable Setting 0xF9 enables to write registers except OFDCR1 When writing a value except 0x06 or 0xF9 0x06 is written If writing register is disabled reading from each register is enabled TMPM3V6 M3V4 Page 423 20...

Page 446: ...bit symbol After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol OFDEN After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Description 31 8 R Read as 0 7 0 OFDEN 7 0 R W Controls frequency detecting 0x00 Disable 0xE4 Enable Writing a value except 0x00 or 0xE4 is invalid and a value will not be changed TMPM3V6 M3V4 20 Oscillation Frequency Detector OFD 20 2 Registers Page 424 2019 02 06 ...

Page 447: ...y Note Writing to the register of OFDMN is protected while OFD circuit is operating 20 2 1 4 OFDMX Higher detection frequency setting register 31 30 29 28 27 26 25 24 bit symbol After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol OFDMX After reset 0 0 0 0 0 0 0 0 Bit Bit S...

Page 448: ... 8 bit symbol After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol OFDRSTEN After reset 0 0 0 0 0 0 0 1 Bit Bit Symbol Type Description 31 1 R Read as 0 0 OFDRSTEN R W Controls generating a reset 0 Disable 1 Enable Note Writing to the register of OFDRST is protected while OFD circuit is operating TMPM3V6 M3V4 20 Oscillation Frequency Detector OFD 20 2 Registers Page 426 2019 02 06 ...

Page 449: ... After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol OFDBUSY FRQERR After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Description 31 2 R Read as 0 1 OFDBUSY R OFD operation 0 Stop 1 Run 0 FRQERR R Error detecting flag 0 No Error 1 Error TMPM3V6 M3V4 Page 427 2019 02 06 ...

Page 450: ...confirm whether it is operating Detecting cycle is reference clock frequen cy 28 MHz When generating reset is enabled the reset is generated if the following condition is satisfied When a target clock frequency is over than the range of a frequency which is specified by OFDMX and OFDMN When the reference clock stops When generating reset is disabled OFDSTAT FRQERR can be confirmed the condition No...

Page 451: ...FDMX is shown below when the target clock error is 10 and the reference clock error is 5 target clock fEHOSC 10MHz 10 Max 11MHz a Min 9MHz b reference clock fIHOSC 10MHz 5 Max 10 5MHz c Min 9 5MHz d higher limit of the detection frequency 1 d 28 a 4 lower limit of the detection frequency 1 c 28 b 4 higher limit of the detection frequency 1 9 5 106 28 11 106 4 74 10 74 truncate after the decimal pl...

Page 452: ...ere is not abnormal sta tus change to external oscillation clock Reset Enable external oscillation setting Enable write register OFDCR1 0xF9 OFDSTAT OFDBUSY 1 Error operation yes no CGRSTFLG OFDRSTF 0 OFDSTAT FRQERR 1 no Error operation yes no yes Disable reset output OFDRST 0 OFD setting OFDMN OFDMX Enable OFD operation OFDCR2 0xE4 Disable OFD operation OFDCR2 0x00 Enable reset output OFDRST 1 En...

Page 453: ...rnal peripheral devices from the watch dog timer pin WDTOUT by outputting Low Note This product does not have the watchdog timer out pin WDTOUT 21 1 Configuration Figure 21 1shows the block diagram of the watchdog timer WDMOD RESCR To internal reset RESET pin Watchdog timer out control WDTOUT Q R S Selector Binary counter 2 15 fsys 2 17 fsys 2 19 fsys 2 21 fsys 2 23 fsys 2 25 fsys WDMOD fsys WDMOD...

Page 454: ...it symbol WDTE WDTP I2WDT RESCR After reset 1 0 0 0 0 0 1 0 Bit Bit Symbol Type Function 31 8 R Read as 0 7 WDTE R W Enable Disable control 0 Disable 1 Enable 6 4 WDTP 2 0 R W Selects WDT detection time Refer toTable 21 1 000 215 fsys 001 217 fsys 010 219 fsys 011 221 fsys 100 223 fsys 101 225 fsys 110 Setting prohibited 111 Setting prohibited 3 R Read as 0 2 I2WDT R W Operation when IDLE mode 0 S...

Page 455: ... 0 82 ms 3 28 ms 13 11 ms 52 43 ms 209 72 ms 838 86 ms 100 fc 2 1 63 ms 6 55 ms 26 21 ms 104 86 ms 419 43 ms 1 68 s 101 fc 4 3 28 ms 13 11 ms 52 43 ms 209 72 ms 838 86 ms 3 36 s 110 fc 8 6 55 ms 26 21 ms 104 86 ms 419 43 ms 1 68 s 6 71 s 111 fc 16 13 12 ms 52 43 ms 209 72 ms 838 86 ms 3 36 s 13 42 s TMPM3V6 M3V4 Page 433 2019 02 06 ...

Page 456: ... symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol WDCR After reset Bit Bit Symbol Type Function 31 8 R Read as 0 7 0 WDCR W Disable Clear code 0xB1 Disable code 0x4E Clear code Others Reserved TMPM3V6 M3V4 21 Watchdog Timer WDT 21 2 Register Page 434 2019 02 06 ...

Page 457: ... Thus CPU detects malfunc tion runway malfunction countermeasure program is performed to return to the normal operation Additionally it is possible to resolve the problem of a malfunction runaway of the CPU by connecting the watchdog timer out pin to reset pins of peripheral devices Note This product does not include a watchdog timer out pin WDTOUT 21 3 2 Operation Mode and Status The watchdog tim...

Page 458: ... the plural CGNMIFLG identifies the factor of non maskable inter rupts In the case of INTWDT interrupt CGNMIFLG NMIFLG0 is set When INTWDT interrupt generates simultaneously the watchdog timer out WDTOUT output Low WDTOUT becomes High by the watchdog timer clearing that is writing clear code 0x4E to the WDCR reg ister Note This product does not have the watchdog timer output pin WDTOUT n Overflow ...

Page 459: ... the binary counter In this case reset status continues for 32 states A clock is initialized so that input clock fsys is the same as a internal high speed frequency clock fosc This means fsys fosc n 32 state WDTOUT Overflow WDT counter Internal reset INTWDT Figure 21 3 Internal reset generation TMPM3V6 M3V4 Page 437 2019 02 06 ...

Page 460: ...error writing by the malfunction first WDTE bit is set to 0 and then the disable code 0xB1 must be written to WDCR register To change the status of the watchdog timer from disable to enable set the WDTE bit to 1 3 Watchdog timer out reset connection RESCR This register specifies whether WDTOUT is used for internal reset or interrupt After reset WDMOD RESCR is initialized to 1 the internal reset is...

Page 461: ...the disable code 0xB1 21 5 3 2 Enabling control Set WDMOD WDTE to 1 7 6 5 4 3 2 1 0 WDMOD 1 Set WDTE to 1 21 5 3 3 Watchdog timer clearing control Writing the clear code 0x4E to the WDCR register clears the binary counter and it restarts counting 7 6 5 4 3 2 1 0 WDCR 0 1 0 0 1 1 1 0 Writes the clear code 0x4E 21 5 3 4 Detection time of watchdog timer In the case that 221 fsys is used set 011 to WD...

Page 462: ...TMPM3V6 M3V4 21 Watchdog Timer WDT 21 5 Control register Page 440 2019 02 06 ...

Page 463: ...sec Note The above values are theoretical values not including data transfer time The write time per chip depends on the write method used by a user Single Boot Mode User Boot Mode Page Configuration 32 ZRUGV 256 32K bytes BLOCK2 32K bytes BLOCK1 32K bytes BLOCK0 32K bytes BLOCK3 32 ZRUGV 256 32 ZRUGV 256 32 ZRUGV 256 0x3F81_8000 0x3F81_0000 0x0001_8000 0x0001_0000 0x3F80_8000 0x0000_8000 0x3F80_0...

Page 464: ... 22 1 5 Pro tect Security Function 22 1 2 Function Flash memory built in this device is generally compliant with the JEDEC standards except for some specif ic functions Therefore if a user is currently using a flash memory as an external memory it is easy to imple ment the functions into this device Furthermore to provide easy write or erase operation this product con tains a dedicated circuit to ...

Page 465: ...or switching Normal mode User boot mode RESET On board programming mode Single chip mode Single boot mode selected by the level of the BOOT pin when reset is released Figure 22 3 Mode transition TMPM3V6 M3V4 Page 443 2019 02 06 ...

Page 466: ...t up from the built in BOOT ROM Mask ROM after reset The BOOT ROM contains the algorithm that can rewrite Flash memory via serial port of this de vice on the user s set With connecting the serial port to external host data transfer is performed in above mentioned protocol and re programmed Flash memory 3 On board programming mode The user boot mode and single boot mode are the modes where flash me...

Page 467: ...FFFF single chip mode 0x3F80_0000 to 0x3F81_FFFF single boot mode 0x2000_0000 to 0x2000_27FF 64KB 8KB 0x0000_0000 to 0x0000_FFFF single chip mode 0x3F80_0000 to 0x3F80_FFFF single boot mode 0x2000_0000 to 0x2000_1FFF 0xFFFF_FFFF 6LQJOH KLS 0RGH Internal RAM 10 KB Internal Flash ROM 128 KB 0x2000_27FF 0x2000_0000 0x0001_FFFF 0x0000_0000 0xFFFF_FFFF 6LQJOH RRW 0RGH Internal RAM 10 KB Internal BOOT R...

Page 468: ...ons on debug functions 22 1 5 1 Protect Function This function inhibits the write erase operation per block To enable the protect function a protect bit corresponding to a block is set to 1 using the protect bit pro gram command If a protect bit is set to 0 using the protect bit erase command a block protect can be can celled The protect bit can be monitored with FCPSRA BLK 3 0 A program of protec...

Page 469: ...ations when the security function is enabled Item Description Read flash memory CPU can read flash memory Debug port JTAG serial wire or trace communication is disabled Command execution to Flash memory Command write to flash memory is not accepted If a user tries to erase a protect bit chip erase is executed and all protect bits are erased The security function is enabled under the following cond...

Page 470: ...egister 31 30 29 28 27 26 25 24 bit symbol After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol SECBIT After reset 0 0 0 0 0 0 0 1 Bit Bit Symbol Type Function 31 1 R Read as 0 0 SECBIT R W Security bit 0 Security function setting is disabled 1 Security function setting is ...

Page 471: ...instruction Buffer Note 1 0 Enable Instruction Buffer 1 Disable Instruction Buffer with Buffer clear This bit is a functional bit for controlling the Flash Interface To use Instruction Buffer set 0 To not use Instruction Buffer set to 1 In TMPM3V6 M3V4 it must be set 0 for Flash accessing Note 1 In TMPM3V6 M3V4 after Flash programming or Flash Erasing it should be Clearing Instruction buffer by th...

Page 472: ...bit outputs 0 to indicate that flash memory is busy Once auto operation is finished this bit becomes ready state and outputs 1 Then next command is accepted If a result of auto operation is failed this bit outputs 0 continuously The bit returns to 1 by hardware re set Note 1 Make sure that flash memory is ready before commands are issued If a command is issued during busy not only the command is n...

Page 473: ...pond to the protection status Note 2 BLK3 BLK2 can not be used in FLASH 64KB version 22 1 6 6 FCPMRA Flash protect mask register 31 30 29 28 27 26 25 24 bit symbol After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol BLKM3 BLKM2 BLKM1 BLKM0 After reset 0 0 0 0 1 1 1 1 Bit B...

Page 474: ...the Flash memory Note 3 When FCPMRA BLKM3 to BLKM0 are modified read the register again to check whether the Flash is re written Then access the Flash memory Note 4 BLKM3 BLKM2 can not be used in FLASH 64KB version TMPM3V6 M3V4 22 Flash Memory Operation 22 1 Features Page 452 2019 02 06 ...

Page 475: ...0 μs or more before read ing data from Flash memory or starting instruction fetch 22 2 2 Operation Mode of Flash Memory Flash memory provides mainly two types of operation modes The mode to read memory data Read mode The mode to erase or rewrite memory data automatically Automatic operation mode After power on after rest or after automatic operation mode is finished normally Flash memory becomes r...

Page 476: ...to 0 When the automatic operation normally ends FCSR RDY_BSY 1 is set and Flash memory returns to the read mode New command sequences are not accepted during the automatic operation If you want to stop the com mand operation use a hardware reset In case that the automatic operation abnormally ends FCSR RDY_BSY remains 0 Flash memory remains locked and will not return to the read mode To re turns t...

Page 477: ...a of the page are written On and after 5th bus cy cle one page data will be written sequentially Data is written in one word unit 32 bit If a part of the page is written set 0xFFFFFFFF as data which means not required to write for entire one page No automatic verify operation is performed internally in the device So be sure to read the data pro grammed to confirm that it has been correctly written...

Page 478: ...otect bit program command In the 7th bus write cycle the protect bit to be written is specified After the command sequence is input the au tomatic protect bit program starts Check whether write operation is normally terminated with FCPSRA BLK3 to BLK0 22 2 5 5 Auto Protect Bit Erase 1 Operation Description The automatic protect bit erase command operation depends on the security status For detail ...

Page 479: ... specified After the 4th bus write cycle read operation in the arbitrary flash area ac quires codes The ID Read can be executed successively The 4th bus write cycle and reading ID value can be exe cuted repeatedly The ID Read command does not automatically return to the read mode To return to the read mode execute the read command read reset command or hardware reset 22 2 5 7 Read Command and Read...

Page 480: ...h bus cycle 5th bus cycle 6th bus cycle 7th bus cycle Addr Addr Addr Addr Addr Addr Addr Data Data Data Data Data Data Data Read 0xXX 0xF0 Read reset 0xX55X 0xXAAX 0xX55X 0xAA 0x55 0xF0 ID Read 0xX55X 0xXAAX 0xX55X IA 0xXX 0xAA 0x55 0x90 0x00 ID Automatic page program 0xX55X 0xXAAX 0xX55X PA PA PA PA 0xAA 0x55 0xA0 PD0 PD1 PD2 PD3 Automatic chip erase 0xX55X 0xXAAX 0xX55X 0xX55X 0xXAAX 0xX55X 0xAA...

Page 481: ...ock erase Block address Table 22 7 Addr 1 0 0 fixed Other bits 0 recommended Automatic page pro gram PA Program page address Setting of the 4th bus write cycle address for page program Page address Addr 1 0 0 fixed Other bits 0 recommended Protect bit program PBA Protect bit address Setting of the 7th bus write cycle address for protect bit program Flash area Fix to 0 Protect bit selection Table 2...

Page 482: ...ddress 7 Block0 BLK0 Fix to 0 0 0 0x0000_0000 0x3F80_0000 Block1 BLK1 0 1 0x0000_0080 0x3F80_0080 Block2 BLK2 Fix to 0 1 0 0x0000_0100 0x3F80_0100 Block3 BLK3 1 1 0x0000_0180 0x3F80_0180 22 2 6 5 ID Read Code IA ID Table 22 9 shows how to specify a code and the content using ID Read command The column of address example indicates an address described in the upper side is used in the use boot mode ...

Page 483: ...0000_0550 Data 0x0000_00AA 0x0000_0055 0x0000_006A 0x0000_00AA 0x0000_0055 0x0000_006A 0x0000_006A 2 Data single boot mode Command Bus cycle 1 2 3 4 5 6 7 Read Address 0x3F80_0000 Data 0x0000_00F0 Read reset Address 0x3F80_0550 0x3F80_0AA0 0x3F80_0550 Data 0x0000_00AA 0x3F80_0055 0x3F80_00F0 ID Read Address 0x3F80_0550 0x3F80_0AA0 0x3F80_0550 IA 0x0000_0000 Data 0x0000_00AA 0x0000_0055 0x0000_0090...

Page 484: ...ogramming Address Address 0x80 set by a page NO Automatic Page Programming Command Sequence Address Command 0x0000_0054xx 0x0000_00AA 0x0000_AAxx 0x0000_0055 0x0000_0054xx 0x0000_00A0 Programming address page address Programming data 32 bit data Figure 22 6 Flowchart of automatic program TMPM3V6 M3V4 22 Flash Memory Operation 22 2 Detail of Flash Memory Page 462 2019 02 06 ...

Page 485: ...00_00AA 0x0000_0AA0 0x0000_0055 0x0000_0550 0x0000_0080 0x0000_0550 0x0000_00AA 0x0000_0AA0 0x0000_0055 0x0000_0550 0x0000_0010 Automatic block erase command sequence address command 0x0000_0540 0x0000_00AA 0x0000_0AA0 0x0000_0055 0x0000_0550 0x0000_0080 0x0000_0550 0x0000_00AA 0x0000_0AA0 0x0000_0055 Block address 0x0000_0030 Figure 22 7 Flowchart of automatic erase TMPM3V6 M3V4 Page 463 2019 02 ...

Page 486: ...is for the single boot mode setting BOOT 0 RESET 0 1 While BOOT pin is set to the above in advance set RESET pin to 0 Then release RESET pin the de vice will boot up in the single boot mode 22 3 2 Interface Specification This section describes UART communication format in the single boot mode The serial operation sup ports UART asynchronous communication modes In order to execute the on board prog...

Page 487: ...s erased data 0xFF it is difficult to protect data secure due to an easy to guess pass word Even if the single boot mode is not used it is recommended to set a unique value as a password 22 3 4 Operation Command The boot program provides the following operation commands Table 22 12 Operation command data Operation command da ta Operation mode 0x10 RAM transfer 0x40 Flash memory chip erase and prot...

Page 488: ...the re ceive pin s level is changed Consequently the timer values of tAB tAC and tAD have a margin of er ror In addition note that if the transfer goes at a high baud rate the CPU may not be able to determine the level of receive pin The flowchart in Figure 22 10 shows the serial operation mode is determined that the time length of the receive pin is long or short If the length is tAB tCD the seri...

Page 489: ...igh to low transition on serial receive pin Software capture and save timer value tAC YES Low to high transition on serial receive pin Software capture and save timer value tAD YES 16 bit Timer 0 stops counting WAC Ӎ tAD Make backup copy of tAD value Point A Point B Point C Point D Done Stop operation infinite loop waiting for RESET YES Figure 22 9 Serial operation mode receive flowchart TMPM3V6 M...

Page 490: ...ote Note When the serial operation is determined as UART if the baud rate setting is determined as unaccept able the boot program aborts without sending back any response Table 22 14 ACK response to the operation command data Transmit data Description 0x 8 Note A receive error occurs in the operation command data 0x 1 Note An undefined operation command data is received normally 0x10 Determined as...

Page 491: ...password verification only when neces sity judging is determined as required Password requirement setting Data Need password Other than 0xFF No password 0xFF If a password is set to 0xFF erased data it is difficult to protect data securely due to an easy to guess password Even if Single Boot mode is not used it is recommended to set a unique value as a password 1 Password verification using RAM tr...

Page 492: ...f receive data password data A password er ror occurs if all 12 bytes do not match If the password error is determined an ACK response data to the 17th of CHECK SUM data is a password error The password verification is performed even if the security function is enabled Start Need password YES Are all bytes the same Password area error Password area is normal YES Figure 22 12 Password area check fl...

Page 493: ...es of 0xE5 and 0xF6 perform 8 bit addition 0xE5 0xF6 0x1DB Take the two s complement of the sum to the lower 8 bit and that is a checksum value So the boot pro gram sends 0x25 to the controller 0 0xDB 0x25 TMPM3V6 M3V4 Page 471 2019 02 06 ...

Page 494: ...T ACK response to operation command Normal state 0x10 Abnormal state 0xX1 Communication error 0xX8 ACK response data to the operation command First checks if 3rd byte of receive data has errors UART mode only If receive er rors exist sends a ACK response data 0xX8 that means abnormal communica tions and waits for a next operation command 3rd byte Upper 4 bits of transmit da ta are undefined same a...

Page 495: ... bytes Specify the data to be stored in the address from 0x2000_0400 through the last address of RAM 24 C T Number of RAM store bytes 7 to 0 25 C T 19th to 24th byte of CHECK SUM value Send 19th byte to 24th byte of CHECK SUM values 26 C T ACK response to CHECK SUM value Normal state 0x10 Abnormal state 0x11 Communication error 0x18 First checks if 19th byte to 25th byte of receive data have error...

Page 496: ...ponse to the operation command Normal state 0x40 Abnormal state 0xX1 Communication error 0xX8 ACK response data to the operation command First checks if 3rd byte of receive data has errors UART mode only If receive er rors exist sends a ACK response data 0xX8 that means abnormal communica tions and waits for a next operation command 3rd byte Upper 4 bits of transmit da ta are undefined same as upp...

Page 497: ...rmal state 0xX1 Communication error 0x58 First checks if 19th byte of receive data has errors If receive errors exist sends a ACK response data bit 3 0x58 that means abnormal communication and waits for next operation command 3rd byte Then if 19th byte of receive data corresponds to the erase enable command re ceive data is echoed back normal ACK response data In this case 0x54 is ech oed back and...

Page 498: ... data Received data 0x40 Transmission routine Send 0x40 normal response Chip erase processing YES 0x40 ACK data ACK data 0x08 Transmission routine Send 0xX8 receive error Yes ACK data Received data 0x01 Command error Transmission routine Send 0xX1 Command error Processed normally Jump to RAM Yes normally Baud rate setting ACK data received data 0x86 Can be set Send 0x86 Normal response Stop operat...

Page 499: ... the host New application program code Flash memory Host I O RAM Boot ROM Old application program code or erased state SIO a Programming routine TMPM3V6 M3V4 22 3 9 2 Step 2 Release the reset by pin condition setting in the boot mode and boot up the BOOT ROM According to the procedure of boot mode transfer the programming routine a via SIO0 UART0 from the source host A password verification with t...

Page 500: ...code or erased state SIO a Programming routine a Programming routine TMPM3V6 M3V4 22 3 9 4 Step 4 The boot program jumps to the programming routine a in the on chip RAM to erase the flash block con taining old application program codes The Block Erase or Chip Erase command is be used New application Program code Flash memory Host I O RAM Boot ROM SIO a Programming routine a Programming routine Era...

Page 501: ...transfer path and the source of the transfer Create a hardware board and programming routine to suit your particular needs New application Program code Flash memory Host I O RAM Boot ROM SIO a Programming routine a Programming routine New application program code TMPM3V6 M3V4 22 3 9 6 Step 6 When programming of Flash memory is complete power off the board and disconnect the cable lead ing from the...

Page 502: ... except reset to avoid abnor mal termination during the user boot mode Taking examples from two cases such as the method that reprogramming routine stored in Flash memory 1 A and transferred from the external device 1 B the following section explains the procedure For a detail of the pro gram erase to Flash memory refer to 22 2 Detail of Flash Memory 22 4 1 1 A Procedure that a Programming Routine...

Page 503: ...cedure a Mode Judgment Routine b Programming routine c Copy routine 0 1 RESET Conditions for entering User Boot mode defined by the user TMPM3V6 M3V4 22 4 1 3 Step 3 Once the device enters the user boot mode execute the copy routine C to download the flash program ming routine b from the host controller to the built in RAM New Application Program Code Old Application Program Code Flash memory Host...

Page 504: ...p 5 Continue to execute the flash programming routine to download new program data from the host control ler and program it into the erased flash block When the programming is complete the write erase protec tion of that flash block in the user program area must be set New Application Program Code New Application Program Code Flash memory Host I O RAM Reset procedure a Mode judgment routine b Prog...

Page 505: ...de After reset the CPU will start along with the new application program New application program code Flash memory Host I O RAM Reset procedure a Mode judgment routine b Programming routine c Copy routine 0 1 RESET Set to normal mode TMPM3V6 M3V4 TMPM3V6 M3V4 Page 483 2019 02 06 ...

Page 506: ...ent such as a flash writer a Mode determination routine A program to determine to switch to reprogramming operation b Transfer routine A program to obtain a reprogramming program from the external device In addition prepare a reprogramming routine shown below must be stored on the host controller c Reprogramming routine A program to reprogram data New application program code Flash memory Host I O...

Page 507: ... Transfer routine Old application program code c Programming routine 0 1 RESET Conditions for entering User Boot mode defined by the user TMPM3V6 M3V4 22 4 2 3 Step 3 Once the device enters the user boot mode execute the transfer routine b to download the program ming routine c from the host controller to the built in RAM New application Program code Flash memory Host I O RAM Reset procedure a Mod...

Page 508: ... 5 Continue to execute the flash programming routine c to download new program data from the host con troller and program it into the erased flash block When the programming is complete the write erase pro tection of that flash block in the user program area must be set New application program code Flash memory Host I O RAM Reset procedure a Mode judgment routine b Transfer routine New application...

Page 509: ...normal mode After reset the CPU will start along with the new application program Flash memory Host I O RAM Reset procedure a Mode judgment routine b Transfer routine New application program code 0 1 RESET Set to normal mode TMPM3V6 M3V4 TMPM3V6 M3V4 Page 487 2019 02 06 ...

Page 510: ...TMPM3V6 M3V4 22 Flash Memory Operation 22 4 Programming in the User Boot Mode Page 488 2019 02 06 ...

Page 511: ... pins TRACEDATA 1 0 SWV for the debugging via the on chip Trace Port Interface Unit TPIU For details about SWJ DP ETM and TPIU refer to the Arm manual Cortex M3 Technical Reference Manual 23 2 SWJ DP SWJ DP supports the Serial Wire Debug Port SWCLK SWDIO and the JTAG Debug Port TDI TDO TMS TCK TRST 23 3 ETM ETM supports two data signal pins TRACEDATA 1 0 one clock signal pin TRACECLK and trace out...

Page 512: ...e configured as debug port function pins The functions of oth er debug interface pins need to be programmed as required When using a low power consumption mode take note of the following points Note 1 If PB3 and PB5 are configured as TMS SWDIO and TDO SWV output continues to be enabled even in STOP mode re gardless of the setting of the CGSTBYCR DRVE bit Note 2 If PB4 is configured as a debug func...

Page 513: ... Peripheral Functions in Halt Mode When the Cortex M3 core enters in the halt mode the watchdog timer WDT automatically stops Other periph eral functions continue to operate TMPM3V6 M3V4 Page 491 2019 02 06 ...

Page 514: ... impossible Please note that it is necessary to prepare for the structure which changes the general purpose port to the de bugging interface function by some kind of methods to connect a debugging tool again Table 23 3 Example Table of using debug interface pins Debug interface pins TRST TDI TDO SWV TCK SWCLK TMS SWDIO TRACE DATA 1 0 TRACE CLK JTAG SW After reset ο ο ο ο ο JTAG SW without TRST Not...

Page 515: ... PB0 to 7 PC0 to 7 PD0 to 6 PE0 to 7 PF0 to 4 PG0 to 7 PL2 PN0 to 7 Output Data P ch Output Enable Input Data Input Enable N ch I O port Open drain Enable Schmitt Programmable Pull down Resistor Programmable Pull up Resistor Pull down Enable Pull up Enable 24 2 PH0 to 7 PI0 to 1 PJ0 to 7 Output Data P ch Output Enable Input Data Input Enable N ch Open drain Enable Schmitt Pull down Enable Pull up ...

Page 516: ...own Resistor Programmable Pull up Resistor 24 4 PM0 to 1 PP0 to 1 Output Data P ch Output Enable Input Data Input Enable N ch Open drain Enable Schmitt Pull down Enable Pull up Enable Input AIN I O port Programmable Pull down Resistor Programmable Pull up Resistor TMPM3V6 M3V4 24 Port Section Equivalent Circuit Schematic 24 3 PL0 Page 494 2019 02 06 ...

Page 517: ... Enable Clock 500kΩ typ 24 6 XT1 XT2 XT1 XT2 120kΩ typ Oscillator Circuit Low frequency Oscillation Enable Clock 20MΩ typ 24 7 RESET Reset Input Port Schmitt Pull up Resistor 24 8 MODE MODE Input Port Schmitt Note MODE pin is fixed to GND TMPM3V6 M3V4 Page 495 2019 02 06 ...

Page 518: ...EST3 Open Note FTEST3 pin is fixed to Open 24 10 VREFH VREFL VREFH VREFL ADC AVDD AVSS String Resistor AVDD5 VREFH AVSS VREFL TMPM3V6 M3V4 24 Port Section Equivalent Circuit Schematic 24 9 FTEST3 Page 496 2019 02 06 ...

Page 519: ...xcept during and debug Flash W E TOPR 40 to 85 C During Flash W E and debug 0 to 70 Note Absolute maximum ratings are limiting values of operating and environmental conditions which should not be exceeded under the worst possible conditions The equipment manufacturer should de sign so that no Absolute maximum rating value is exceeded with respect to current voltage power con sumption temperature e...

Page 520: ...2 AVDD5 3 9V IOL 1 6 mA 0 4 High level Output volt age PORT A B C D E F G L M N P VOH1 DVDD5 3 9V IOH 1 6 mA DVDD5 0 4 V PORT H I J VOH2 AVDD5 3 9V IOH 1 6 mA AVDD5 0 4 Input leakage current ILI 0 0 V VIN DVDD5 0 0 V VIN AVDD5 0 02 5 μA Output leakage current ILO 0 2 V VIN DVDD5 0 2 V 0 2 V VIN AVDD5 0 2 V 0 05 10 Pull up resistor at Reset RRST 3 9 V DVDD5 5 5 V 38 5 50 71 4 kΩ Schmitt trigger inp...

Page 521: ...M0 1 PP0 1 GrL4 PE6 7 PL2 PN0 7 20 mA ΣIOL2 Per group 3 9 V AVDD5 5 5 V GrL5 PH0 7 PI0 1 PJ0 7 9 mA ΣIOL Total all ports 30 mA High level output current IOH Per pin 2 mA ΣIOH1 Per group 3 9 V DVDD5 5 5 V GrH1 PA0 7 PE0 3 PG0 7 PM0 1 PP0 1 GrH2 PB0 7 PC0 7 PD0 6 PF0 4 PL0 GrH3 PE4 7 PL2 PN0 7 20 mA ΣIOH2 Per group 3 9 V AVDD5 5 5 V GrH4 PH0 7 PI0 1 PJ0 7 9 mA ΣIOH Total all ports 30 mA TMPM3V6 M3V4...

Page 522: ...therwise noted Note 2 Measurement condition of IDD NORMAL Execution program Dhrystone V2 1 built in FLASH operation All peripheral functions operate excluding A DC Note 3 Measurement condition of IDD IDLE CPU is stopped all peripheral functions operate excluding A DC Note 4 Measurement condition of IDD SLEEP All peripheral functions stopped CPU is stopped using RMC RTC only TMPM3V6 M3V4 25 Electri...

Page 523: ...onversion time 1 85 μs 9 LSB Note 2 DNL error 6 to 1 Offset error 5 Full scale error 8 to 2 Total error 12 to 8 INL error 10bit mode AIN resistance 600 Ω AIN load capacitance 0 1μF Conversion time 1 70 μs 3 LSB Note 3 DNL error 2 Offset error 3 Full scale error 3 Total error 4 Note 1 A D when using separate power supply for the converter you must keep this condition Note 2 1LSB AVDD5 AVSS 4096 V N...

Page 524: ...ax SCLK Clock High width input tSCH 4x 100 ns SCLK Clock Low width input tSCL 4x 100 SCLK cycle tSCY tSCH tSCL 200 Valid Data Input SCLK rise or fall Note 1 tSRD 30 30 SCLK rise or fall Input Data hold Note 1 tHSR x 30 55 Output Parameter Symbol Equation 40 MHz Unit Min Max Min Max SCLK Clock High width input tSCH 4x 120 Note 3 ns SCLK Clock Low width input tSCL 4x 120 Note 3 SCLK cycle tSCY tSCH ...

Page 525: ...S tSCY 2 20 30 SCLK rise Output Data hold tOHS tSCY 2 20 30 Valid Data Input SCLK rise tSRD 45 45 SCLK rise Input Data hold tHSR 0 0 0 1 2 3 1 VALID OUTPUT DATA TxD INPUT DATA RxD SCLK Output mode Rising edge input mode SCLK Falling edge input mode tOSS tSCY tSCH tSCL tOHS 0 tSRD 2 3 tHSR VALID VALID VALID TMPM3V6 M3V4 Page 503 2019 02 06 ...

Page 526: ... n 1 14 x On I2C bus specification maximum Speed of Standard Mode fast mode is 100kHz 400khz Internal SCL Frequency set ting should comply with fsys and Note1 Note2 shown above Note 3 The output data hold time is equal to 4x of internal SCL Note 4 The Philips I2C bus specification states that a device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined...

Page 527: ...x 100 ns SCK Clock Low width input tSCL 4x 100 SCK cycle tSCY 8x 200 Valid Data input SCK rise tSRD 30 x 5 SCK rise Input Data hold tHSR 2x 30 80 Output Parameter Symbol Equation 40 MHz Unit Min Max Min Max SCK Clock High width input tSCH 4x 120 Note 2 ns SCK Clock Low width input tSCL 4x 120 Note 2 SCK cycle tSCY 8x 240 Output Data SCK rise tOSS tSCY 2 3x 45 0 Note 1 SCK rise Output Data hold tOH...

Page 528: ...utput Data hold tOHS tSCY 2 20 180 Valid Data input SCK rise tSRD x 45 70 SCK rise Input Data hold tHSR 0 0 Note 1 SCK cycle after automatic wait becomes 14x Note 2 tOSS after automatic wait may be tSCY 2 x 20 0 1 2 3 1 VALID OUTPUT DATA SO INPUT DATA SI SCK tOSS tSCY tSCH tSCL tOHS 0 tSRD 2 3 tHSR VALID VALID VALID TMPM3V6 M3V4 25 Electrical Characteristics 25 6 AC Electrical Characteristics Page...

Page 529: ...M m T 2 20 0 30 Master mode SPCLK high level pulse width tWHM m T 2 20 0 30 Slave mode SPCLK low level pulse width tWLS n T 2 10 0 140 Slave mode SPCLK high level pulse width tWHS n T 2 10 0 140 Master mode SPCLK rise fall to output data valid tODSM 15 15 Master mode SPCLK rise fall to output data hold tODHM m T 2 15 35 Master mode SPCLK rise fall to input data valid delay time tIDSM 35 35 Master ...

Page 530: ... Master mode m CPSDVSR 1 SCR fsys SPCLK CPSDVSR is set only even number and m must set between the range of 65024 m 2 Slave mode n fsys SPCLK 65024 n 12 TMPM3V6 M3V4 25 Electrical Characteristics 25 6 AC Electrical Characteristics Page 508 2019 02 06 ...

Page 531: ...ate Internal Clock state tOFSM tWH tWL tr tf Tm tODHM tODSM tODSM tIDSM tIDHM SPCLK output Master SSPCR0 SPO 1 SPDO output SPDI input SPFSS output 2 Master SSPCR0 SPH 1 Data is latched on the second edge SPCLK output Master SSPCR0 SPO 1 tOFSM tWH tWL tr tf Tm tODHM tODSM tIDSM tIDHM SPCLK output Master SSPCR0 SPO 0 SPDO output SPDI input SPFSS output TMPM3V6 M3V4 Page 509 2019 02 06 ...

Page 532: ...f Ts tIDSS tODSS tODHS SPCLK input SSPCR0 SPO 1 SPDI input SPDO output SPFSS input tIDHS 4 Slave SSPCR0 SPH 1 Data is latched on the second edge SPCLK input SSPCR0 SPO 1 tOFSS tWH tWL tr tf Ts tIDHS tODSS tODHS SPCLK input SSPCR0 SPO 0 SPDI input SPDO output SPFSS input tIDSS TMPM3V6 M3V4 25 Electrical Characteristics 25 6 AC Electrical Characteristics Page 510 2019 02 06 ...

Page 533: ...It varies depending on the programming of the clock gear function Parameter Symbol Equation 40 MHz Unit Min Max Min Max Low level pulse width tCPL 2x 100 150 ns High level pulse width tCPH 2x 100 150 ns 25 6 7 External Interrupt In the table below the letter x represents the fsys cycle time 1 Except STOP release interrupts Parameter Symbol Equation 40 MHz Unit Min Max Min Max INT0 to F low level p...

Page 534: ...ax High level pulse width tSCH 0 5T 5 7 5 ns Low level pulse width tSCL 0 5T 5 7 5 ns Note In the above table the letter T represents the cycle time of the SCOUT output clock tSCH SCOUT tSCL TMPM3V6 M3V4 25 Electrical Characteristics 25 6 AC Electrical Characteristics Page 512 2019 02 06 ...

Page 535: ...rise Tds 20 CLK rise Input data hold Tdh 15 25 6 9 2 JTAG Interface Parameter Symbol Min Max Unit CLK cycle Tdck 100 ns CLK fall Output data hold Td3 4 CLK fall Output data valid Td4 37 Input data valid CLK rise Tds 20 CLK rise Input data hold Tdh 15 Tdck Td1 Td2 Td3 Td4 Tds Tdh CLK input SWCLK TCK Output data SWDIO Output data TDO Input data SWDIO TMS TDI TMPM3V6 M3V4 Page 513 2019 02 06 ...

Page 536: ...tsetupf ttclk tholdf tsetupr tholdr 25 6 11 On chip Oscillator Characteristic Parameter Symbol Condition Min Typ Max Unit Oscillation frequency IHOSC Ta 25 C 9 0 MHz Oscillation accuracy Ta 40 to 85 C 15 15 Note Do not use an on chip oscillator as a system clock fsys when high accuracy oscillation frequency is required 25 6 12 Flash Characteristic Parameter Condition Min Typ Max Unit Guaranteed nu...

Page 537: ... evaluate oscillation stability using the substrate you use The TX03 has been evaluated by the oscillator vender below Please refer this information when selecting exter nal parts 25 7 1 Ceramic Oscillator 25 7 2 Crystal Oscillator TMPM3V6 M3V4 Page 515 This product has been evaluated by the ceramic oscillator by Murata Manufacturing Co Ltd Please refer to the company s website for details This pr...

Page 538: ...TMPM3V6 M3V4 25 Electrical Characteristics 25 7 Recommended Oscillation Circuit Page 516 2019 02 06 ...

Page 539: ... 㻵㻺㻰㻱㼄 㻝 㻞㻡 㻞㻢 㻡㻜 㻡㻝 㻣㻡 㻣㻢 㻝㻜㻜 㻿 㻜㻚㻜㻤 㻿 㻝㻢㻚㻜㼼㻜㻚㻞 㻞 㻚 㻜 㼼 㻜 㻚 㻢 㻝 㻝㻠㻚㻜㼼㻜㻚㻝 㻝 㻚 㻜 㼼 㻜 㻚 㻠 㻝 㻜 㻚 㻝 㻕 㻔 㻝㻚㻜 㻔 㻕 㻜㻚㻡 㻜㻚㻞 㻗㻜㻚㻜㻣 㻙㻜㻚㻜㻟 㻡 㻜 㻚 㻜 㼼 㻝 㻚 㻜 㻠 㻚 㻝 㻡 㻝 㻚 㻜 㻗 㻡 㻜 㻚 㻜 㻙 㼄 㻭 㻹 㻣 㻚 㻝 㻜䡚㻤㼻 㻗㻜㻚㻜 㻣㻡 㻙㻜㻚㻜㻟 㻡 㻜㻚㻝㻞 㻡 㻡 㻞 㻚 㻜 㻜㻚㻡 㻔 㻕 㻜㻚㻠㻡䡚㻜㻚㻣㻡 LPHQVLRQV TMPM3V6 M3V4 Page 517 2019 02 06 ...

Page 540: ...26 2 TMPM3V6FWDFG Type QFP100 P 1420 0 65A Unit mm LPHQVLRQV TMPM3V6 M3V4 26 Package Dimensions 26 2 TMPM3V6FWDFG Page 518 2019 02 06 ...

Page 541: ...26 3 TMPM3V4FWUG TMPM3V4FSUG Type LQFP64 P 1010 0 50E LPHQVLRQV TMPM3V6 M3V4 Page 519 2019 02 06 ...

Page 542: ...26 4 TMPM3V4FWEFG TMPM3V4FSEFG Type QFP64 P 1414 0 80A Unit mm LPHQVLRQV TMPM3V6 M3V4 26 Package Dimensions 26 4 TMPM3V4FWEFG TMPM3V4FSEFG Page 520 2019 02 06 ...

Page 543: ... equipment used for automobiles trains ships and other transportation traffic signaling equipment equipment used to control combustions or explosions safety devices elevators and escalators and devices related to power plant IF YOU USE PRODUCT FOR UNINTENDED USE TOSHIBA ASSUMES NO LIABILITY FOR PRODUCT For details please contact your TOSHIBA sales representative or contact us via our website Do no...

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