Toshiba TMPM3V4, Manual

Page: 270 / 544

12.10.3.3 Transmit in I/O interface Mode with Clock Output Mode
In the I/O interface mode with clock output mode, the clock output automatically stops when all data trans-
mission is completed and underrun error will not occur.
The timing of suspension and resume of clock output is different depending on the buffer and FIFO us-
age.
(1) Single Buffer
The clock output stops each time one frame of data is transferred. Handshaking for each data
with the other side of communication can be enabled. The clock output resumes when the next data
is written in the buffer.
(2) Double Buffer
The clock output stops upon completion of data transmission in the transmit shift register and the
transmit buffer. The clock output resumes when the next data is written in the buffer.
(3) FIFO
The transmission of all data stored in the transmit shift register, transmit buffer and FIFO is comple-
ted, the SCLK output stops. The next data is written, clock output resumes.
If SCxFCNF<RXTXCNT> is configured, SCxMOD0<TXE> bit is cleared at the same time as
clock stops and the transmission stops.
12.10.3.4 Level of TXDx pin after the last bit is output in I/O interface mode
The level of TXDx pin after the data hold time is passed after the last bit is output is specified by
SCxCR<TIDLE>.
When SCxCR<TIDLE> is "00", the level of TXDx pin is output "Low" level. When SCxCR<TIDLE>
is "01", the level of TXDx pin is output "High" level. When SCxCR<TIDLE> is "10", the level of TXDx
pin is output the level of the last bit.
Low Low
High High
Keep the last bit Keep the last bit
SCLKx output
TXDx pin
(SCxCR<TIDLE[1:0]>="00")
TXDx pin
(SCxCR<TIDLE[1:0]>="01")
TXDx pin
(SCxCR<TIDLE[1:0]>="10")
Figure 12-9 Level of TXDx pin After the last bit is output
TMPM3V6/M3V4
12. Serial Channel with 4bytes FIFO (SIO/UART)
12.10 Transmit
Page 248
2019-02-06