Schweitzer Engineering Laboratories SEL-351-5, Instruction Manual

Page: 207 / 706

5.5
Date Code 20070117
Instruction Manual SEL-351-5, -6, -7 Relay
Trip and Target Logic
Trip Logic
Factory Settings
Example (Using
Setting TR)
If the “communications-assisted” and “switch-onto-fault” trip logic at the top
of
Figure 5.1 can effectively be ignored, the figure becomes a lot smaller.
Then SEL
OGIC
control equation trip setting TR is the only input into OR-1
gate and follows into the “seal-in and unlatch” logic for Relay Word bit TRIP.
The factory settings for the trip logic SEL
OGIC
control equation settings are:
TR = 51PT + 51GT + 81D1T + LB3 + 50P1 * SH0 + OC (trip conditions)
ULTR = !(51P + 51G) (unlatch trip conditions)
The factory setting for the Minimum Trip Duration Timer setting is:
TDURD =
9.00 cycles
See the settings sheets in Section 9: Setting the Relay for setting ranges.
Set Trip
In SEL
OGIC
control equation setting TR = 51PT + 51GT + 81D1T + LB3 +
50P1 * SH0 + OC:
➤
Time-overcurrent elements 51PT and 51GT trip directly. Time-
overcurrent and definite-time overcurrent elements can be
torque controlled (e.g., elements 51PT and 51GT are torque
controlled by SEL
OGIC
control equation settings 51PTC and
51GTC, respectively). Check torque control settings to see if
any control is applied to time-overcurrent and definite-time
overcurrent elements. Such control is not apparent by mere
inspection of trip setting TR or any other SEL
OGIC
control
equation trip setting.
➤
Frequency element 81D1T trips directly.
➤
Local bit LB3 trips directly (operates as a manual trip switch
via the front panel). See
Local Control Switches on page 7.6 for
more information on local bits.
➤
Phase instantaneous overcurrent element 50P1 is supervised by
Relay Word bit SH0 in an ANDed condition 50P1 * SH0.
Elements 50P1 can only generate a trip when SH0 = logical 1
(reclosing relay is at shot = 0). After the first trip in a reclose
cycle, the shot counter increments from 0 to 1, SH0 = logical 0,
and element 50P1 cannot generate a trip. See
Section 6: Close
and Reclose Logic for more information on reclosing relay
operation.
➤
Relay Word bit OC asserts for execution of the OPEN
command. See OPE Command (Open Breaker) on page 10.37
for more information on the OPEN command.
With setting TDURD = 9.00 cycles, once the TRIP Relay Word bit asserts via
SEL
OGIC
control equation setting TR, it remains asserted at logical 1 for a
minimum of 9 cycles.
Unlatch Trip
In SEL
OGIC
control equation setting
ULTR =
!(51P + 51G)
Both time-overcurrent element pickups 51P and 51G must be deasserted
before the trip logic unlatches and the TRIP Relay Word bit deasserts to
logical 0.