Schweitzer Engineering Laboratories SEL-351-5, Instruction Manual

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9.31
Date Code 20070117
Instruction Manual SEL-351-5, -6, -7 Relay
Setting the Relay
Relay Word Bits (Used in SEL
OGIC
Control Equations)
41 3PO Three pole open condition (see Figure 5.3 ) Testing
SOTFE Switch-onto-fault condition (see Figure 5.3 )
Z3RB Zone (level) 3 reverse block (see Figure 5.6 )
KEY Key permissive trip signal start (see Figure 5.6 )
EKEY Echo key (see Figure 5.6 )
ECTT Echo conversion to trip condition (see Figure 5.6 )
WFC Weak infeed condition (see Figure 5.6 )
PT Permissive trip signal to POTT logic (see Figure 5.5 )
42 PTRX2 Permissive trip 2 signal from DCUB logic (see Figure 5.10 )
PTRX Permissive trip signal to Trip logic (see Figure 5.7 )
PTRX1 Permissive trip 2 signal from DCUB logic (see Figure 5.10 )
UBB1 Unblocking block 1 from DCUB logic (see Figure 5.10 )
UBB2 Unblocking block 2 from DCUB logic (see Figure 5.10 )
UBB Unblocking block to Trip logic (see Figure 5.11 )
Z3XT Logic output from zone (level) 3 extension timer (see Figure 5.14 )
DSTRT Directional carrier start (see Figure 5.14 )
43 NSTRT Nondirectional carrier start (see Figure 5.14 )
STOP Carrier stop (see Figure 5.14 )
BTX Block trip input extension (see Figure 5.14 )
TRIP Trip logic output asserted (see Figure 5.1 ) Output contact assignment
OC
c
Asserts 1/4 cycle for OPEN command execution (see the Note following
Figure 5.2 and the Note in the Lockout State discussion, following Table 6.1 )
Testing
CC
c
Asserts 1/4 cycle for CLOSE command execution (see the Note in the Set
Close discussion, following Figure 6.1 )
DCHI Station dc battery instantaneous overvoltage element (see Figure 8.9 ) Indication
DCLO Station dc battery instantaneous undervoltage element (see Figure 8.9 )
44 67P2S Level 2 directional phase definite-time (short delay) overcurrent element
67P2S timed out (derived from 67P2; see
Figure 3.3 and Figure 5.14 )
Tripping in DCB schemes
67N2S Level 2 directional neutral ground definite-time (short delay) overcurrent ele-
ment 67N2S timed out (derived from 67N2; see
Figure 3.8 and Figure 5.14 )
67G2S Level 2 directional residual ground definite-time (short delay) overcurrent ele-
ment 67G2S timed out (derived from 67G2; see
Figure 3.10 and Figure 5.14 )
67Q2S Level 2 directional negative-sequence definite-time (short delay) overcurrent
element 67Q2S timed out (derived from 67Q2; see
Figure 3.12 and
Figure 5.14 )
PDEM Phase demand current above pickup setting PDEMP (see Figure 8.13 ) Indication
NDEM Neutral ground demand current above pickup setting NDEMP
(see
Figure 8.13 )
GDEM Residual ground demand current above pickup setting GDEMP
(see
Figure 8.13 )
QDEM Negative-sequence demand current above pickup setting QDEMP
(see
Figure 8.13 )
Table 9.6 Relay Word Bit Definitions for SEL-5, -6, -7 (Sheet 13 of 18)
Row Bit Definition Primary Application