Schweitzer Engineering Laboratories SEL-351-5, Instruction Manual

Page: 518 / 706

12.18
SEL-351-5, -6, -7 Relay Instruction Manual
Date Code 20070117
Standard Event Reports, Sag/Swell/Interruption Report, and SER
Standard 15/30-Cycle Event Reports
BTX BTX * Block trip input extension BTX asserted.
TMB A 12 TMB1A, TMB2A 1 M
IRRORED
B
ITS®
channel A transmit bit 1 TMB1A asserted.
2 M
IRRORED
B
ITS
channel A transmit bit 2 TMB2A asserted.
b Both TMB1A and TMB2A asserted.
TMB A 34 TMB3A, TMB4A 3 M
IRRORED
B
ITS
channel A transmit bit 3 TMB3A asserted.
4 M
IRRORED
B
ITS
channel A transmit bit 4 TMB4A asserted.
b Both TMB3A and TMB4A asserted.
TMB A 56 TMB5A, TMB6A 5 M
IRRORED
B
ITS
channel A transmit bit 5 TMB5A asserted.
6 M
IRRORED
B
ITS
channel A transmit bit 6 TMB6A asserted.
b Both TMB5A and TMB6A asserted.
TMB A 78 TMB7A, TMB8A 7 M
IRRORED
B
ITS
channel A transmit bit 7 TMB7A asserted.
8 M
IRRORED
B
ITS
channel A transmit bit 8 TMB8A asserted.
b Both TMB7A and TMB8A asserted.
RMB A 12 RMB1A, RMB2A 1 M
IRRORED
B
ITS
channel A receive bit 1 RMB1A asserted.
2 M
IRRORED
B
ITS
channel A receive bit 2 RMB2A asserted.
b Both RMB1A and RMB2A asserted.
RMB A 34 RMB3A, RMB4A 3 M
IRRORED
B
ITS
channel A receive bit 3 RMB3A asserted.
4 M
IRRORED
B
ITS
channel A receive bit 4 RMB4A asserted.
b Both RMB3A and RMB4A asserted.
RMB A 56 RMB5A, RMB6A 5 M
IRRORED
B
ITS
channel A receive bit 5 RMB5A asserted.
6 M
IRRORED
B
ITS
channel A receive bit 6 RMB6A asserted.
b Both RMB5A and RMB6A asserted.
RMB A 78 RMB7A, RMB8A 7 M
IRRORED
B
ITS
channel A receive bit 7 RMB7A asserted.
8 M
IRRORED
B
ITS
channel A receive bit 8 RMB8A asserted.
b Both RMB7A and RMB8A asserted.
TMB B 12 TMB1B, TMB2B 1 M
IRRORED
B
ITS
channel B transmit bit 1 TMB1B asserted.
2 M
IRRORED
B
ITS
channel B transmit bit 2 TMB2B asserted.
b Both TMB1B and TMB2B asserted.
TMB B 34 TMB3B, TMB4B 3 M
IRRORED
B
ITS
channel B transmit bit 3 TMB3B asserted.
4 M
IRRORED
B
ITS
channel B transmit bit 4 TMB4B asserted.
b Both TMB3B and TMB4B asserted.
TMB B 56 TMB5B, TMB6B 5 M
IRRORED
B
ITS
channel B transmit bit 5 TMB5B asserted.
6 M
IRRORED
B
ITS
channel B transmit bit 6 TMB6B asserted.
b Both TMB5B and TMB6B asserted.
TMB B 78 TMB7B, TMB8B 7 M
IRRORED
B
ITS
channel B transmit bit 7 TMB7B asserted.
8 M
IRRORED
B
ITS
channel B transmit bit 8 TMB8B asserted.
b Both TMB7B and TMB8B asserted.
RMB B 12 RMB1B, RMB2B 1 M
IRRORED
B
ITS
channel B receive bit 1 RMB1B asserted.
2 M
IRRORED
B
ITS
channel B receive bit 2 RMB2B asserted.
b Both RMB1B and RMB2B asserted.
Table 12.3 Output, Input, and Protection, and Control Element Event Report Columns (Sheet 8 of 10)
Column Heading
Corresponding
Elements (Relay
Word Bits)
Symbol Definition