Schweitzer Engineering Laboratories SEL-351-5, Instruction Manual

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4.17
Date Code 20070117
Instruction Manual SEL-351-5, -6, -7 Relay
Loss-of-Potential, Load Encroachment, and Directional Element Logic
Directional Control for Neutral Ground and Residual Ground Overcurrent Elements
Directional Element
Routing
Refer to Figure 4.4 , Figure 4.5 , Figure 4.15 , and Figure 4.16 .
The directional element outputs are routed to the forward (Relay Word bits
32GF and 32NF) and reverse (Relay Word bits 32GR and 32NR) logic points
and then on to the direction forward/reverse logic in
Figure 4.17 and
Figure 4.18 .
Loss-of-Potential
Note if all the following are true:
➤
Enable setting ELOP = Y,
➤
Global setting VSCONN = VS,
➤
A loss-of-potential condition occurs (Relay Word bit LOP
asserts),
➤
And internal enable 32IE (for channel IN current-polarized
directional element) is not asserted
then the forward logic point (Relay Word bit 32GF in Figure 4.15 and 32NF in
Figure 4.16 ) asserts to logical 1, thus, enabling the residual ground
( Figure 4.17 ) and neutral ground ( Figure 4.18 ) overcurrent elements that are
set direction forward (with settings DIR1 = F, DIR2 = F, etc.). These direction
forward overcurrent elements effectively become nondirectional and provide
overcurrent protection during a loss-of-potential condition.
If global setting VSCONN = 3V0 and group setting ELOP = Y, the LOP
condition will not cause the forward directional outputs to assert when either
directional element enable 32VE or 32NE is asserted, as shown at the top of
Figure 4.15 and Figure 4.16 . In this situation, the elements that are enabled by
signals 32VE and 32NE are still able to operate reliably during a loss-of-
potential condition, so there is no need to force the forward outputs to assert.
However, when 32VE or 32NE are not asserted, a standing LOP condition will
force the forward outputs to assert continuously. Consider this when
determining residual- and neutral-ground overcurrent element pickup settings
and time delay settings, so that “load conditions” do not cause a forward-set
ground directional overcurrent element to pick up and start timing.
As detailed previously in Internal Enables on page 4.13 , some or all of the
voltage-based directional elements are disabled during a loss-of-potential
condition. Thus, the overcurrent elements controlled by these voltage-based
directional elements are also disabled. However, this disable condition is
overridden for these overcurrent elements set direction forward if setting
ELOP = Y.
Refer to Figure 4.1 and accompanying text for more information on loss-of-
potential.
Direction Forward/
Reverse Logic
Refer to Figure 4.4 , Figure 4.5 , Figure 4.17 , and Figure 4.18 .
The forward (Relay Word bit 32GF in Figure 4.17 and 32NF in Figure 4.18 )
and reverse (Relay Word bit 32GR in Figure 4.17 and 32NR in Figure 4.18 )
logic points are routed to the different levels of overcurrent protection by the
level direction settings DIR1 through DIR4.
Table 4.4 shows the overcurrent elements that are controlled by each level
direction setting. Note in Table 4.4 that all the time-overcurrent elements
(51_T elements) are controlled by the DIR1 level direction setting.