SyncFlash Operation
MOTOROLA
SDRAM Memory Controller
24-65
24.8.6 SDRAM Memory Refresh
SDRAM memory specifications generally specify an interval during which all rows in the device must be
refreshed. The memory refresh requirements are outlined in Table 24-48. The SDRAM Controller refresh
rate (SREFR field of the Control Register) is programmable to meet these varying requirements. Refresh
must be enabled prior to storing data in the memory.
NOTE:
The memory data sheet must always be consulted to determine the correct
refresh interval and array architecture (number of rows). Refresh clock
rates other the nominal value require recalculation of the value to be
programmed into REFR.
24.9 SyncFlash Operation
Micron SyncFlash memories are 3 V electrically sector-erasable, non-volatile memories architected to
comply with the SDRAM interface specifications. With few exceptions, they are capable of matching all
SDRAM operating modes.
24.9.1 SyncFlash Reset Initialization
SyncFlash initialization is considerably more straightforward than SDRAM. The SyncFlash sequence is:
1. Apply power to Vcc, VccQ, and VccP simultaneously.
2. Apply clock.
3. After clock is stable, transition RESET_SF from low to high.
4. Maintain power, stable clock, and RESET_SF high for minimum of 100
µ
s.
5. Initialization is now complete.
The SDRAM Controller asserts RESET_SF low anytime sd_rst is asserted. The 200
µ
s delay between the
negation of sd_rst and negation of m_rst easily meets the 100
µ
s stabilization requirement of the
SyncFlash.
Table 24-48. SDRAM Memory Refresh
Device
Size
Array Size
Refresh
Interval
Refresh Rate
Requirement
SREFR
Value
64 Mbit
4096 rows
64 ms
1 row every 15.6 µs
2 rows refreshed during
each 32 kHz clock
10
128 Mbit
4096 rows
64 ms
1 row ever 15.6 µs
2 rows refreshed during
each 32 kHz clock
10
256 Mbit
8192 rows
64 ms
1 row every 7.8 µs
4 rows refreshed during
each 32 kHz clock
11
Summary of Contents for DragonBall MC9328MX1
Page 68: ...1 12 MC9328MX1 Reference Manual MOTOROLA Introduction ...
Page 86: ...2 18 MC9328MX1 Reference Manual MOTOROLA Signal Descriptions and Pin Assignments ...
Page 116: ...3 30 MC9328MX1 Reference Manual MOTOROLA Memory Map ...
Page 126: ...4 10 MC9328MX1 Reference Manual MOTOROLA ARM920T Processor ...
Page 160: ...8 8 MC9328MX1 Reference Manual MOTOROLA System Control ...
Page 272: ...13 32 MC9328MX1 Reference Manual MOTOROLA DMA Controller ...
Page 281: ...Programming Model MOTOROLA Watchdog Timer Module 14 9 ...
Page 282: ...14 10 MC9328MX1 Reference Manual MOTOROLA Watchdog Timer Module ...
Page 300: ...15 18 MC9328MX1 Reference Manual MOTOROLA Analog Signal Processor ASP ...
Page 438: ...18 16 MC9328MX1 Reference Manual MOTOROLA Serial Peripheral Interface Modules SPI 1 and SPI 2 ...
Page 478: ...19 40 MC9328MX1 Reference Manual MOTOROLA LCD Controller ...
Page 574: ...21 32 MC9328MX1 Reference Manual MOTOROLA Memory Stick Host Controller MSHC Module ...
Page 598: ...23 16 MC9328MX1 Reference Manual MOTOROLA Real Time Clock RTC ...
Page 670: ...24 72 MC9328MX1 Reference Manual MOTOROLA SDRAM Memory Controller ...
Page 726: ...25 56 MC9328MX1 Reference Manual MOTOROLA SmartCard Interface Module SIM ...
Page 736: ...26 10 MC9328MX1 Reference Manual MOTOROLA General Purpose Timers ...
Page 854: ...29 18 MC9328MX1 Reference Manual MOTOROLA I2C Module ...
Page 900: ...30 46 MC9328MX1 Reference Manual MOTOROLA Synchronous Serial Interface SSI ...
Page 942: ...32 26 MC9328MX1 Reference Manual MOTOROLA GPIO Module and I O Multiplexer IOMUX ...