Motorola DragonBall MC9328MX1, Reference Manual

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Programming Model
MOTOROLA Phase-Locked Loop and Clock Controller 12-11
12.5.3.2 MCU PLL and System Clock Control Register 1
The MCU PLL and System Clock Control Register 1 (MPCTL1) is a 32-bit register that directs the
operation of the on-chip MCU PLL. The MPCTL1 control bits are described in Table 12-10.
12.5.4 Generation of 48 MHz Clocks
The USB interface clock (CLK48M) is used internally by the USB module. Its frequency is set to 48 MHz
using the PLL control registers assuming a default input clock frequency 16.384 MHz. This input clock
frequency assumes a 32 kHz crystal input.
The predivider/multiplier output depends on the input clock frequency as shown in Table 12-11.
MPCTL1 MCU PLL and System Clock Control Register 1
Addr
0x0021B008
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TYPE r r r r r r r r r r r r r r r r
RESET
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x0000
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRMO
TYPE r r r r r r r r r rw r r r r r r
RESET
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x0000
Table 12-10. MCU PLL and System Clock Control Register 1 Description
Name Description Settings
Reserved
Bits 31–7 Reserved—These bits are reserved and should read 0.
BRMO
Bit 6
BRM Order —Controls the BRM order. The first order BRM is used if a
MF fractional part is both more than 1/10 and less than 9/10. In other
cases, the second order BRM is used. The BRMO bit is cleared by a
hardware reset. A delay of reference cycles is required between two write
accesses to BRMO.
0 = BRM contains
first order
1 = BRM contains
second order
Reserved
Bits 5–0 Reserved—These bits are reserved and should read 0.
Table 12-11. System PLL Multiplier Factor
PLL
Input
Frequency
Premultiplier PD MFD MFI MFN
PLL
Output
Frequency
USBDIV
USB
Clock
Frequency
32 kHz 16.384 MHz 1 63 5 55 96 MHz 2 48 MHz
The default setting exception is USB_DIV. The user must program this to 010.