Motorola DragonBall MC9328MX1, Reference Manual

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28-4 MC9328MX1 Reference Manual MOTOROLA
USB Device Port
• Requires no microcontroller or firmware support
• Provides USB device state handling
• Enables clock and data recovery from USB
• Supports bit stripping and bit stuffing functions
• Supports CRC5 checking and CRC16 generation and checking
• Provides serial to parallel data conversion
• Maintains data synchronization bits (DATA0/DATA1) toggle bits
• Understands and decodes standard USB commands to endpoint 0
28.2.2 Synchronization and Transaction Decode
The synchronization and transaction decode block performs two functions:
• It synchronizes the front-end logic timing to the UDC’s application bus timing. The front-end logic
is targeted for a maximum of 96 MHz operation, while the UDC’s application bus runs at 12 MHz
for full-speed devices.
• The synchronization layer contains a transaction decoder. The application bus protocol is very
simple and makes no distinction between RAM, FIFO, and configuration access. The decoder
examines the type of transaction requested by the UDC and generates control signals appropriate to
that transaction type (RAM, FIFO, and so on).
The transaction decoder ensures that all packet transfers occur in units of the maximum packet size for the
selected endpoint. This block decodes the buffer address from the UDC’s application bus to determine the
maximum packet size for the current endpoint. It also looks at bytes free and end-of-frame (EOF)
information from the FIFO module to determine when a packet transfer occurs.
In general, all transfers are of the maximum packet size
except
when all of these conditions apply:
• The endpoint is isochronous
• The transmit FIFO has less than the maximum packet size worth of data available
• There is an end-of-frame indicator in the FIFO
The transaction decoder also handles hardware retries of USB packets containing errors. The hardware is
capable of retransmitting an IN packet to the host or discarding an OUT packet from the host.
The synchronization and transaction decode section contains logic related to the UDC module’s clock
enable. The UDC module is designed with low-power operation in mind. It includes a gated clock and part
of the enable logic for that clock
with low-power operation in mind.
28.2.3 Endpoint FIFO Architecture
The USB protocol has some specialized requirements that affect FIFO implementation and essentially
require one FIFO per USB endpoint. The USB host can access any endpoint on the function in any order,
even the same endpoint in back-to-back transactions, however there is a latency requirement that means
the USB device must respond to the USB host within a certain number of USB bit times or the device loses
its time slice on the USB until some point in the future. To achieve maximum USB bandwidth use, the
USB device must provide full packets of data to the USB host immediately on request and receive full
packets from the host on request. This requirement results in one FIFO per USB endpoint.
Depending on the traffic requirements, the FIFO sizes are adjustable to support double buffering.
Typically, bulk and isochronous endpoints are double buffered, while interrupt and control endpoints
usually are single buffered.